KR100419901B1 - Method of fabricating semiconductor device having dual damascene interconnection - Google Patents
Method of fabricating semiconductor device having dual damascene interconnection Download PDFInfo
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- KR100419901B1 KR100419901B1 KR10-2001-0031455A KR20010031455A KR100419901B1 KR 100419901 B1 KR100419901 B1 KR 100419901B1 KR 20010031455 A KR20010031455 A KR 20010031455A KR 100419901 B1 KR100419901 B1 KR 100419901B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 230000009977 dual effect Effects 0.000 title abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 77
- 239000010410 layer Substances 0.000 claims abstract description 73
- 239000011229 interlayer Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000003321 amplification Effects 0.000 claims description 6
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 21
- 239000000463 material Substances 0.000 abstract description 15
- 239000002253 acid Substances 0.000 abstract description 7
- 238000006555 catalytic reaction Methods 0.000 abstract description 2
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract
듀얼 다마신 배선을 가지는 반도체 소자의 제조방법을 제공한다. 이 방법은, 노광된 포토레지스트에서 발생한 산의 촉매작용을 억제할 수 있는 물질막을 사용하여 포토레지스트를 잔류시킴으로써, 잔류된 포토레지스트를 식각마스크로 사용한다. 먼저, 하부 배선이 형성된 반도체 기판 상에 식각저지막 및 층간절연막을 차례로 형성한다. 이어서, 층간절연막을 패터닝하여 하부 배선 상에 식각저지막이 노출된 비아홀을 형성하고, 비아홀을 가로질러 상기 층간절연막을 노출시킨 제2 포토레지스트 패턴(32)을 형성한다. 이 때, 비아홀 내에서 식각저지막 상부에 포토레지스트가 남는다. 계속해서, 제2 포토레지스트 패턴 및 잔존한 포토레지스트를 식각마스크로 사용하여 층간절연막의 상부를 일부식각하여 비아홀을 지나는 배선홈을 형성한다. 제2 포토레지스트 패턴 및 비아홀 내에 잔존한 포토레지스트를 제거하고, 비아홀 내에 노출된 식각저지막을 제거하여 하부배선을 노출시킨다.A method of manufacturing a semiconductor device having dual damascene wiring is provided. This method uses the remaining photoresist as an etch mask by leaving the photoresist with a material film capable of inhibiting the catalysis of acid generated in the exposed photoresist. First, an etch stop film and an interlayer insulating film are sequentially formed on the semiconductor substrate on which the lower wiring is formed. Subsequently, the interlayer insulating layer is patterned to form a via hole in which an etch stop layer is exposed on the lower wiring, and a second photoresist pattern 32 exposing the interlayer insulating layer is formed across the via hole. At this time, photoresist remains on the etch stop layer in the via hole. Subsequently, the upper portion of the interlayer insulating film is partially etched using the second photoresist pattern and the remaining photoresist as an etching mask to form wiring grooves passing through the via holes. The second photoresist pattern and the photoresist remaining in the via hole are removed, and the etch stop layer exposed in the via hole is removed to expose the lower wiring.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 더 구체적으로 듀얼 다마신 배선을 가지는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having dual damascene wiring.
반도체 소자의 다층배선을 형성하는 방법은 다마신(damascene) 기술을 포함한다. 다마신 기술 중 하부배선 또는 반도체 기판과 접촉하는 비아홀(via hole)과 배선이 형성된 배선홈을 절연층에 형성한 후, 비아홀과 배선홈에 도전막을 동시에 충전하여 배선과 비아를 형성하는 듀얼 다마신 기술(dual damascene technology)이 있다. 상기 듀얼 다마신 기술은 공정을 간략화하고, 공정시간을 단축하여 반도체 소자의 제조비용을 절감시키는 장점을 가지고 있다.The method of forming a multilayer wiring of a semiconductor device includes a damascene technique. Dual damascene is a damascene technology in which a via hole and a wiring groove in which wiring is in contact with a lower substrate or a semiconductor substrate are formed in an insulating layer, and then the wiring and via are formed by simultaneously filling the via hole and the wiring groove with a conductive film. There is a dual damascene technology. The dual damascene technology has the advantage of simplifying the process and shortening the process time to reduce the manufacturing cost of the semiconductor device.
도 1 내지 도 3은 종래의 듀얼 다마신 배선 형성방법을 설명하기 위한 공정단면도들이다.1 to 3 are cross-sectional views illustrating a conventional method for forming a dual damascene wiring.
도 1에 도시된 바와 같이, 하부배선(10)이 형성된 반도체 기판(100) 상에 식각저지막(11) 및 층간절연막(12)을 차례로 형성한다. 상기 식각저지막(11)은 통상적으로 SiC 또는 SiN을 사용하여 형성한다. 상기 층간절연막(12)은 반도체 소자의 신호전송 속도를 향상시키기 위하여 낮은 유전율을 가지는 물질막으로 형성한다. 이러한 물질막으로 SiOC:H 막이 상기 층간절연막(12)에 적용된다.As illustrated in FIG. 1, an etch stop layer 11 and an interlayer insulating layer 12 are sequentially formed on the semiconductor substrate 100 on which the lower wiring 10 is formed. The etch stop layer 11 is typically formed using SiC or SiN. The interlayer insulating film 12 is formed of a material film having a low dielectric constant in order to improve the signal transmission speed of the semiconductor device. As the material film, a SiOC: H film is applied to the interlayer insulating film 12.
상기 층간절연막(12) 상에 상기 하부배선(10)을 노출시키는 비아홀을 형성하기 위하여 제1 포토레지스트 패턴(14)를 형성하고, 상기 제1 포토레지스트 패턴(14)를 식각마스크로 사용하여 비아홀(16)을 형성한다. 이때, 상기 식각저지막(11)은 상기 비아홀(16)을 형성하는 동안 상기 하부배선(10)이 식각되는것을 방지하여 준다. 그러나, 도시된 바와 같이, 층간절연막(12)으로 사용하는 SiOC:H막과 식각저지막(11)으로 사용하는 SiC 또는 SiN막의 식각선택비가 낮아 상기 식각저지막(11)의 상부의 일부가 함께 식각된다.A first photoresist pattern 14 is formed on the interlayer insulating layer 12 to form a via hole exposing the lower interconnection 10, and the first photoresist pattern 14 is used as an etching mask. (16) is formed. In this case, the etch stop layer 11 prevents the lower wiring 10 from being etched while the via hole 16 is formed. However, as shown, the etching selectivity of the SiOC: H film used as the interlayer insulating film 12 and the SiC or SiN film used as the etch stop film 11 is low, so that a part of the upper portion of the etch stop film 11 is together. Etched.
도 2 및 도 3을 참조하면, 상기 제1 포토레지스트 패턴(14)를 제거하고, 상기 비아홀(16)을 가로지르는 배선홈(도 3의 20)을 형성하기 위한 제2 포토레지스트 패턴(18)을 형성한다. 이어서, 상기 제2 포토레지스트 패턴(18)을 식각 마스크로 사용하여 상기 비아홀(16)을 가로지르는 배선홈(20)을 형성한다. 이 때, 상술한 바와 같이 식각저지막(11) 및 층간절연막(12)의 식각선택비가 낮기 때문에 상기 식각저지막(11)이 함께 제거된다. 통상적으로 상기 비아홀(16)을 형성할 때 보다 배선홈(20)을 형성하기 위하여 식각되는 영역이 넓다. 이로 인해, 상기 식각저지막(11)이 과식각되는 양 또한 많아져 상기 하부배선(10)이 노출되어 과식각되는 문제를 일으킨다. 따라서, 저유전율을 가지는 물질인 SiOC:H를 사용하여 층간절연막을 형성하기 위해서는 상술한 문제점을 해결할 수 있는 방법이 요구된다.2 and 3, the second photoresist pattern 18 for removing the first photoresist pattern 14 and forming a wiring groove (20 in FIG. 3) crossing the via hole 16. To form. Subsequently, the wiring groove 20 crossing the via hole 16 is formed using the second photoresist pattern 18 as an etching mask. At this time, since the etching selectivity of the etch stop film 11 and the interlayer insulating film 12 is low as described above, the etch stop film 11 is removed together. In general, the area to be etched to form the wiring groove 20 is wider than when the via hole 16 is formed. As a result, the amount of the etch stop layer 11 is overetched also increases, causing the lower wiring 10 to be exposed and overetching. Therefore, in order to form an interlayer insulating film using SiOC: H, which is a material having a low dielectric constant, a method capable of solving the above-described problems is required.
본 발명의 목적은 상술한 종래기술의 문제점을 해결하기 위하여 SiOC:H를 사용하여 층간절연막을 형성하였을 경우, 다마신 배선을 형성하기위하여 식각공정을 실시하는 동안 하부배선이 과식각되는 것을 방지할 수 있는 방법을 제공하는 데 있다.An object of the present invention is to prevent the over-etching of the lower wiring during the etching process to form the damascene wiring when the interlayer insulating film is formed using SiOC: H to solve the above-mentioned problems of the prior art. To provide a way to do this.
도 1 내지 도 3은 종래의 듀얼 다마신 배선 형성방법을 설명하기 위한 공정단면도들이다.1 to 3 are cross-sectional views illustrating a conventional method for forming a dual damascene wiring.
도 4 내지 도 7은 본 발명의 제1 실시예에 따른 듀얼 다마신 배선 형성방법을 설명하기 위한 공정단면도들이다.4 to 7 are process cross-sectional views illustrating a method of forming dual damascene wiring according to a first embodiment of the present invention.
도 8 내지 도 10은 본 발명의 제2 실시예에 따른 듀얼 다마신 배선 형성방법을 설명하기 위한 공정단면도들이다.8 to 10 are cross-sectional views illustrating a method of forming a dual damascene wiring according to a second exemplary embodiment of the present invention.
※ 도면의 주요부분에 대한 부호의 설명 ※※ Explanation of code about main part of drawing ※
100: 반도체 기판 10, 20: 하부 도전막100: semiconductor substrate 10, 20: lower conductive film
11, 23, 42: 식각저지막 12, 26: 층간절연막11, 23, 42: etch stop film 12, 26: interlayer insulating film
14, 28: 제1 포토레지스트 패턴 16, 30: 비아 홀14, 28: first photoresist pattern 16, 30: via hole
18, 32: 제2 포토레지스트 패턴 20, 36: 배선 홈18, 32: second photoresist pattern 20, 36: wiring groove
22: 제1 절연막 24: 제2 절연막22: first insulating film 24: second insulating film
34, 44: 잔존 포토레지스트34, 44: remaining photoresist
상기 목적을 달성하기 위하여 본 발명은, 하부 배선이 형성된 반도체 기판상에 식각저지막 및 층간절연막을 차례로 형성한다. 상기 식각저지막은 포토레지스트와 반응하여, 포토레지스트 내의 화학증폭작용을 억제하여 현상용액에 녹지않는 결합구조를 유지하도록 하는 물질막으로 형성한다. 본 발명의 실시예에서 상기 식각저지막은 질소(N)가 도우핑된 실리콘 카바이드(N-doped SiC) 또는 질소(N)가 도우핑된 실리콘 옥시카바이드(N-doped SiOC:H)를 사용하는 것이 바람직하다. 계속해서, 상기 층간절연막을 패터닝하여 상기 하부 배선 상에 상기 식각저지막이 노출된 비아홀을 형성한다. 이어서, 상기 비아홀을 가로질러 상기 층간절연막을 노출시킨 포토레지스트 패턴을 형성한다. 이 때, 상기 비아홀 내에 상기 식각저지막과 반응하여 상기 식각저지막 상부에 포토레지스트가 잔존한다. 상기 배선홈을 형성하기 위한 포토레지스트는 화학증폭형 포토레지스트로 형성하는 것이 바람직하다. 상기 화학증폭형 포토레지스트는 PAG(photoacid generator)를 포함하고 있어 노광공정에서 빛을 받은 레지스트는 산을 발생시킨다. 이 때 발생한 산이 촉매역할을 하여 포토레지스트의 결합구조가 현상용액에 녹기쉬운 구조로 변경되어 패턴이 형성된다. 본 발명의 실시예에서, 상기 비아홀 하부에 상기 식각저지막과 접촉한 포토레지스트는 노광공정시 산을 발생하게 되지만 상기 식각저지막으로 사용된 물질막 내에 도우핑된 질소(N)에 의해 산의 촉매작용이 억제된다. 그 결과, 노광된 포토레지스트를 제거하여도 상기 식각저지막과 접하는 인접지역의 포토레지스트는 제거되지 않고 남게된다. 계속해서, 상기 포토레지스트 패턴 및 상기 잔존한 포토레지스트를 식각마스크로 사용하여 상기 층간절연막의 상부를 일부식각하여 상기 비아홀을 지나는 배선홈을 형성한다. 상기 포토레지스트 패턴 및 상기 비아홀 내에 잔존한 포토레지스트를 제거한 후, 상기 비아홀 내에 노출된 식각저지막을 제거하여 상기 하부배선의 상부를 노출시킨다.In order to achieve the above object, the present invention sequentially forms an etch stop film and an interlayer insulating film on a semiconductor substrate on which lower wirings are formed. The etch stop layer is formed of a material layer that reacts with the photoresist and suppresses chemical amplification in the photoresist to maintain a bonding structure insoluble in the developing solution. In the embodiment of the present invention, the etch stop layer may use N-doped silicon carbide (N-doped SiC) or nitrogen-doped silicon oxycarbide (N-doped SiOC: H). desirable. Subsequently, the interlayer insulating layer is patterned to form via holes in which the etch stop layer is exposed. Subsequently, a photoresist pattern exposing the interlayer insulating film is formed across the via hole. At this time, the photoresist remains on the etch stop layer in reaction with the etch stop layer in the via hole. The photoresist for forming the interconnection grooves is preferably formed of a chemically amplified photoresist. The chemically amplified photoresist includes a photoacid generator (PAG), the resist that receives light in the exposure process generates an acid. At this time, the generated acid acts as a catalyst to change the bonding structure of the photoresist into a structure that is easily soluble in the developing solution, thereby forming a pattern. In an embodiment of the present invention, the photoresist in contact with the etch stop layer under the via hole generates an acid during the exposure process, but the acid is prevented by nitrogen (N) doped in the material film used as the etch stop layer. Catalysis is inhibited. As a result, even if the exposed photoresist is removed, the photoresist in the adjacent region in contact with the etch stop layer is left without being removed. Subsequently, the upper portion of the interlayer insulating layer is partially etched using the photoresist pattern and the remaining photoresist as an etching mask to form a wiring groove passing through the via hole. After removing the photoresist pattern and the photoresist remaining in the via hole, the etch stop layer exposed in the via hole is removed to expose the upper portion of the lower wiring.
상기 식각저지막은 이중의 적층구조로 형성할 수 있다. 이 경우, 상기 비아홀을 형성하기 위하여 상기 층간절연막을 식각하였을 때, 상기 비아홀의 바닥측벽에 상기 반응 물질막이 노출된다. 따라서, 상기 노출된 반응 물질막과 포토레지스트가 반응하여 상기 포토레지스트가 노광 및 현상공정을 실시하더라도 제거되지 않고 상기 비아홀의 바닥에 잔존한다.The etch stop layer may be formed in a double stacked structure. In this case, when the interlayer insulating film is etched to form the via hole, the reactive material film is exposed on the bottom side wall of the via hole. Thus, even if the exposed reactive material film and the photoresist react to perform the exposure and development processes, the photoresist is not removed but remains at the bottom of the via hole.
이하 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세하게 설명하도록 한다. 그러나, 본 발명은 여기서 설명되어지는 실시예에 한정되지 않고 다른 형태로 구체화될 수도 있다. 오히려, 여기서 소개되는 실시예들은 개시된 내용이 철저하고 완전해질 수 있도록 그리고 당업자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위해 제공되어지는 것이다. 도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장되어진 것이다. 또한, 층이 다른 층 또는 기판 상에 있다고 언급되어지는 경우에 그것은 다른 층 또는 기판 상에 직접 형성될 수 있거나 또는 그들 사이에 제3의 층이 개재될 수도 있다. 명세서 전체에 걸쳐서 동일한 참조번호들은 동일한 구성요소들을 나타낸다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Also, if it is mentioned that the layer is on another layer or substrate, it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.
도 4 내지 도 7은 본 발명의 제1 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도들이다.4 through 7 are process cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 4를 참조하면, 하부배선(20)이 형성된 반도체 기판(100)에 제1 절연막(22) 및 제2 절연막(24)이 차례로 적층된 식각저지막(23)을 형성하고, 계속해서 층간절연막(26)을 형성한다. 상기 층간절연막(26)은 반도체 소자의 신호전송 속도를 향상시키기 위하여 유전율이 낮은 물질막으로써, 예컨대, SiOC:H막으로 형성하는 것이 바람직하다. 종래기술과 다른 본 발명의 특징은 상기 식각저지막(23)에 포토레지스트와 반응하여 노광된 포토레지스가 현상되지 않도록 하는 반응물질막을 적어도 한 층 포함하는 것이다. 본 발명의 제1 실시예에서 상기 식각저지막(23)은 SiC 또는 SiN으로 형성한 제1 절연막(22) 및 반응물질막에 해당하는 제2 절연막(22)으로 구성된다. 상기 반응물질막은 예컨대, N-doped SiOC:H막으로 형성하는 것이 바람직하다. 상기 N-doped SiOC:막은 질소가 도핑되어 있기 때문에 포토레지스트의 노광지역에 발생한 산과 반응하여 산의 광학적 증폭효과를 약화시켜 포토레지스가 현상액에 녹는 결합구조로 변하는 것을 막아준다. 이에 따라, 상기 반응물질막과 반응한 부분의 포토레지스트는 현상과정에서 현상되지 않고 잔류한다.Referring to FIG. 4, an etch stop layer 23 in which the first insulating layer 22 and the second insulating layer 24 are sequentially stacked is formed on the semiconductor substrate 100 on which the lower wiring 20 is formed. (26) is formed. The interlayer insulating layer 26 is formed of a material having a low dielectric constant, for example, an SiOC: H film, in order to improve the signal transmission speed of the semiconductor device. A feature of the present invention that is different from the prior art is that the etch stop film 23 includes at least one reactive material film that reacts with the photoresist so that the exposed photoresist is not developed. In the first embodiment of the present invention, the etch stop layer 23 includes a first insulating layer 22 formed of SiC or SiN and a second insulating layer 22 corresponding to the reactive material layer. The reactant film is preferably formed of, for example, an N-doped SiOC: H film. Since the N-doped SiOC: film is doped with nitrogen, the N-doped SiOC film reacts with the acid generated in the exposure region of the photoresist, thereby weakening the optical amplification effect of the acid, thereby preventing the photoresist from changing to a bonding structure in which the developer is dissolved in the developer. Accordingly, the photoresist of the portion reacted with the reactant film remains undeveloped in the developing process.
계속해서, 상기 층간절연막(26) 상에 상기 하부도선(20)을 노출시키는 비아홀을 형성하기 위한 제1 포토레지스트 패턴(28)을 형성한다. 상기 제1 포토레지스트 패턴(28)을 식각 마스크로 사용하여 상기 층간절연막(26) 및 상기 제2 절연막(24)를 차례로 식각하여 비아홀(30)을 형성한다. 그 결과, 상기 비아홀(30)의 바닥측벽(bottom sidewall)에 상기 제2 절연막(24)이 노출된다.Subsequently, a first photoresist pattern 28 is formed on the interlayer insulating layer 26 to form a via hole exposing the lower conductive line 20. The via hole 30 is formed by sequentially etching the interlayer insulating layer 26 and the second insulating layer 24 using the first photoresist pattern 28 as an etching mask. As a result, the second insulating layer 24 is exposed on the bottom sidewall of the via hole 30.
도 5를 참조하면, 상기 비아홀을 형성하기 위한 제1 포토레지스트 패턴(28)을 제거하고, 상기 층간절연막(26) 상에 포토레지스트를 형성한다. 이어서, 상기 포토레지스트를 선택적으로 노광하여 상기 층간절연막(26) 상에 상기 비아홀을 지나는 배선홈을 형성하기 위한 제2 포토레지스트 패턴(32)을 형성한다. 상기 제2 포토레지스트 패턴(32)는 상기 비아홀을 가로질러 상기 층간절연막(26)의 상부를 노출시킨다. 이 때, 상기 비아홀(30) 내부의 포토레지스트도 노광되는 영역에 포함되지만 상기 비아홀(30) 내에 노출된 상기 제2 절연막(24)이 포토레지스트의 화학증폭작용을 억제하여 상기 비아홀(30) 바닥에 포토레지스트가 남는다. 따라서, 도시된 바와 같이, 상기 제2 포토레지스트 패턴(32)를 형성하였을 때 상기 비아홀(30)의 바닥에 잔존 포토레지스트(34)이 상기 노출된 제1 절연막(22)를 덮는다.Referring to FIG. 5, the first photoresist pattern 28 for forming the via hole is removed and a photoresist is formed on the interlayer insulating layer 26. Subsequently, the photoresist is selectively exposed to form a second photoresist pattern 32 on the interlayer insulating layer 26 to form a wiring groove passing through the via hole. The second photoresist pattern 32 exposes an upper portion of the interlayer insulating layer 26 across the via hole. In this case, the photoresist inside the via hole 30 is also included in the exposed area, but the second insulating film 24 exposed in the via hole 30 suppresses chemical amplification of the photoresist, thereby lowering the bottom of the via hole 30. Photoresist remains. Accordingly, when the second photoresist pattern 32 is formed, the remaining photoresist 34 covers the exposed first insulating layer 22 at the bottom of the via hole 30.
도 6을 참조하면, 상기 제2 포토레지스트 패턴(32) 및 상기 잔존한 포토레지스트(34)를 식각마스크로 사용하여, 상기 층간절연막(26)의 상부를 일부식각하여 상기 비아홀(30)을 가로지르는 배선홈(36)을 형성한다. 따라서, 종래기술과 달리 본 발명은, 상기 배선홈(36)을 형성하는 동안 상기 비아홀(30)의 바닥에 노출된 식각저지막(23)은 잔존 포토레지스트(34)에 의해 보호한다. 따라서, 과식각에 의해 상기 하부배선(10)이 식각되는 것이 방지된다.Referring to FIG. 6, by using the second photoresist pattern 32 and the remaining photoresist 34 as an etching mask, the upper portion of the interlayer insulating layer 26 is partially etched to cross the via hole 30. Forming wiring grooves 36 are formed. Therefore, unlike the prior art, the present invention protects the etch stop layer 23 exposed to the bottom of the via hole 30 by the remaining photoresist 34 while forming the interconnection groove 36. Therefore, the lower wiring 10 is prevented from being etched by over etching.
도 7을 참조하면, 상기 제2 포토레지스트 패턴(32) 및 상기 잔존 포토레지스트(34)를 제거한다. 이어서, 상기 비아홀(30) 바닥에 노출된 제1 절연막(26)을 제거하여 상기 하부배선(10)을 노출시킨다.Referring to FIG. 7, the second photoresist pattern 32 and the remaining photoresist 34 are removed. Subsequently, the first insulating layer 26 exposed at the bottom of the via hole 30 is removed to expose the lower wiring 10.
이에 더하여 도시하지는 않았지만, 상기 하부배선(10)이 노출된 반도체 기판의 전면에 상기 비아홀 및 상기 배선홈을 채우는 도전막을 형성하고 평탄화하여 비아 콘택플러그 및 배선층을 형성하는 이후 공정을 통상적인 방법을 사용하여 진행한다.In addition, although not shown, a process of forming a via contact plug and a wiring layer by forming and planarizing a conductive film filling the via hole and the wiring groove on the entire surface of the semiconductor substrate where the lower wiring 10 is exposed is used. Proceed by
도 8 내지 도 10은 본 발명의 제2 실시예를 설명하기 위한 공정단면도이다.8 to 10 are process cross-sectional views for explaining the second embodiment of the present invention.
도 8을 참조하면, 본 발명의 제2 실시예에서는 상술한 제1 실시예와 달리 식각저지막(42)를 단일층으로 형성한다. 상기 식각저지막(42)은 층간절연막(36)과 식각선택비를 가지고, 제1 실시예에서 설명한 것과 같이 포토레지스트와 반응하는 물질막으로써, 예컨대, N-doped SiC를 사용하여 형성하는 것이 바람직하다. 본 발명의 제1 실시예와 마찬가지로, 제1 포토레지스트 패턴(28)을 형성한 후, 상기 제1 포토레지스트 패턴(28)을 식각마스크로 사용하여 상기 식각저지막(42)이 노출되도록 층간절연막(26)을 식각하여 비아홀(30)을 형성한다.Referring to FIG. 8, in the second embodiment of the present invention, the etch stop layer 42 is formed as a single layer, unlike the above-described first embodiment. The etch stop layer 42 has an etch selectivity with the interlayer insulating layer 36 and is formed of a material layer reacting with the photoresist as described in the first embodiment, for example, using N-doped SiC. Do. As in the first embodiment of the present invention, after the first photoresist pattern 28 is formed, the interlayer insulating layer 42 is exposed to expose the etch stop layer 42 by using the first photoresist pattern 28 as an etching mask. The 26 is etched to form the via hole 30.
도 9를 참조하면, 상기 제1 포토레지스트 패턴(28)을 제거하고, 상기 층간절연막 상에 배선홈을 형성하기 위한 제2 포토레지스트 패턴(32)를 형성한다. 이 과정에서, 상술한 제1 실시예와 유사하게 상기 비아홀(30)의 바닥에 노출된 식각저지막(42)이 포토레지스트의 화학증폭작용을 억제하여 상기 비아홀(30) 바닥에 잔존 포토레지스트(44)가 남는다. 이어서, 상기 제2 포토레지스트 패턴(32) 및 상기 잔존 포토레지스트(44)를 식각마스크로 사용하여, 상기 층간절연막(26)의 상부를 일부식각(partial etch)하여 상기 비아홀(30)을 가로지르는 배선홈(36)을 형성한다. 따라서, 상기 잔존 포토레지스트(44)에 의해 상기 하부배선(20)이 과식각되는 것이 방지된다. 계속해서, 상기 제2 포토레지스트 패턴(32) 및 상기 잔존 포토레지스트(44)를 제거하고, 상기 비아홀(30) 바닥에 노출된 식각저지막(42)를 제거하여 상기 하부배선(20)을 노출시킨다.Referring to FIG. 9, the first photoresist pattern 28 is removed and a second photoresist pattern 32 is formed on the interlayer insulating layer to form a wiring groove. In this process, similarly to the first embodiment described above, the etch stop layer 42 exposed on the bottom of the via hole 30 suppresses chemical amplification of the photoresist, thereby remaining on the bottom of the via hole 30. 44) remains. Subsequently, the upper portion of the interlayer insulating layer 26 is partially etched using the second photoresist pattern 32 and the remaining photoresist 44 as an etch mask to cross the via hole 30. The wiring groove 36 is formed. Therefore, the lower wiring 20 is prevented from being etched by the remaining photoresist 44. Subsequently, the second photoresist pattern 32 and the remaining photoresist 44 are removed, and the etch stop layer 42 exposed on the bottom of the via hole 30 is removed to expose the lower interconnection 20. Let's do it.
이어서, 도시하지는 않았지만 상술한 실시예와 동일하게 통상적인 방법을 사용하여 이후공정을 진행한다.Subsequently, although not shown, a subsequent process is performed using a conventional method similarly to the above-described embodiment.
상술한 바와 같이 본 발명에 따르면, 포토레지스트와 반응하여 포토레지스트가 현상액에 녹는 결합구조로 변형되는 것을 막아주는 물질막을 식각저지막으로 사용함으로써, 듀얼 다마신 배선을 형성하는 동안 하부배선이 과식각되는 것을 방지할 수 있다. 또한, 하부의 물질막과 식각선택비가 우수하지 않더라도 낮은 정전용량을 가지는 물질막을 층간절연막으로 사용할 수 있어 소자의 신호전송속도를 향상시킬 수 있다.As described above, according to the present invention, by using a material film as an etch stop layer that reacts with the photoresist and prevents the photoresist from deforming into a bonding structure soluble in the developer, the lower wiring is overetched during the formation of the dual damascene wiring. Can be prevented. In addition, even if the underlying material film and the etching selectivity are not excellent, a material film having a low capacitance can be used as the interlayer insulating film, thereby improving the signal transmission speed of the device.
Claims (6)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5702982A (en) * | 1996-03-28 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits |
| KR19990052529A (en) * | 1997-12-22 | 1999-07-15 | 윤종용 | Method for forming conductive line in semiconductor device |
| US5989997A (en) * | 1998-02-16 | 1999-11-23 | United Microelectronics Corp. | Method for forming dual damascene structure |
| WO2001001480A1 (en) * | 1999-06-30 | 2001-01-04 | Intel Corporation | Method of protecting an underlying wiring layer during dual damascene processing |
| KR20010017560A (en) * | 1999-08-12 | 2001-03-05 | 윤종용 | Method for forming dual damascene structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5702982A (en) * | 1996-03-28 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits |
| KR19990052529A (en) * | 1997-12-22 | 1999-07-15 | 윤종용 | Method for forming conductive line in semiconductor device |
| US5989997A (en) * | 1998-02-16 | 1999-11-23 | United Microelectronics Corp. | Method for forming dual damascene structure |
| WO2001001480A1 (en) * | 1999-06-30 | 2001-01-04 | Intel Corporation | Method of protecting an underlying wiring layer during dual damascene processing |
| KR20020020921A (en) * | 1999-06-30 | 2002-03-16 | 피터 엔. 데트킨 | Method of protecting an underlying wiring layer during dual damascene processing |
| KR20010017560A (en) * | 1999-08-12 | 2001-03-05 | 윤종용 | Method for forming dual damascene structure |
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