KR100405176B1 - 선택적 에스오아이 구조를 이용한 단결정 실리콘마이크로일렉트로미케니컬 시스템을 위한 절연 방법 - Google Patents
선택적 에스오아이 구조를 이용한 단결정 실리콘마이크로일렉트로미케니컬 시스템을 위한 절연 방법 Download PDFInfo
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- KR100405176B1 KR100405176B1 KR10-2001-0019656A KR20010019656A KR100405176B1 KR 100405176 B1 KR100405176 B1 KR 100405176B1 KR 20010019656 A KR20010019656 A KR 20010019656A KR 100405176 B1 KR100405176 B1 KR 100405176B1
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- Prior art keywords
- electrode
- single crystal
- film
- crystal silicon
- soi
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- 238000002955 isolation Methods 0.000 title claims description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 92
- 238000009413 insulation Methods 0.000 claims abstract description 46
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 14
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000000708 deep reactive-ion etching Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 40
- 235000012431 wafers Nutrition 0.000 description 26
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000002184 metal Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000010292 electrical insulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005459 micromachining Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76262—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Crystallography & Structural Chemistry (AREA)
- Micromachines (AREA)
- Pressure Sensors (AREA)
Abstract
Description
절연방법 | p-n 접합 | 스크림 | 트렌치 산화물 | 삼중막 | 산화막 기둥 | 본 발명 |
종횡비가 높은 구조에의 적용성 | 어려움 | 어려움 | 가능 | 가능 | 가능 | 가능 |
누설전류 | 큼 | 작음 | 작음 | 작음 | 작음 | 작음 |
기생 정전용량 | ~ 0.1 pF | ~ 1.7 pF | ~ 80 fF | ~ 1.7 pF | ~ 6 fF | ~0.26 pF |
메사 타입의 전극 구조물 | 가능 | 가능 | 어려움 | 가능 | 가능 | 가능 |
Claims (6)
- 전극이 형성되는 부분에서, 부유된 구조물이 매몰된 절연층 위에 제작된 전극 및 지지대에 의하여 지지되도록 하는 부분적인 SOI 구조를 구현한 선택적 SOI 구조를 이용한 단결정실리콘 MEMS을 위한 절연 방법에 있어서, 전극이 형성되는 부분에 에치홀을 패터닝하고, 상기 매몰 절연층의 깊이만큼 에칭하는 단계(a); 표준 SBM 공정에 의하여 상기 전극 부분 하부에서 실리콘 기판을 수평방향으로 에칭하여 전극과 전극 하부의 기판 사이의 간극인 매몰층을 정의하는 첫 번째 SBM 단계(b); 상기 단계(b)에서 정의된 매몰층을 절연막으로 채우는 매몰절연층 형성 단계(c); 및 표준 SBM 공정에 의하여 상기 단계(c)에서 형성된 매몰절연층에 전극 및 지지대를 형성하고 부유된 구조물을 구현하는 두 번째 SBM 단계(d)를 포함하는 것임을 특징으로 하는, 선택적 SOI를 이용한 단결정실리콘 MEMS을 위한 절연 방법.
- 제1항에 있어서,상기 단결정실리콘은 (111) 단결정실리콘인 것임을 특징으로 하는 선택적 SOI를 이용한 단결정실리콘 MEMS을 위한 절연 방법.
- 제1항에 있어서,상기 단계(a)에서 매몰 절연막의 깊이만큼 에칭하는 것은, 실리콘 딥 반응성 이온 식각에 의한 것임을 특징으로 하는 선택적 SOI를 이용한 단결정실리콘 MEMS을위한 절연 방법.
- 제1항에 있어서,상기 단계(a)에서 매몰 절연막의 깊이는, 전극의 두께 및 최종적으로 부유될 구조물의 희생층 깊이보다 깊어야 하는 것임을 특징으로 하는 선택적 SOI를 이용한 단결정실리콘 MEMS을 위한 절연 방법.
- 제1항에 있어서,상기 단계(c)에서 상기 절연막은, LPCVD 산화막, LPCVD 질화막, LPCVD 다결정실리콘막, 열산화막, PECVD 산화막, PECVD 질화막, PECVD TEOS막, PECVD PSG막, APCVD PSG막 중 하나 또는 이 중에서 선택된 둘 이상의 조합을 사용하는 것임을 특징으로 하는 선택적 SOI를 이용한 단결정실리콘 MEMS을 위한 절연 방법.
- 삭제
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR10-2001-0019656A KR100405176B1 (ko) | 2001-04-12 | 2001-04-12 | 선택적 에스오아이 구조를 이용한 단결정 실리콘마이크로일렉트로미케니컬 시스템을 위한 절연 방법 |
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KR10-2001-0019656A KR100405176B1 (ko) | 2001-04-12 | 2001-04-12 | 선택적 에스오아이 구조를 이용한 단결정 실리콘마이크로일렉트로미케니컬 시스템을 위한 절연 방법 |
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KR20020079040A KR20020079040A (ko) | 2002-10-19 |
KR100405176B1 true KR100405176B1 (ko) | 2003-11-12 |
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KR10-2001-0019656A KR100405176B1 (ko) | 2001-04-12 | 2001-04-12 | 선택적 에스오아이 구조를 이용한 단결정 실리콘마이크로일렉트로미케니컬 시스템을 위한 절연 방법 |
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Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100613604B1 (ko) * | 2005-01-31 | 2006-08-21 | 삼성전자주식회사 | Soi 웨이퍼를 이용한 부유 구조체 형성방법 |
KR20160120558A (ko) | 2015-04-08 | 2016-10-18 | 주식회사 스탠딩에그 | 3축 관성 측정 시스템의 제조 방법 및 이를 이용한 3축 관성 측정 시스템 |
CN116429299B (zh) * | 2023-06-12 | 2023-09-22 | 之江实验室 | 一种可晶圆***集成的压力传感芯片制造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121552A (en) * | 1997-06-13 | 2000-09-19 | The Regents Of The University Of Caliofornia | Microfabricated high aspect ratio device with an electrical isolation trench |
US6136630A (en) * | 1998-06-04 | 2000-10-24 | The Regents Of The University Of Michigan | Method of making a micromechanical device from a single crystal semiconductor substrate and monolithic sensor formed thereby |
US6159385A (en) * | 1998-05-08 | 2000-12-12 | Rockwell Technologies, Llc | Process for manufacture of micro electromechanical devices having high electrical isolation |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121552A (en) * | 1997-06-13 | 2000-09-19 | The Regents Of The University Of Caliofornia | Microfabricated high aspect ratio device with an electrical isolation trench |
US6159385A (en) * | 1998-05-08 | 2000-12-12 | Rockwell Technologies, Llc | Process for manufacture of micro electromechanical devices having high electrical isolation |
US6136630A (en) * | 1998-06-04 | 2000-10-24 | The Regents Of The University Of Michigan | Method of making a micromechanical device from a single crystal semiconductor substrate and monolithic sensor formed thereby |
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KR20020079040A (ko) | 2002-10-19 |
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