KR100400784B1 - Method for forming salicide of semiconductor device - Google Patents
Method for forming salicide of semiconductor device Download PDFInfo
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- KR100400784B1 KR100400784B1 KR10-2001-0087271A KR20010087271A KR100400784B1 KR 100400784 B1 KR100400784 B1 KR 100400784B1 KR 20010087271 A KR20010087271 A KR 20010087271A KR 100400784 B1 KR100400784 B1 KR 100400784B1
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- salicide
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 88
- 239000000463 material Substances 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 230000002265 prevention Effects 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 게이트 전극에 저저항성의 살리사이드층을 형성하고 소오스/드레인에 누설전류를 억제할 수 있는 살리사이드층을 형성하는 데 적당한 반도체 소자의 살리사이드 형성 방법 관한 것으로, 반도체 기판의 액티브 영역상에 폴리실리콘막, 살리사이드 방지막이 적층된 구조의 게이트 전극들을 형성하고, 소오스/드레인 이온 주입을 하는 단계; 상기 전면에 제 1 살리사이드 형성용 물질층을 형성하고, 열처리 공정으로 액티브 영역의 표면에 제 1 살리사이드층을 형성하는 단계; 미반응의 제 1 살리사이드 형성용 물질층을 제거한 후, 전면에 평탄화용 절연막을 증착하는 단계; 상기 평탄화된 절연층을 평탄화하여 상기 폴리실리콘막의 표면을 노출시키는 단계; 상기 전면에 제 2 살리사이드 형성용 물질층을 형성하고, 열처리 공정으로 상기 노출된 폴리실리콘막 상에 제 2 살리사이드층을 형성하는 단계; 미반응의 제 2 살리사이드 형성용 물질층을 제거한 후, 전면에 층간절연막을 증착하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a salicide of a semiconductor device suitable for forming a low resistance salicide layer on a gate electrode and forming a salicide layer capable of suppressing leakage current in a source / drain. Forming gate electrodes having a structure in which a polysilicon film and a salicide prevention film are stacked on each other, and performing source / drain ion implantation; Forming a first salicide forming material layer on the front surface and forming a first salicide layer on the surface of the active region by a heat treatment process; Removing the unreacted first salicide forming material layer and depositing a planarization insulating film on the entire surface; Planarizing the planarized insulating layer to expose a surface of the polysilicon film; Forming a second salicide forming material layer on the entire surface, and forming a second salicide layer on the exposed polysilicon layer by a heat treatment process; And removing an unreacted second salicide forming material layer, and depositing an interlayer insulating film on the entire surface.
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 특히 게이트 전극에 저저항성의 살리사이드층을 형성하고, 소오스/드레인에 누설전류를 억제할 수 있는 살리사이드층을 형성할 수 있는 반도체 소자의 살리사이드 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices. In particular, salicide formation of semiconductor devices capable of forming a low resistance salicide layer on the gate electrode and forming a salicide layer capable of suppressing leakage current in the source / drain. It is about a method.
일반적으로 고속의 반도체 소자를 구성하기 위하여 게이트 전극과 소오스/드레인 영역의 면저항과 콘택 저항을 감소시켜야 한다.In general, in order to form a high-speed semiconductor device, the sheet resistance and the contact resistance of the gate electrode and the source / drain regions should be reduced.
이를 위하여, 게이트 전극과 소오스/드레인 영역에만 선택적으로 비저항이 낮은 실리사이드(silicide)를 형성시키는 살리사이드(Self-Aligned silicide) 공정이 널리 사용되고 있다.To this end, a salicide (Self-Aligned silicide) process of forming a silicide (Siicide) having a low specific resistance selectively to the gate electrode and the source / drain region is widely used.
특히 1G 이상의 DRAM 또는 로직(logic) 및 통합 메모리 로직(Merged Memory Logic; MML) 소자 등의 게이트 특성을 향상시키기 위해 살리사이드 게이트 공정이 많이 적용되고 있다.In particular, salicide gate processes have been widely applied to improve gate characteristics of 1G DRAM or more logic and integrated memory logic (MML) devices.
이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 살리사이드층 형성 공정에 관하여 설명하면 다음과 같다.Hereinafter, a salicide layer forming process of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
도 1a내지 도 1d는 종래 기술의 반도체 소자의 살리사이드 형성을 위한 공정 단면도이다.1A to 1D are cross-sectional views of a process for forming a salicide of a semiconductor device of the prior art.
먼저, 도 1a에서와 같이, 반도체 기판(1)에 트렌치를 형성하고 절연 물질을 매립하는 STI(Shallow Trench Isolation) 공정으로 소자 격리층(2)을 형성하여 PMOS 트랜지스터 형성 영역과 NMOS 트랜지스터 형성 영역을 갖는 액티브 영역을 정의한다.First, as shown in FIG. 1A, the device isolation layer 2 is formed by a shallow trench isolation (STI) process in which a trench is formed in the semiconductor substrate 1 and the insulating material is filled to form a PMOS transistor formation region and an NMOS transistor formation region. It defines the active area having.
그리고 전면에 게이트 산화막(3), 게이트 형성용 물질층을 증착하고 선택적으로 패터닝하여 상기 PMOS 트랜지스터 형성 영역과 NMOS 트랜지스터 형성 영역상에 게이트 전극(4)을 형성한다.A gate oxide film 3 and a gate forming material layer are deposited on the entire surface and selectively patterned to form a gate electrode 4 on the PMOS transistor formation region and the NMOS transistor formation region.
그리고 상기 게이트 전극(4)을 마스크로 하여 저농도의 불순물 이온을 주입하여 LDD 영역(6)을 형성한다.The LDD region 6 is formed by implanting low concentrations of impurity ions using the gate electrode 4 as a mask.
이어, 전면에 제 1,2 게이트 측벽 형성용 물질층을 증착하고 이방성 식각하여 제 1,2 게이트 측벽(5)을 형성한다.Subsequently, a material layer for forming the first and second gate sidewalls is deposited on the entire surface and anisotropically etched to form the first and second gate sidewalls 5.
그리고, 전면에 포토레지스트를 도포하고 선택적으로 패터닝하여 트랜지스터 형성 영역이 오픈되는 포토레지스트 패턴층(도시하지 않음)을 형성한다.Then, photoresist is applied to the entire surface and selectively patterned to form a photoresist pattern layer (not shown) in which the transistor formation region is opened.
이어, 상기 포토레지스트 패턴층을 마스크로 하여 고농도의 불순물 이온을 주입하여 트랜지스터의 소오스/드레인 영역(7)을 형성한다.Subsequently, a high concentration of impurity ions are implanted using the photoresist pattern layer as a mask to form a source / drain region 7 of the transistor.
그리고 도 1b에서와 같이, 전면에 살리사이드 형성용 금속층(8)으로 Co 또는 Ti을 증착한다.1B, Co or Ti is deposited on the entire surface of the salicide-forming metal layer 8.
이어, 도 1c에서와 같이, 제 1 RTP(Rapid Thermal Process) 공정을 진행하여 Co2Si층(9)을 형성한 후 미반응의 살리사이드 형성용 금속층을 제거한다.Subsequently, as shown in FIG. 1C, a first rapid thermal process (RTP) process is performed to form a Co 2 Si layer 9, and then an unreacted salicide-forming metal layer is removed.
그리고 제 2 RTP 공정을 진행하여 살리사이드층(9)을 형성한다.Then, the second RTP process is performed to form the salicide layer 9.
이어, 도 1d에서와 같이, BLC(Bit Line Contact) 공정을 위한 제 1 절연막(도시하지 않음)을 형성한다.Subsequently, as shown in FIG. 1D, a first insulating film (not shown) for a BLC process is formed.
제 1 절연막은 LP HLD 증착 또는 LP 나이트라이드 증착 또는 열산화 공정으로 형성한다.The first insulating film is formed by LP HLD deposition or LP nitride deposition or thermal oxidation process.
그리고, 전면에 ILD(Inter Layer Dielectric)층으로 제 2 절연막(10)을 형성한다.The second insulating film 10 is formed on the entire surface by using an inter layer dielectric (ILD) layer.
이어, 상기 제 2 절연막(10)을 평탄화한 후에 전면에 포토레지스트를 도포하고 선택적으로 패터닝하여 비트 라인 콘택 영역을 정의하는 포토레지스트 패턴층(도시하지 않음)을 형성한다.Subsequently, after the second insulating film 10 is planarized, a photoresist is coated on the entire surface and selectively patterned to form a photoresist pattern layer (not shown) defining a bit line contact region.
그리고, 상기 포토레지스트 패턴층을 마스크로 하여 노출된 절연층을 식각하여 비트라인 콘택홀을 형성한 후에 도전성 물질층 콘택홀내에 매립하여 비트라인 콘택층을 형성한다.The exposed insulating layer is etched using the photoresist pattern layer as a mask to form a bit line contact hole, and then is embedded in the conductive material layer contact hole to form a bit line contact layer.
이와 같은 종래의 살리사이드 형성 방법은 게이트 전극 및 소오스/드레인 영역에 동일한 두께의 티타늄 또는 코발트를 증착한 후, 열처리를 실시하여 동시에 살리사이드를 형성한다.In the conventional salicide forming method, the same thickness of titanium or cobalt is deposited on the gate electrode and the source / drain regions, followed by heat treatment to form salicide at the same time.
그러나, 최근 반도체 소자의 집적도가 증가함에 따라 게이트 전극의 크기가 감소하고 소오스/드레인의 깊이가 감소하여 저항이 증가하게 되었다.However, as the degree of integration of semiconductor devices increases, the size of the gate electrode decreases and the depth of the source / drain decreases, thereby increasing the resistance.
따라서, 소오스/드레인의 깊이가 감소함에 따라 소오스/드레인에 형성되는 살리사이드는 얇은 두께로 형성해야 하며, 게이트 전극의 크기가 감소함에 따라 게이트 전극에 형성되는 실리사이드는 저저항성이 요구된다.Therefore, as the depth of the source / drain decreases, the salicide formed on the source / drain should be formed in a thin thickness, and as the size of the gate electrode decreases, the silicide formed on the gate electrode requires low resistance.
그러나 이와 같은 종래 기술의 반도체 소자의 살리사이드층 형성 공정은 다음과 같은 문제점이 있다.However, the salicide layer forming process of the semiconductor device of the prior art has the following problems.
게이트 전극와 소오스/드레인 영역에 동일한 금속 물질을 동일한 두께로 증착한 후, 열처리를 실시하여 살리사이드를 형성한다.The same metal material is deposited on the gate electrode and the source / drain regions with the same thickness, and then heat-treated to form salicide.
이는 게이트 전극의 저항 감소와 소오스/드레인의 접합층 두께 감소를 동시에 만족시킬 수 없다.This cannot satisfy both the decrease in resistance of the gate electrode and the decrease in the thickness of the junction layer of the source / drain.
본 발명은 이와 같은 종래 기술의 반도체 소자의 살리사이드층 형성 공정의 문제를 해결하기 위한 것으로, 본 발명은 게이트 전극에 저저항성의 살리사이드층을 형성하고 소오스/드레인에 누설전류를 억제할 수 있는 살리사이드층을 형성하는 데 적당한 반도체 소자의 살리사이드 형성 방법을 제공하는데 그 목적이 있다.The present invention is to solve the problem of the salicide layer forming process of the prior art semiconductor device, the present invention can form a low-resistance salicide layer on the gate electrode and can suppress the leakage current in the source / drain It is an object of the present invention to provide a method for forming a salicide of a semiconductor device suitable for forming a salicide layer.
도 1a내지 도 1d는 종래 기술의 반도체 소자의 살리사이드 형성 방법을 나타낸 공정 단면도1A to 1D are cross-sectional views illustrating a method of forming a salicide of a semiconductor device of the prior art.
도 2a내지 도 2f는 본 발명에 따른 반도체 소자의 살리사이드 형성 방법을 나타낸 공정 단면도2A to 2F are cross-sectional views illustrating a method of forming a salicide of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21. 반도체 기판 22. 소자 격리층21. Semiconductor substrate 22. Device isolation layer
23. 게이트 산화막 24. 게이트 전극23. Gate oxide 24. Gate electrode
25. 살리사이드 방지막 26. 제 1,2 게이트 측벽25. Salicide prevention layer 26. First and second gate sidewalls
27. LDD 영역 28. 소오스/드레인 영역27. LDD region 28. Source / drain region
29. 제 1 살리사이드 형성용 물질층 30. 제 1 살리사이드층29. First salicide layer material layer 30. First salicide layer
31. 평탄화용 절연막 32. 제 2 살리사이드 형성용 물질층31. Insulating film for planarization 32. Material layer for forming second salicide
33. 제 2 살리사이드층33. Second Salicide Layer
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 살리사이드 형성 방법은 반도체 기판의 액티브 영역상에 폴리실리콘막, 살리사이드 방지막이 적층된 구조의 게이트 전극들을 형성하고, 소오스/드레인 이온 주입을 하는 단계; 상기 전면에 제 1 살리사이드 형성용 물질층을 형성하고, 열처리 공정으로 액티브 영역의 표면에 제 1 살리사이드층을 형성하는 단계; 미반응의 제 1 살리사이드 형성용 물질층을 제거한 후, 전면에 평탄화용 절연막을 증착하는 단계; 상기 평탄화된 절연층을 평탄화하여 상기 폴리실리콘막의 표면을 노출시키는 단계; 상기 전면에 제 2 살리사이드 형성용 물질층을 형성하고, 열처리 공정으로 상기 노출된 폴리실리콘막 상에 제 2 살리사이드층을 형성하는 단계; 미반응의 제 2 살리사이드 형성용 물질층을 제거한 후, 전면에 층간절연막을 증착하는 단계를 포함함을 특징으로 한다.In order to achieve the above object, the method of forming a salicide of a semiconductor device according to the present invention includes forming gate electrodes having a structure in which a polysilicon layer and a salicide prevention layer are stacked on an active region of a semiconductor substrate, and performing source / drain ion implantation. Doing; Forming a first salicide forming material layer on the front surface and forming a first salicide layer on the surface of the active region by a heat treatment process; Removing the unreacted first salicide forming material layer and depositing a planarization insulating film on the entire surface; Planarizing the planarized insulating layer to expose a surface of the polysilicon film; Forming a second salicide forming material layer on the entire surface, and forming a second salicide layer on the exposed polysilicon layer by a heat treatment process; And removing an unreacted second salicide forming material layer, and depositing an interlayer insulating film on the entire surface.
이하, 첨부된 도면을 참고하여 본 발명에 따른 반도체 소자의 살리사이드 형성 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a salicide forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a내지 도 2f는 본 발명에 따른 반도체 소자의 살리사이드 형성을 위한 공정 단면도이다.2A to 2F are cross-sectional views of a process for forming a salicide of a semiconductor device according to the present invention.
본 발명은 게이트 전극에 저저항성의 살리사이드층을 형성하고, 소오스/드레인에 얇은 두께의 살리사이드층을 형성하여 소자의 전기적 특성을 향상시키도록 한 것이다.The present invention is to improve the electrical properties of the device by forming a low-resistance salicide layer on the gate electrode and a thin salicide layer on the source / drain.
먼저, 도 2a에서와 같이, 반도체 기판(21)에 트렌치를 형성하고 절연 물질을 매립하는 STI(Shallow Trench Isolation) 공정으로 소자 격리층(22)을 형성하여 액티브 영역을 정의한다.First, as shown in FIG. 2A, the device isolation layer 22 is formed by a shallow trench isolation (STI) process in which a trench is formed in the semiconductor substrate 21 and an insulating material is embedded to define an active region.
그리고 전면에 게이트 산화막(23), 게이트 형성용 물질층, 살리사이드 방지막()을 차례로 증착하고 선택적으로 패터닝하여 게이트 전극(24)을 형성한다.In addition, the gate oxide layer 23, the gate forming material layer, and the salicide barrier layer () are sequentially deposited on the front surface and selectively patterned to form the gate electrode 24.
여기서, 상기 게이트 형성용 물질층은 폴리실리콘을 재료로 하며, 상기 살리사이드 방지막(25)은 질화물질 또는 산화물질을 재료로 하여 200∼500Å의 두께로 형성한다.Here, the gate forming material layer is made of polysilicon, and the salicide prevention layer 25 is formed to have a thickness of 200 to 500 kW using a nitride material or an oxide material.
이어, 상기 게이트 전극(24)을 마스크로 하여 저농도의 불순물 이온을 주입하여 LDD 영역(27)을 형성한다.Subsequently, a low concentration of impurity ions are implanted using the gate electrode 24 as a mask to form the LDD region 27.
또한, 전면에 제 1,2 게이트 측벽 형성용 물질층을 증착하고 이방성 식각하여 제 1,2 게이트 측벽(26)을 형성한다.In addition, the first and second gate sidewalls 26 may be formed by depositing and anisotropically etching the material layers for forming the first and second gate sidewalls.
그리고, 전면에 포토레지스트를 도포하고 선택적으로 패터닝하여 트랜지스터 형성 영역이 오픈되는 포토레지스트 패턴(도시하지 않음)을 형성한다.Then, a photoresist is applied to the entire surface and selectively patterned to form a photoresist pattern (not shown) in which the transistor formation region is opened.
이어, 상기 포토레지스트 패턴을 마스크로 하여 고농도의 불순물 이온을 주입한 후, 열처리하여 트랜지스터의 소오스/드레인 영역(28)을 형성한다.Subsequently, a high concentration of impurity ions are implanted using the photoresist pattern as a mask, followed by heat treatment to form a source / drain region 28 of the transistor.
그리고 도 2b에서와 같이, 전면에 제 1 살리사이드 형성용 물질층(29)으로 니켈을 50∼150Å의 두께로 증착한다.As shown in FIG. 2B, nickel is deposited on the entire surface of the first salicide forming material layer 29 at a thickness of 50 to 150 kPa.
이어, 도 2c에서와 같이, RTP(Rapid Thermal Process) 공정을 통해 니켈과 실리콘과의 반응을 유도하여 제 1 살리사이드층(30)을 형성한 후, 미반응의 제 1 살리사이드 형성용 물질층(29)을 습식 식각 공정으로 제거한다.Subsequently, as shown in FIG. 2C, after forming a first salicide layer 30 by inducing a reaction between nickel and silicon through a rapid thermal process (RTP) process, an unreacted first salicide forming material layer is formed. (29) is removed by a wet etching process.
여기서, 상기 RTP 공정은 400∼500℃의 온도로 진행하고, 상기 습식 식각 공정은 H2SO4: H2O2= 4 : 1의 혼합액을 사용한다.Here, the RTP process proceeds at a temperature of 400 ~ 500 ℃, the wet etching process uses a mixture of H 2 SO 4 : H 2 O 2 = 4: 1.
이어, 도 2d에서와 같이, 전면에 평탄화용 절연막(31)으로 질화물질 또는 산화물질을 증착한다.Next, as illustrated in FIG. 2D, a nitride material or an oxide material is deposited on the entire surface of the planarization insulating layer 31.
그리고, 도 2e에서와 같이, 화학적 기계 연마법(CMP)을 이용하여 상기 평탄화용 절연막(31)을 평탄화한다.As shown in FIG. 2E, the planarization insulating film 31 is planarized by chemical mechanical polishing (CMP).
이때, 상기 살리사이드 방지막(25)이 제거되고, 상기 살리사이드 방지막(25) 하부의 게이트 전극(24)인 폴리실리콘이 드러날 때까지 연마한다.At this time, the salicide barrier layer 25 is removed and polished until polysilicon, which is the gate electrode 24 under the salicide barrier layer 25, is exposed.
이어, 전면에 제 2 살리사이드 형성용 물질층(32)으로 코발트를 100∼200Å의 두께로 형성한다.Subsequently, cobalt is formed to a thickness of 100 to 200 mm 3 on the entire surface of the second salicide forming material layer 32.
이후, 도 2f에서와 같이, RTP 공정을 통해 코발트와 실리콘과의 반응을 유도하여 제 2 살리사이드층(33)을 형성한 후, 미반응의 제 2 살리사이드 형성용 물질층(32)을 습식 식각 공정으로 제거한다.Thereafter, as shown in FIG. 2F, the second salicide layer 33 is formed by inducing a reaction between cobalt and silicon through an RTP process, and then the unreacted second salicide forming material layer 32 is wetted. Removed by etching process.
여기서, 상기 RTP 공정은 650∼750℃의 온도로 진행하고, 상기 습식 식각 공정은 H2SO4: H2O2= 4 : 1의 혼합액을 사용한다.Here, the RTP process is carried out at a temperature of 650 ~ 750 ℃, the wet etching process uses a mixture of H 2 SO 4 : H 2 O 2 = 4: 1.
그리고, 전면에 BLC(Bit Line Contact) 공정을 위한 절연막(도시하지 않음)과 전면에 ILD(Inter Layer Dielectric)층으로 BPSG(Boron Phosphorus Silicate Glass)을 증착하여 절연층(도시하지 않음)을 형성한다.In addition, an insulating layer (not shown) is formed by depositing a BPSG (Boron Phosphorus Silicate Glass) with an insulating film for a bit line contact (BLC) process on the front surface and an inter layer dielectric (ILD) layer on the front surface. .
또한, 비트 라인 콘택 영역을 정의하는 포토레지스트 패턴(도시하지 않음)을 형성한 후, 상기 포토레지스트 패턴을 마스크로 하여 노출된 절연층을 식각하여 비트라인 콘택홀을 형성한 후에 도전성 물질층 콘택홀내에 매립하여 비트라인 콘택(도시하지 않음)을 형성한다.In addition, after forming a photoresist pattern (not shown) defining a bit line contact region, the exposed insulating layer is etched using the photoresist pattern as a mask to form a bit line contact hole, and then a conductive material layer contact hole. Buried in to form bit line contacts (not shown).
이와 같은 본 발명에 따른 반도체 소자의 살리사이드 형성 방법은 다음과 같은 효과가 있다.The salicide formation method of the semiconductor device according to the present invention has the following effects.
본 발명은 게이트 전극에 코발트을 이용하여 저저항성을 갖는 살리사이드층을 형성하고, 소오스/드레인에 니켈을 이용하여 얇은 두께의 살리사이드층을 형성할 수 있다.According to the present invention, a salicide layer having low resistance may be formed using cobalt on a gate electrode, and a salicide layer having a thin thickness may be formed using nickel on a source / drain.
즉, 소오스/드레인에 실리콘 소모량이 적은 니켈 살리사이드층을 형성함으로써, 트랜지스터의 단채널 효과를 방지할 수 있고, 게이트에 비저항이 낮은 코발트 살리사이드를 형성함으로써, 고집적 소자에서 저항의 증가를 방지할 수 있는 효과가 있다.That is, by forming a nickel salicide layer with low silicon consumption in the source / drain, the short channel effect of the transistor can be prevented, and cobalt salicide with low specific resistance can be formed in the gate, thereby preventing an increase in resistance in the highly integrated device. It can be effective.
Claims (5)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5869396A (en) * | 1996-07-15 | 1999-02-09 | Chartered Semiconductor Manufacturing Ltd. | Method for forming a polycide gate electrode |
| KR20000004742A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Manufacturing method of semiconductor device |
| US6060387A (en) * | 1995-11-20 | 2000-05-09 | Compaq Computer Corporation | Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions |
| KR20000066540A (en) * | 1999-04-19 | 2000-11-15 | 김영환 | Method of forming dissymmetric salicide layer in Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6060387A (en) * | 1995-11-20 | 2000-05-09 | Compaq Computer Corporation | Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions |
| US5869396A (en) * | 1996-07-15 | 1999-02-09 | Chartered Semiconductor Manufacturing Ltd. | Method for forming a polycide gate electrode |
| KR20000004742A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Manufacturing method of semiconductor device |
| KR20000066540A (en) * | 1999-04-19 | 2000-11-15 | 김영환 | Method of forming dissymmetric salicide layer in Semiconductor device |
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