KR100387254B1 - Method of manufacturing a metal wiring in a semiconductor device - Google Patents

Method of manufacturing a metal wiring in a semiconductor device Download PDF

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Publication number
KR100387254B1
KR100387254B1 KR10-2000-0084737A KR20000084737A KR100387254B1 KR 100387254 B1 KR100387254 B1 KR 100387254B1 KR 20000084737 A KR20000084737 A KR 20000084737A KR 100387254 B1 KR100387254 B1 KR 100387254B1
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South Korea
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hole pattern
forming
via hole
metal wiring
film
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KR10-2000-0084737A
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Korean (ko)
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KR20020055313A (en
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이성권
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 자기 정렬 듀얼 다마신 공정 기법으로 비아홀 패턴을 형성할 때, 비아홀 패턴이 형성될 부분에 대응되는 작은 크기의 홀 패턴이 형성된 에치 버퍼용 질화막을 사용하는데, 홀 패턴을 용이하게 형성하면서 전 지역에 걸쳐 존재하는 에치 버퍼용 질화막으로 인한 스트레스를 줄이기 위하여, 본 발명에서는 비아홀 패턴이 형성될 부분의 주변에만 에치 버퍼용 질화막을 남기므로, 오픈할 지역이 넓어 홀 패턴을 용이하게 형성할 수 있고, 에치 버퍼용 질화막이 비아홀 패턴 주변에만 존재하여 스트레스를 줄일 수 있는 반도체 소자의 금속 배선 형성 방법에 관하여 기술된다.The present invention relates to a method of forming a metal wiring of a semiconductor device, and when forming a via hole pattern using a self-aligned dual damascene process, a nitride film for an etch buffer having a small hole pattern corresponding to a portion where a via hole pattern is to be formed is formed. In order to reduce the stress caused by the etch buffer nitride film existing throughout the entire area while easily forming a hole pattern, in the present invention, the nitride buffer film is left only around the portion where the via hole pattern is to be formed. A method of forming a metal wiring of a semiconductor device in which the wider hole pattern can be easily formed and the etch buffer nitride film exists only around the via hole pattern can reduce stress.

Description

반도체 소자의 금속 배선 형성 방법{Method of manufacturing a metal wiring in a semiconductor device}Method of manufacturing a metal wiring in a semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 자기 정렬 듀얼 다마신 공정 기법으로 비아홀 콘택을 형성할 때 적용되는 에치 버퍼용 질화막의 홀 패턴을 용이하게 형성하면서 에치 버퍼용 질화막으로 인한 스트레스를 줄일 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device. In particular, the stress due to the etch buffer nitride film can be easily formed while easily forming the hole pattern of the etch buffer nitride film applied when the via hole contact is formed by a self-aligned dual damascene process technique. The present invention relates to a method for forming a metal wiring of a semiconductor device, which can reduce the number.

반도체 소자가 고집적화 되어 감에 따라 금속 배선의 폭은 좁아지고, 다층 구조를 이루고, 하부 도전층과 상부 도전층을 전기적으로 연결시켜주기 위한 비아 콘택홀의 크기 역시 작아지고 있는 추세이다. 금속 배선의 폭이 좁아지므로 인해 발생되는 저항의 증가를 방지하기 위해 전기 전도도가 우수한 대체 물질에 대한 연구가 진행되고 있는데, 전기 비저항이 낮고 EM(electromigration) 특성 및 SM(stressmigration) 특성이 우수한 구리 배선에 대한 연구가 크게 부각되고 있다. 하지만 구리 박막은 현재까지 반도체 소자의 금속 배선으로 사용하고 있는 알루미늄 박막과는 달리 구리 박막의 재료의 물성적인 특징에 기인하는 문제점이 있다.As semiconductor devices have been highly integrated, the width of metal wirings has narrowed, and the size of via contact holes for forming a multilayer structure and electrically connecting the lower conductive layer and the upper conductive layer is also decreasing. In order to prevent the increase in resistance caused by the narrowing of the metal wiring, research is being conducted on alternative materials having excellent electrical conductivity.Copper wiring with low electrical resistivity and excellent electromigration (EM) and stress migration (SM) characteristics There is a great deal of research on. However, unlike the aluminum thin film, which has been used as metal wiring for semiconductor devices, the copper thin film has a problem due to the physical properties of the material of the copper thin film.

구리 박막은 실리콘 또는 실리콘 산화막 내로 구리 원자가 쉽게 침투하여 들어가 소자의 전기적 특성 및 절연 특성을 악화시키는 문제점이 있으며, 산소와 쉽게 반응하여 구리 산화물을 형성하는 등 내 산화성이 매우 취약하다. 또한, 구리 박막의 증착 방법으로 연구되고 있는 금속유기 화학기상증착(MOCVD) 방법은 양산 공정에 적용될 만큼 안정된 공정을 보이지 않고 있으며, 기존의 플라즈마 방법으로 식각시 낮은 증기압으로 인해 식각 공정 진행상 난제가 많다.The copper thin film has a problem in that copper atoms easily penetrate into the silicon or silicon oxide film, thereby deteriorating the electrical and insulating properties of the device. The copper thin film is very vulnerable to oxidation resistance such as easily reacting with oxygen to form copper oxide. In addition, the metal organic chemical vapor deposition (MOCVD) method, which is being studied as a method of depositing a copper thin film, does not show a stable process so as to be applied to a mass production process. .

구리를 반도체 공정에 적용하기 위해서는 위에 열거한 많은 문제점을 고려하여 진행해야한다. 현재 구리를 배선재료로 사용함에 있어 자기 정렬 듀얼 다마신 공정 기법이 널리 적용하고 있다. 자기 정렬 듀얼 다마신 공정 기법을 적용한 종래 반도체 소자의 금속 배선 형성 방법을 도 1a 내지 도 1e를 참조하여 설명하면 다음과 같다.In order to apply copper to semiconductor processes, it is necessary to take into consideration many of the problems listed above. Currently, the self-aligned dual damascene process technique is widely applied to copper as a wiring material. A method of forming a metal wiring of a conventional semiconductor device to which a self-aligned dual damascene process technique is applied will be described with reference to FIGS. 1A to 1E.

도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11)상에 하부 금속배선(12), 하부 절연막(13) 및 에치 버퍼용 질화막(14)을 순차적으로 형성한다.Referring to FIG. 1A, a lower metal wiring 12, a lower insulating film 13, and an etch buffer nitride film 14 are sequentially formed on a substrate 11 on which various elements for forming a semiconductor device are formed.

상기에서, 에치 버퍼용 질화막(14)은 하부 절연막(13)의 전면에 걸쳐 형성된다.In the above, the etch buffer nitride film 14 is formed over the entire surface of the lower insulating film 13.

도 1b를 참조하면, 마스크 공정 및 에치 공정을 실시하여 비아홀 패턴이 형성될 부분에 대응되는 에치 버퍼용 질화막(14)의 일부분을 제거하여 홀 패턴(15)을 형성한다.Referring to FIG. 1B, a hole pattern 15 is formed by performing a mask process and an etch process to remove a portion of the etch buffer nitride film 14 corresponding to the portion where the via hole pattern is to be formed.

상기에서, 홀 패턴(15)은 타임 에치 방식으로 플라즈마 에치하여 형성된다.In the above, the hole pattern 15 is formed by plasma etching in a time etch manner.

도 1c를 참조하면, 홀 패턴(15)을 포함한 에치 버퍼용 질화막(14)상에 상부 절연막(16)을 형성한다.Referring to FIG. 1C, an upper insulating film 16 is formed on the etch buffer nitride film 14 including the hole pattern 15.

도 1d를 참조하면, 마스크 공정 및 에치 공정으로 상부 절연막(16)의 일부분을 제거하여 홀 패턴(15)의 크기보다 큰 크기의 홀을 먼저 형성하고, 노출된 에치 버퍼용 질화막(14)의 부분을 자기 정렬 마스크로 이용하여 홀 패턴(15) 부분의 하부 절연막(13)을 제거하여 하부 금속 배선(12)이 노출되는 비아홀 패턴(17)을 형성한다.Referring to FIG. 1D, a portion of the upper insulating layer 16 is removed by a mask process and an etch process to first form a hole having a size larger than that of the hole pattern 15, and then expose the portion of the nitride film 14 for the etch buffer exposed. The lower insulating layer 13 of the hole pattern 15 is removed using the self-alignment mask to form the via hole pattern 17 through which the lower metal wiring 12 is exposed.

도 1e를 참조하면, 비아홀 패턴(17) 내에 장벽 금속층(18) 및 상부 금속 배선(19)을 형성한다.Referring to FIG. 1E, the barrier metal layer 18 and the upper metal wiring 19 are formed in the via hole pattern 17.

상기한 바와 같이, 자기 정렬 듀얼 다마신 공정 기법을 적용한 종래 반도체 소자의 금속 배선 형성 방법에서는 에치 버퍼용 질화막(14)을 전면에 도포한 후, 비아홀 패턴(17)이 형성될 부위에 대해서 비아홀 패턴(17)보다 작은 크기의 홀 패턴(15)을 형성하는데, 홀 패턴(15)은 매우 작은 크기이기 때문에 에치 공정시 EOP를 잡을 수 없고, 또한 홀 패턴(15) 이외의 부분에 에치 버퍼용 질화막(14)이 남아있게 되어 스트레스의 발생 등을 초래한다.As described above, in the method of forming a metal wiring of a semiconductor device using the self-aligned dual damascene process technique, after applying the etch buffer nitride film 14 to the entire surface, the via hole pattern is formed on a portion where the via hole pattern 17 is to be formed. The hole pattern 15 having a smaller size than (17) is formed, but since the hole pattern 15 is very small, the EOP cannot be caught during the etch process, and the nitride film for the etch buffer is formed in a portion other than the hole pattern 15. (14) remains and causes occurrence of stress.

따라서, 본 발명은 자기 정렬 듀얼 다마신 공정 기법으로 비아홀 콘택을 형성할 때 적용되는 에치 버퍼용 질화막의 홀 패턴을 용이하게 형성하면서 에치 버퍼용 질화막으로 인한 스트레스를 줄일 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention can easily form the hole pattern of the etch buffer nitride film applied when the via hole contact is formed by the self-aligned dual damascene process technique, while forming the metal wiring of the semiconductor device which can reduce the stress caused by the etch buffer nitride film. The purpose is to provide a method.

도 1a 내지 도 1e는 종래 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of a device for explaining a metal wiring formation method of a conventional semiconductor device.

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.2A to 2E are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11, 21: 기판 12, 22: 하부 금속 배선11, 21: substrate 12, 22: lower metal wiring

13, 23: 하부 절연막 14, 24: 에치 버퍼용 질화막13, 23: lower insulating film 14, 24: etch buffer nitride film

15, 25: 홀 패턴 240: 비아홀용 패턴15, 25: hole pattern 240: via hole pattern

16, 26: 상부 절연막 17, 27: 비아홀 패턴16, 26: upper insulating film 17, 27: via hole pattern

18, 28: 장벽 금속층 19, 29: 상부 금속 배선18, 28: barrier metal layer 19, 29: upper metal wiring

본 발명의 반도체 소자의 금속 배선 형성 방법은 하부 금속배선이 형성된 기판상에 하부 절연막 및 에치 버퍼용 질화막을 순차적으로 형성하는 단계; 마스크 공정 및 에치 공정으로 상기 에치 버퍼용 질화막을 제거하여 홀 패턴을 형성하되, 비아홀 패턴이 형성될 부분의 주변에만 상기 에치 버퍼용 질화막이 남도록 하여 상기 홀 패턴을 둘러싸는 비아홀용 패턴을 형성하는 단계; 상기 홀 패턴 및 비아홀용 패턴을 포함한 하부 절연막상에 상부 절연막을 형성한 후, 마스크 공정 및 에치 공정으로 상기 상부 절연막 및 상기 홀 패턴 부분의 하부 절연막을 제거하여 비아홀 패턴을 형성하는 단계; 및 상기 비아홀 패턴내에 장벽 금속층 및 상부 금속 배선을 형성하는 단계를 포함하여 이루어진다.A method of forming a metal wiring of a semiconductor device according to the present invention includes the steps of sequentially forming a lower insulating film and a etch buffer nitride film on a substrate on which a lower metal wiring is formed; Forming a hole pattern by removing the etch buffer nitride film by a mask process and an etch process, but leaving the etch buffer nitride film only around the portion where the via hole pattern is to be formed to form a via hole pattern surrounding the hole pattern ; Forming an upper insulating film on the lower insulating film including the hole pattern and the via hole pattern, and then forming a via hole pattern by removing the upper insulating film and the lower insulating film of the hole pattern portion by a mask process and an etch process; And forming a barrier metal layer and an upper metal wiring in the via hole pattern.

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.2A to 2E are cross-sectional views of devices for describing a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.

도 2a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(21)상에 하부 금속 배선(22), 하부 절연막(23) 및 에치 버퍼용 질화막(24)을 순차적으로 형성한다.Referring to FIG. 2A, a lower metal wiring 22, a lower insulating film 23, and an etch buffer nitride film 24 are sequentially formed on a substrate 21 on which various elements for forming a semiconductor device are formed.

상기에서, 하부 금속 배선(22)은 구리, 은, 금, 백금 중 적어도 어느 하나를 사용하여 형성한다. 에치 버퍼용 질화막(24)은 하부 절연막(23)의 전면에 걸쳐 500 내지 3000Å의 두께로 형성하며, 질화막 대신에 Al2O3등의 재료로 형성할 수 있다. 하부 절연막(23)은 SiO2를 근간으로 하는 모든 종류의 산화 절연막인 BPSG, SOG, HTO, PSG, HSQ, HOSP, PTFE, BCB 등으로 형성한다. HSQ, HOSP, PTFE, BCB는 저유전 특성을 갖는다.In the above, the lower metal wiring 22 is formed using at least one of copper, silver, gold, and platinum. The etch buffer nitride film 24 is formed to a thickness of 500 to 3000 kPa over the entire surface of the lower insulating film 23, and may be formed of a material such as Al 2 O 3 instead of the nitride film. The lower insulating film 23 is formed of BPSG, SOG, HTO, PSG, HSQ, HOSP, PTFE, BCB and the like which are all kinds of oxide insulating films based on SiO 2 . HSQ, HOSP, PTFE, BCB have low dielectric properties.

도 2b를 참조하면, 마스크 공정 및 에치 공정을 실시하여 비아홀 패턴이 형성될 부분에 대응되는 에치 버퍼용 질화막(24)의 일부분을 제거하여 홀 패턴(25)을 형성하고, 이때 홀 패턴(25) 주변의 에치 버퍼용 질화막(24)을 제외한 모든 에치 버퍼용 질화막(24)을 제거하며, 이로 인하여 홀 패턴(25) 주변에는 비아홀용 패턴(240)의 에치 버퍼용 질화막(24)이 남게된다.Referring to FIG. 2B, a hole pattern 25 is formed by removing a portion of the etch buffer nitride film 24 corresponding to a portion where a via hole pattern is to be formed by performing a mask process and an etch process. All of the etch buffer nitride film 24 except for the etch buffer nitride film 24 in the vicinity is removed, and thus, the etch buffer nitride film 24 of the via hole pattern 240 remains around the hole pattern 25.

상기에서, 홀 패턴(25)은 타임 에치 방식으로 플라즈마 에치하여 형성되는데, 홀 패턴(25)의 주변에 남겨지는 비아홀용 패턴(240)을 제외한 모든 에치 버퍼용 질화막(24)을 제거하기 때문에 에치 면적이 넓어 EOP를 잡기가 용이해 진다. 홀 패턴(25)을 형성하기 위해 사용되는 마스크는 도넛츠, 마름모, 정사각형, 직사각형 등의 다양한 모양으로 제작하여 사용할 수 있다. 한편, 비아홀용 패턴(240)은 0.5 내지 3㎛의 크기로 형성 가능하다. 이로써, 홀 패턴(25)을 둘러싸도록 도넛츠, 마름모, 정사각형, 직사각형 등의 다양한 형태를 갖는 비아홀용 패턴(240)이 형성된다.In the above, the hole pattern 25 is formed by plasma etching in a time etch manner, and because the etch buffer nitride film 24 is removed except for the via hole pattern 240 remaining around the hole pattern 25. The large area makes it easier to catch EOP. The mask used to form the hole pattern 25 may be manufactured and used in various shapes such as donuts, rhombuses, squares, rectangles, and the like. On the other hand, the via hole pattern 240 may be formed in a size of 0.5 to 3㎛. As a result, a via hole pattern 240 having various shapes such as a donut, a rhombus, a square, and a rectangle is formed to surround the hole pattern 25.

도 2c를 참조하면, 홀 패턴(25) 및 비아홀용 패턴(240)을 포함한 하부 절연막(23)상에 상부 절연막(26)을 형성한다.Referring to FIG. 2C, an upper insulating layer 26 is formed on the lower insulating layer 23 including the hole pattern 25 and the via hole pattern 240.

도 2d를 참조하면, 마스크 공정 및 에치 공정으로 상부 절연막(26)의 일부분을 제거하여 홀 패턴(25)의 크기보다 큰 크기의 홀을 먼저 형성하고, 노출된 비아홀용 패턴(240)의 부분을 자기 정렬 마스크로 이용하여 홀 패턴(25) 부분의 하부 절연막(23)을 제거하여 하부 금속 배선(22)이 노출되는 비아홀 패턴(27)을 형성한다.Referring to FIG. 2D, a portion of the upper insulating layer 26 is removed by a mask process and an etch process to first form a hole having a size larger than that of the hole pattern 25, and then expose a portion of the exposed via hole pattern 240. The lower insulating layer 23 of the hole pattern 25 is removed using the self-alignment mask to form a via hole pattern 27 through which the lower metal wiring 22 is exposed.

도 2e를 참조하면, 비아홀 패턴(27) 내에 장벽 금속층(28) 및 상부 금속 배선(29)을 형성한다.Referring to FIG. 2E, the barrier metal layer 28 and the upper metal wiring 29 are formed in the via hole pattern 27.

상기에서, 장벽 금속층(28)은 TiN, TaN, Ta, TiW, WN, CrN 등으로 형성한다.상부 금속 배선(29)은 구리, 은, 금, 백금 중 적어도 어느 하나를 사용하여 형성한다.In the above, the barrier metal layer 28 is formed of TiN, TaN, Ta, TiW, WN, CrN, or the like. The upper metal wiring 29 is formed using at least one of copper, silver, gold, and platinum.

상기한 바와 같이, 자기 정렬 듀얼 다마신 공정 기법을 본 발명의 반도체 소자의 금속 배선 형성 방법에서는 작은 크기의 홀 패턴(15)을 형성할 때 다른 부분의 에치 버퍼용 질화막(24)도 제거하기 때문에 에치 영역이 넓어 에치 공정시 EOP를 잡을 수 있고, 또한 에치 버퍼용 질화막(24)이 비아홀용 패턴(240)으로 홀 패턴(25) 주변에만 남아있게 되어 기존처럼 에치 버퍼용 질화막으로 인한 스트레스의 발생이 없게된다.As described above, since the self-aligned dual damascene process technique removes the other portions of the etch buffer nitride film 24 when forming the small sized hole pattern 15 in the method for forming the metal wiring of the semiconductor device of the present invention. The etch area is wide enough to catch EOP during the etch process, and the etch buffer nitride film 24 remains only around the hole pattern 25 as the via hole pattern 240, so that the stress caused by the etch buffer nitride film as before. There will be no.

상술한 바와 같이, 본 발명은 자기 정렬 듀얼 다마신 공정 기법으로 금속 배선을 형성할 때 적용하는 에치 버퍼용 절연막의 홀 패턴을 용이하게 형성할 수 있을 뿐만아니라 에치 버퍼용 절연막으로 인한 스트레스가 없어 효과적으로 구리 금속 배선을 형성할 수 있다.As described above, the present invention can not only easily form the hole pattern of the etch buffer insulating film applied when forming the metal wiring by the self-aligned dual damascene process technique, but also effectively eliminates the stress caused by the etch buffer insulating film. Copper metal wiring can be formed.

Claims (7)

하부 금속 배선이 형성된 기판 상에 SiO2막을 근간으로 하는 산화막으로 하부 절연막을 형성하는 단계;Forming a lower insulating film on the substrate on which the lower metal wiring is formed, using an oxide film based on the SiO 2 film; 상기 하부 절연막 상에 에치 버퍼용 Al2O3막을 형성하는 단계;Forming an Al 2 O 3 film for etch buffer on the lower insulating film; 상기 에치 버퍼용 Al2O3막을 패터닝하여 홀 패턴을 정의하는 비아홀용 패턴을 형성하되, 상기 홀 패턴이 형성될 부분의 주변에만 상기 에치 버퍼용 Al2O3막이 남도록 하여 상기 홀 패턴을 둘러싸는 도넛츠 형태를 갖도록 상기 비아홀용 패턴을 형성하는 단계;Patterning the Al 2 O 3 film for the etch buffer to form a via hole pattern defining a hole pattern, but leaving the Al 2 O 3 film for the etch buffer only around the portion where the hole pattern is to be formed to surround the hole pattern. Forming a pattern for the via hole to have a donut shape; 전체 구조 상부에 상부 절연막을 형성하는 단계;Forming an upper insulating film on the entire structure; 마스크 공정과, 상기 비아홀용 패턴을 에치 버퍼로 이용한 에치 공정으로 상기 상부 절연막 및 상기 하부 절연막을 순차적으로 식각하여 비아홀 패턴을 형성하는 단계;Forming a via hole pattern by sequentially etching the upper insulating film and the lower insulating film by a mask process and an etch process using the via hole pattern as an etch buffer; 상기 비아홀 패턴의 내측면을 따라 장벽 금속층을 형성하는 단계; 및Forming a barrier metal layer along an inner surface of the via hole pattern; And 상기 비아홀 패턴이 갭 필링되도록 상부 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.Forming an upper metal line so that the via hole pattern is gap-filled. 제 1 항에 있어서,The method of claim 1, 상기 에치 버퍼용 Al2O3막은 500 내지 3000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the Al 2 O 3 film for etch buffer is formed to a thickness of 500 to 3000 GPa. 제 1 항에 있어서,The method of claim 1, 상기 하부 절연막은 BPSG, SOG, HTO, PSG 중 어느 하나로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The lower insulating layer is formed of any one of the BPSG, SOG, HTO, PSG metal wiring forming method of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 홀 패턴은 타임 에치 방식으로 플라즈마 에치하여 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the hole pattern is formed by plasma etching using a time etch method. 제 1 항에 있어서,The method of claim 1, 상기 비아홀용 패턴은 상기 비아홀 패턴 형성시 자기 정렬 마스크 역할을 하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The via hole pattern may serve as a self alignment mask when the via hole pattern is formed. 제 1 항에 있어서,The method of claim 1, 상기 장벽 금속층은 TiN, TaN, Ta, TiW, WN, CrN 중 어느 하나로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The barrier metal layer is formed of any one of TiN, TaN, Ta, TiW, WN, CrN metal wiring forming method of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 하부 금속 배선 및 상부 금속 배선은 구리, 은, 금, 백금 중 적어도 어느 하나로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The lower metal wiring and the upper metal wiring are formed of at least one of copper, silver, gold and platinum.
KR10-2000-0084737A 2000-12-28 2000-12-28 Method of manufacturing a metal wiring in a semiconductor device KR100387254B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990030048A (en) * 1997-09-29 1999-04-26 디어터 크리스트, 베르너 뵈켈 Dual damascene method with self-aligned interconnect passage
US6093632A (en) * 1998-12-07 2000-07-25 Industrial Technology Research Institute Modified dual damascene process
JP2000232106A (en) * 1999-02-10 2000-08-22 Tokyo Electron Ltd Semiconductor device and manufacture of semiconductor device
US6133144A (en) * 1999-08-06 2000-10-17 Taiwan Semiconductor Manufacturing Company Self aligned dual damascene process and structure with low parasitic capacitance

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990030048A (en) * 1997-09-29 1999-04-26 디어터 크리스트, 베르너 뵈켈 Dual damascene method with self-aligned interconnect passage
US6093632A (en) * 1998-12-07 2000-07-25 Industrial Technology Research Institute Modified dual damascene process
JP2000232106A (en) * 1999-02-10 2000-08-22 Tokyo Electron Ltd Semiconductor device and manufacture of semiconductor device
US6133144A (en) * 1999-08-06 2000-10-17 Taiwan Semiconductor Manufacturing Company Self aligned dual damascene process and structure with low parasitic capacitance

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