KR100384080B1 - Semiconductor package - Google Patents

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Publication number
KR100384080B1
KR100384080B1 KR10-1999-0048981A KR19990048981A KR100384080B1 KR 100384080 B1 KR100384080 B1 KR 100384080B1 KR 19990048981 A KR19990048981 A KR 19990048981A KR 100384080 B1 KR100384080 B1 KR 100384080B1
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South Korea
Prior art keywords
lead
semiconductor package
semiconductor
chip
exposed
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KR10-1999-0048981A
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Korean (ko)
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KR20010045638A (en
Inventor
이길진
한임택
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앰코 테크놀로지 코리아 주식회사
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Priority to KR10-1999-0048981A priority Critical patent/KR100384080B1/en
Publication of KR20010045638A publication Critical patent/KR20010045638A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 반도체 패키지에 관한 것으로서, 특히 반도체 패키지의 크기를 보다 경박단소화로 제조하는 동시에 칩에서 발생되는 열의 방출을 극대화시킬 수 있는 구조의 반도체 패키지를 안출한 것으로서, 이에 수직 절곡된 리드프레임의 리드와, 상기 리드의 상단 저면과 접착수단으로 부착되는 반도체 칩과, 상기 리드와 반도체 칩의 본딩패드간에 연결된 와이어와, 상기 리드의 일부분과 상기 반도체 칩의 저면을 외부로 노출시키면서 몰딩하고 있는 수지로 구성된 반도체 패키지를 제공하고자 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package. In particular, the present invention provides a semiconductor package having a structure capable of maximizing the emission of heat generated from a chip while simultaneously manufacturing the size of the semiconductor package in a lighter and thinner size, and thus having a vertically curved lead frame. A resin which is molded while exposing a lead, a semiconductor chip attached by an upper end of the lead and adhesive means, a wire connected between the lead and a bonding pad of the semiconductor chip, and a portion of the lead and the bottom of the semiconductor chip to the outside It is to provide a semiconductor package consisting of.

Description

반도체 패키지{Semiconductor package}Semiconductor Package {Semiconductor package}

본 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 반도체 칩의 저면과 리드의 일부가 외부로 노출시켜, 반도체 패키지의 크기를 최소화시키는 동시에 열방출 효과를 극대화시킬 수 있도록 한 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package in which a bottom surface of a semiconductor chip and a part of a lead are exposed to the outside, thereby minimizing the size of the semiconductor package and maximizing heat dissipation effect.

통상적으로 반도체 패키지의 구조는 웨이퍼에서 소잉된 각 반도체 칩이 리드 프레임상에 형성되어 있는 칩탑재판에 에폭시와 같은 접착수단으로 접착되어 있고, 이 접착된 반도체 칩의 본딩패드와 상기 리드 프레임의 리드간에 와이어가 연결되어 있으며, 상기 반도체 칩과 와이어등은 몰딩 컴파운드 수지로 몰딩되어 감싸여진 구조로 이루어져 있다.In general, the structure of the semiconductor package is bonded to the chip mounting plate on which each semiconductor chip sourced from the wafer is formed on the lead frame by an adhesive means such as epoxy, and the bonding pad of the bonded semiconductor chip and the lead of the lead frame. Wires are connected to each other, and the semiconductor chip and the wire have a structure that is molded and wrapped with a molding compound resin.

또한, 상기와 같은 통상적인 구조의 반도체 패키지 뿐만아니라, 전자기기의 집약적 발달과 소형화 경향으로 인하여 고집적화, 소형화, 고기능화의 추세에 병행하여, 상기 칩탑재판의 저면이 외부로 노출되어진 구조의 EPP(Exposed Pad Package) 반도체 패키지, 볼 그리드 어레이 반도체 패키지, 칩탑재판과 리드프레임의 일면이 외부로 동시에 노출된 구조의 MLP(Micro Leadframe Package) 반도체 패키지등 다양한 종류의 반도체 패키지가 경박단소화로 개발되어 왔고, 개발중에 있다.In addition, as well as the semiconductor package of the conventional structure as described above, due to the intensive development and miniaturization tendency of the electronic device, in parallel to the trend of high integration, miniaturization, and high functionalization, the bottom surface of the chip mounting plate is exposed to the outside of the EPP ( Exposed Pad Package) Various kinds of semiconductor packages such as semiconductor package, ball grid array semiconductor package, chip mounting plate and MLP (Micro Leadframe Package) semiconductor package with one surface of lead frame exposed to the outside at the same time It is in development.

상기 나열한 반도체 패키지 중에 EPP반도체 패키지와 MLP반도체 패키지는 칩칩에서 발생되는 열을 효율적으로 방출시킬 수 있는 구조의 패키지로서, 리드와 반도체 칩탑재판의 일면이 외부로 노출된 MLP반도체 패키지가 열방출 효과는 더 뛰어난 것으로 알려져 있다.Among the semiconductor packages listed above, the EPP semiconductor package and the MLP semiconductor package have a structure capable of efficiently dissipating heat generated from the chip chip, and the heat dissipation effect of the MLP semiconductor package in which one side of the lead and the semiconductor chip mounting plate is exposed to the outside Is known to be more outstanding.

상기와 같이 반도체 칩에서 발생되는 열을 보다 효율적으로 방출시키고자 하는 패키지의 개발은 계속 진행되고 있는 바, 이에 본 발명은 반도체 패키지의 크기를 보다 경박단소화로 제조하는 동시에 칩에서 발생되는 열의 방출을 극대화시킬 수 있는 구조의 반도체 패키지를 안출한 것으로서, 반도체 칩의 일면과 리드의 일부가 외부로 노출된 구조의 반도체 패키지를 제공하는데 그 목적이 있다.As described above, the development of a package for releasing heat generated from a semiconductor chip more efficiently continues, and according to the present invention, the size of the semiconductor package is manufactured in a thinner and lighter size, and at the same time, the heat generated from the chip is released. It is an object of the present invention to provide a semiconductor package having a structure capable of maximizing the semiconductor package, and a surface of one side of the semiconductor chip and a part of the lead is exposed to the outside.

도 1a,1b는 본 발명에 따른 반도체 패키지의 일실시예를 나타내는 단면도 및 저면도,1A and 1B are a cross-sectional view and a bottom view showing an embodiment of a semiconductor package according to the present invention;

도 2a,2b는 본 발명에 따른 반도체 패키지의 다른 실시예를 나타내는 단면도 및 저면도,2A and 2B are a cross-sectional view and a bottom view of another embodiment of a semiconductor package according to the present invention;

도 3a,3b,3c는 본 발명에 따른 반도체 패키지의 또 다른 실시예를 나타내는 단면도, 평면도 및 측면도,3A, 3B, and 3C are cross-sectional views, top views, and side views showing yet another embodiment of a semiconductor package according to the present invention;

도 4와 도 5는 도 1의 반도체 패키지에서 리드의 끝부분의 구조가 다른 반도체 패키지를 나타내는 단면도,4 and 5 are cross-sectional views illustrating semiconductor packages having different structures of ends of leads in the semiconductor package of FIG. 1;

도 6a,6b는 도 1의 반도체 패키지에서 몰딩수지의 구조가 다른 반도체 패키지를 나타내는 단면도,6A and 6B are cross-sectional views illustrating semiconductor packages having different molding resin structures in the semiconductor package of FIG. 1;

도 7은 도 3a,3b,3c의 반도체 패키지에서 리드의 구조가 다른 반도체 패키지를 나타내는 단면도.FIG. 7 is a cross-sectional view of a semiconductor package having a different lead structure in the semiconductor packages of FIGS. 3A, 3B, and 3C; FIG.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10 : 반도체 패키지 12 : 리드10 semiconductor package 12 lead

14 : 반도체 칩 16 : 와이어14 semiconductor chip 16: wire

18 : 접착수단 20 : 몰딩수지22 : 돌기18: bonding means 20: molding resin 22: projection

이하, 첨부도면을 참조로 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 수직절곡된 리드프레임의 리드(12)와, 이 리드(12)의 상단 저면과 접착수단(18)으로 부착된 반도체 칩(14)과, 상기 리드(12)와 반도체 칩(10)의 본딩패드간에 연결된 와이어(16)와, 상기 리드(12)의 일부분과 상기 반도체 칩(10)의 저면을 외부로 노출시키면서 몰딩하고 있는 수지(20)로 구성된 것을 특징으로 한다.According to an embodiment of the present invention, a lead 12 of a vertically bent lead frame, a semiconductor chip 14 attached to an upper bottom surface of the lead 12, and an adhesive means 18, the lead 12 and the semiconductor chip 10 are provided. The wire 16 is connected between the bonding pads of the, and a portion of the lead 12 and the resin 20 is molded while exposing the bottom surface of the semiconductor chip 10 to the outside.

상기 수직절곡된 리드(12)의 노출부위는 하단끝면만을 노출시키거나, 하단의끝면과 그 외측면을 노출시키거나, 하단의 끝면과 그 외측면과 상단의 바깥쪽 끝부분을 노출시키게 된다.The exposed portion of the vertically bent lead 12 exposes only the lower end surface, or exposes the lower end and its outer surface, or exposes the lower end and its outer surface and the outer end of the upper end.

특히, 상기 수직절곡된 리드(12)의 하단끝면을 하프에칭(Half-etching)을 시켜 몰딩수지(20)의 안쪽으로 위치시킴에 따라 인출단자를 부착시킬 수 있는 랜드로 형성시키는 동시에 수지와의 계면박리를 방지할 수 있도록 한다.In particular, the bottom end surface of the vertically bent lead 12 is half-etched to position the inside of the molding resin 20 so as to form a land to which the outgoing terminal can be attached. Prevent interfacial peeling.

또한, 상기 수직절곡되어 외부로 노출된 리드(12)의 하단 양측을 단차지게 형성하여 수지(20)와의 결합력을 증대시킬 수 있다.In addition, it is possible to increase the bonding force with the resin 20 by forming both sides of the lower end of the lead 12 vertically bent and exposed to the outside.

또한, 상기 반도체 칩(14)의 저면 테두리 일부에도 수지(20)가 몰딩되도록 하여, 칩(14)과 수지(20)간의 결합력을 증대시킬 수 있도록 한다.In addition, the resin 20 is also molded to a part of the bottom edge of the semiconductor chip 14 so that the bonding force between the chip 14 and the resin 20 can be increased.

더욱 바람직하게는, 상기 리드(12)의 하단을 다시 한번 수직 절곡하여 외부로 노출되는 면적을 높일 수 있도록 한다.More preferably, the lower end of the lead 12 is once again vertically bent to increase the area exposed to the outside.

여기서 본 발명을 실시예로서, 첨부된 도면을 참조하여 더욱 상세하게 설명하면 다음과 같다.Herein, the present invention will be described in more detail with reference to the accompanying drawings.

첨부한 도 1a,1b는 본 발명에 따른 반도체 패키지의 일실시예를 나타내는 단면도 및 저면도로서, 도시한 바와 같이 상기 반도체 패키지(10)는 반도체 칩의 일면과 리드의 일부분이 외부로 노출된 패키지이다.1A and 1B are cross-sectional views and bottom views illustrating one embodiment of a semiconductor package according to the present invention. As illustrated, the semiconductor package 10 includes a package in which one surface of a semiconductor chip and a portion of a lead are exposed to the outside. to be.

상기 반도체 패키지(10)의 리드(12)는 상단이 수평방향으로 하단이 수직방향으로 직각 절곡된 형태로서, 상기 리드(12)의 상단 저면과 반도체 칩(10)의 상면 테두리간이 접착수단(18)에 의하여 부착되어진다.The lead 12 of the semiconductor package 10 is bent at right angles in a horizontal direction and at a lower end in a vertical direction, and a bonding means 18 is formed between an upper bottom surface of the lead 12 and an upper edge of the semiconductor chip 10. Is attached.

또한, 상기 반도체 칩(10)의 상면 안쪽으로 형성된 본딩패드와 상기리드(12)간에 와이어(16)가 본딩되어진다.In addition, a wire 16 is bonded between the bonding pad formed inside the upper surface of the semiconductor chip 10 and the lead 12.

상기의 상태에서 반도체 칩(10)의 저면과 리드(12)의 하단끝면을 제외하고, 반도체 칩(10)의 상면과 측면, 그리고 와이어(16)와 리드(12)등이 몰딩수지(20)로 몰딩되어짐으로써, 도 1b에 도시한 바와 같이 반도체 칩(10)의 저면과 리드(12)의 하단끝면이 외부로 노출된 패키지가 달성되어진다.In the above state, except for the bottom surface of the semiconductor chip 10 and the bottom end surface of the lead 12, the top and side surfaces of the semiconductor chip 10, the wire 16, the lead 12, and the like are molded resin 20. By being molded in, a package in which the bottom surface of the semiconductor chip 10 and the bottom end surface of the lid 12 are exposed to the outside as shown in FIG. 1B is achieved.

여기서 본 발명의 다른 실시예를 첨부한 도 2a,2b를 참조로 설명한다.Herein, another embodiment of the present invention will be described with reference to FIGS. 2A and 2B.

첨부한 도 2a에 도시한 반도체 패키지는 도 1a를 참조로 설명한 본 발명의 일실시예의 반도체 패키지와 같이 반도체 칩(14)과 리드(12)의 일부분이 외부로 노출된 형태의 패키지로서, 수직절곡된 리드(12)의 하단 끝면외에 하단 바깥쪽면까지 외부로 노출되게 몰딩수지(20)로 몰딩된 구조를 그 특징으로 한다.The semiconductor package illustrated in FIG. 2A is a package in which a portion of the semiconductor chip 14 and the lead 12 are exposed to the outside, like the semiconductor package of the embodiment of the present invention described with reference to FIG. 1A, and is vertically bent. In addition to the lower end surface of the lead 12 is characterized in that the structure molded with a molding resin 20 to be exposed to the outside to the lower outer surface.

특히, 상기 반도체 패키지(10)의 각 구석쪽에 위치한 리드(12)는 도 2b에 도시한 바와 같이, 바깥쪽면과 일측면이 동시에 노출되게 몰딩되어진다.In particular, the leads 12 located at each corner of the semiconductor package 10 are molded such that the outer side and one side thereof are simultaneously exposed as shown in FIG. 2B.

따라서, 리드(12)의 하단 외측면까지 외부로 노출되어, 반도체 칩(14)으로 부터의 열을 보다 용이하게 외부로 방출시킬 수 있게 된다.Therefore, it is exposed to the outside to the bottom outer surface of the lead 12, it is possible to more easily discharge the heat from the semiconductor chip 14 to the outside.

첨부한 도 3a,3b,3c는 본 발명에 따른 반도체 패키지의 또 다른 실시예를 나타내는 도면으로서, 이를 참조로 설명하면 다음과 같다.3A, 3B, and 3C are diagrams illustrating still another embodiment of a semiconductor package according to the present invention, which will be described below with reference to the drawings.

도 3a에 도시한 반도체 패키지는 도 2a를 참조로 설명한 본 발명의 다른 실시예의 반도체 패키지와 같이 반도체 칩(14)과 리드(12)의 일부분이 외부로 노출된 형태의 패키지로서, 수직절곡된 리드(12)의 하단 끝면과 하단 바깥쪽면외에 상단 바깥쪽 일부면까지 외부로 노출되게 몰딩수지(20)로 몰딩된 구조를 그 특징으로 한다.The semiconductor package illustrated in FIG. 3A is a package in which a portion of the semiconductor chip 14 and the lead 12 are exposed to the outside, like the semiconductor package of another embodiment of the present invention described with reference to FIG. 2A. Characterized by a structure molded with a molding resin 20 so as to be exposed to the outside to the upper outer portion of the outer surface besides the lower end surface and the lower outer surface of (12).

이때, 상기 리드(12)는 하단 끝면과 하단 바깥쪽면외에 상단 바깥쪽 일부면까지 외부로 노출됨에 따라, 외부로 노출된 면적이 크기 때문에 몰딩수지(20)와의 결합력이 약화될 수 있는 바, 첨부한 도 7에 도시한 바와 같이 수직절곡된 리드(12)의 하단 양측면에 에칭 처리를 하여 돌기(22)를 형성하여 줌으로써, 몰딩수지(20)와의 결합력을 증대시킬 수 있다.In this case, as the lead 12 is exposed to the outside of the upper end portion and the lower outer side of the lower outer surface, the bonding force with the molding resin 20 can be weakened because the area exposed to the outside is large. As shown in FIG. 7, by forming the protrusions 22 by etching the lower ends of the leads 12 vertically bent, the bonding force with the molding resin 20 can be increased.

여기서 도 1a,1b에 도시한 반도체 패키지에서 리드의 일부구조가 다른 반도체 패키지를 첨부한 도 4를 참조로 설명하면 다음과 같다.1A and 1B, the semiconductor package shown in FIGS. 4A and 4B which is attached to a semiconductor package having a different structure of a lead is as follows.

상기 수직절곡된 리드(12)의 하단끝면이 외부로 노출되어 있는 바, 이 하단끝을 하프에칭시킴에 따라, 몰딩수지(20)와 평행하게 위치되어, 몰딩수지(20)와 리드(12)의 하단끝면 사이의 계면박리 현상을 방지할 수 있게 되고, 인출단자를 부착시킬 수 있는 랜드로서의 역할을 하게 된다.The lower end face of the vertically bent lead 12 is exposed to the outside. As the lower end is half-etched, the lower end face is positioned parallel to the molding resin 20, and thus the molding resin 20 and the lead 12 are exposed. It is possible to prevent the interfacial peeling phenomenon between the lower end surface of the, and to serve as a land to attach the withdrawal terminal.

본 발명의 바림직한 실시예로서, 도 1a,1b에 도시한 반도체 패키지에서 몰딩수지의 구조가 약간 다른 반도체 패키지를 첨부한 도 6a,6b를 참조로 설명하면 다음과 같다.As a preferred embodiment of the present invention, the semiconductor package shown in FIGS. 1A and 1B will be described with reference to FIGS. 6A and 6B to which semiconductor packages with slightly different structures of molding resins are attached.

도 6a,6b의 반도체 패키지는 반도체 칩(14)의 저면과 수직절곡된 리드(12)의 하단끝면이 에칭등으로 인출단자가 부착될 수 있도록 외부로 노출되되, 상기 반도체 칩(14)의 저면이 모두 노출되지 않도록 몰딩수지(20)가 칩(14)의 저면 테두리 일부에까지 연장 몰딩되어져 이루어진 구조이다.6A and 6B, the bottom end surface of the lead 12, which is vertically bent from the bottom surface of the semiconductor chip 14, is exposed to the outside so that the lead terminal may be attached by etching or the like, and the bottom surface of the semiconductor chip 14 may be exposed. The molding resin 20 is molded to extend to a part of the bottom edge of the chip 14 so as not to expose all of them.

따라서, 몰딩수지(20)와 칩(14)사이로 침투할 수 있는 습기의 침투경로가 길어지게 되어 칩(14)의 성능을 향상시킬 수 있고, 칩(14)과 몰딩수지(20)간의 접촉면적이 증가하여 결합력을 증대시킬 수 있다.Therefore, the penetration path of moisture that can penetrate between the molding resin 20 and the chip 14 is long, so that the performance of the chip 14 can be improved, and the contact area between the chip 14 and the molding resin 20 is increased. This increase can increase the bonding force.

첨부한 도 5는 도 1의 반도체 패키지에서 리드의 끝부분의 구조가 다른 반도체 패키지를 나타내는 단면도로서, 도 5의 반도체 패키지는 상기 리드(12)의 하단끝이 반도체 칩(14)쪽으로 다시 한번 수직 절곡되어진 형태의 패키지로서, 리드(12)의 외부 노출 면적이 증대되어 열방출 효과를 높일 수 있게 된다.5 is a cross-sectional view illustrating a semiconductor package having a different structure of an end portion of a lead in the semiconductor package of FIG. 1. In the semiconductor package of FIG. 5, the lower end of the lead 12 is once again perpendicular to the semiconductor chip 14. As a package in a bent form, the external exposed area of the lid 12 is increased to enhance the heat dissipation effect.

이상에서의 실시예와 같은 반도체 패키지는 반도체 칩(14)의 일면과 리드(12)의 일부가 외부로 노출되도록 제조됨에 따라, 반도체 칩(14)에서 발생되는 열은 칩의 저면으로 직접 방출되거나, 칩(14)과 접착수단(14)과 리드(12)를 경유하여 방출되거나, 칩(14)과 와이어(16)와 리드(12)를 경유하여 방출될 수 있어, 열방출효과를 극대화시킬 수 있게 된다.As the semiconductor package as described above is manufactured such that one surface of the semiconductor chip 14 and a part of the lead 12 are exposed to the outside, the heat generated from the semiconductor chip 14 is directly discharged to the bottom of the chip, or , Can be released via the chip 14 and the bonding means 14 and the lead 12, or can be released via the chip 14, the wire 16 and the lead 12, to maximize the heat dissipation effect It becomes possible.

이상에서 본 바와 같이 본 발명에 따른 반도체 패키지에 의하면, 반도체 칩과 리드의 일부를 외부로 노출시킴에 따라, 패키지 자체의 크기를 보다 경박단소화로 제조할 수 있고, 칩에서 발생되는 열을 외부로 용이하게 방출시킬 수 있는 장점이 있다.As described above, according to the semiconductor package according to the present invention, by exposing a portion of the semiconductor chip and the lead to the outside, the size of the package itself can be manufactured in a lighter and thinner, the heat generated from the chip is external There is an advantage that can be easily released.

Claims (8)

수직 절곡된 리드프레임의 리드(12)와, 상기 리드(12)의 상단 저면과 접착수단(18)으로 부착되는 반도체 칩(14)과, 상기 리드(12)와 반도체 칩(10)의 본딩패드간에 연결된 와이어(16)와, 상기 리드(12)의 일부분과 상기 반도체 칩(10)의 저면을 외부로 노출시키면서 몰딩하고 있는 수지(20)를 포함하는 반도체 패키지에 있어서,A lead 12 of the vertically bent lead frame, a semiconductor chip 14 attached to an upper bottom surface of the lead 12 and an adhesive means 18, and a bonding pad of the lead 12 and the semiconductor chip 10 A semiconductor package comprising a wire 16 connected therebetween and a resin 20 molded while exposing a portion of the lead 12 and a bottom surface of the semiconductor chip 10 to the outside. 상기 수직 절곡된 리드(12)는 하단 끝면과 그 바깥쪽 외측면이 노출되어진 것을 특징으로 하는 반도체 패키지.The vertically bent lead 12 is a semiconductor package, characterized in that the lower end surface and the outer outer surface is exposed. 삭제delete 삭제delete 제 1 항에 있어서, 상기 수직 절곡된 리드(12)의 노출부위는 하단 끝면과 그 바깥면 외측면 외에 상단의 바깥쪽 끝부분 일부가 더 노출되는 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1, wherein the exposed portion of the vertically bent lead (12) further exposes a portion of the outer end portion of the upper portion in addition to the lower end surface and the outer surface outer portion thereof. 삭제delete 제 1 항에 있어서, 상기 수직 절곡되어 외부로 노출된 리드(12)의 하단 양측면에 수지(20)와의 결합력을 증대시키도록 돌기(22)가 형성된 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1, wherein protrusions (22) are formed on both sides of the lower ends of the leads (12) vertically bent and exposed to the outside to increase the bonding force with the resin (20). 제 1 항에 있어서, 상기 칩(14)과 수지(20)간의 결합력을 증대시킬 수 있도록 반도체 칩(14)의 저면 테두리 일부에 수지(20)가 몰딩되도록 한 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1, wherein the resin (20) is molded in a part of the bottom edge of the semiconductor chip (14) so as to increase the bonding force between the chip (14) and the resin (20). 삭제delete
KR10-1999-0048981A 1999-11-05 1999-11-05 Semiconductor package KR100384080B1 (en)

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JPH06188333A (en) * 1992-12-17 1994-07-08 Fujitsu Ltd Semiconductor device
US5677566A (en) * 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
KR19980025881A (en) * 1996-10-05 1998-07-15 김광호 Lead frame for chip scale package and chip scale package using the same
KR19980039679A (en) * 1996-11-28 1998-08-17 황인길 Lead-on Chip Area Array Bumped Semiconductor Package
KR19990016571A (en) * 1997-08-18 1999-03-15 윤종용 High heat dissipation lead-on chip package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06188333A (en) * 1992-12-17 1994-07-08 Fujitsu Ltd Semiconductor device
US5677566A (en) * 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
KR19980025881A (en) * 1996-10-05 1998-07-15 김광호 Lead frame for chip scale package and chip scale package using the same
KR19980039679A (en) * 1996-11-28 1998-08-17 황인길 Lead-on Chip Area Array Bumped Semiconductor Package
KR19990016571A (en) * 1997-08-18 1999-03-15 윤종용 High heat dissipation lead-on chip package

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