KR100365422B1 - Method for forming potential barrier at semiconductor substrate - Google Patents
Method for forming potential barrier at semiconductor substrate Download PDFInfo
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- KR100365422B1 KR100365422B1 KR1019950069554A KR19950069554A KR100365422B1 KR 100365422 B1 KR100365422 B1 KR 100365422B1 KR 1019950069554 A KR1019950069554 A KR 1019950069554A KR 19950069554 A KR19950069554 A KR 19950069554A KR 100365422 B1 KR100365422 B1 KR 100365422B1
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- 238000005036 potential barrier Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 229910052796 boron Inorganic materials 0.000 claims abstract description 32
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 25
- 230000007547 defect Effects 0.000 abstract description 15
- 238000005468 ion implantation Methods 0.000 abstract description 9
- -1 boron ions Chemical class 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
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Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 더욱 상세하게는 반도체 소자의 제조시, 기생전류의 흐름을 억제하기 위하여 반도체 기판에서의 매몰층과 매몰층 하부사이의 전위 장벽을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a potential barrier between a buried layer and a bottom of a buried layer in a semiconductor substrate in order to suppress parasitic current flow in manufacturing a semiconductor device. will be.
일반적으로 반도체 기판에서 매몰층이 형성되는 경우에는 매몰층과 매몰층 하부사이의 기생 전류의 흐름을 억제하기 위하여, 그들 사이에 전위장벽을 형성하게 된다. 대표적으로, 전위 장벽은 고농도의 붕소층으로 이루어진다. 고농도 붕소층의 전위 장벽을 형성하는 종래의 방법은 고에너지 이온 주입기를 이용하여 매몰층의 하부에 붕소 이온을 주입하는 것으로 이루어진다. 그러나, 이러한 종래의 방법은 공정이 비교적 단순하다는 장점이 있지만, 높은 농도에서 이온 주입을 실시하는 경우에는 침입형 실리콘 원자가 발생한다는 문제가 있다. 침입형 실리콘 원자는 붕소층을 가로지르는 적체형 결함을 형성하고, 이러한 적체형 결함은 매몰층과 매몰층 하부사이의 전류 통로로 작용하여 소자에 치명적인 영향을 미친다. 따라서, 상기의 적체형 결함의 문제로 인하여 종래의 방법은 적체형 결함이 발생하지 않을 정도의 낮은 농도에서 이온 주입을 실시할 수밖에 없었기 때문에, 높은 전위 장벽을 형성할 수 없었다는 문제점이 있었다.In general, when a buried layer is formed in a semiconductor substrate, a potential barrier is formed therebetween to suppress the flow of parasitic current between the buried layer and the bottom of the buried layer. Typically, the dislocation barrier consists of a high concentration of boron layers. The conventional method of forming the potential barrier of the high concentration boron layer consists of implanting boron ions in the lower part of the buried layer using a high energy ion implanter. However, such a conventional method has an advantage that the process is relatively simple, but there is a problem that invasive silicon atoms are generated when ion implantation is performed at a high concentration. Invasive silicon atoms form a stacked defect across the boron layer, which acts as a current path between the buried layer and the bottom of the buried layer, which has a fatal effect on the device. Therefore, due to the problem of the stacked defect, the conventional method had to perform ion implantation at a low concentration such that the accumulated defect did not occur, and thus there was a problem that a high potential barrier could not be formed.
따라서, 본 발명의 목적은 상기의 종래의 문제점을 해결하기 위하여 안출된 것으로, 붕소를 고농도로 이온주입하여 충분히 높은 전위 장벽을 형성하면서도, 고농도 붕소측의 전위 장벽내에 침입형 실리콘 원자가 존재하지 않도록하여 전위 장벽내에서 적체형 결함의 발생을 최소화시킬 수 있는, 반도체 기판에서의 전위 장벽을 형성하는 방법을 제공하는 데에 있다.Accordingly, an object of the present invention is to solve the above-mentioned conventional problems, and to form a sufficiently high potential barrier by implanting boron in a high concentration so that the invasive silicon atoms do not exist in the potential barrier on the high concentration boron side. It is to provide a method of forming a potential barrier in a semiconductor substrate that can minimize the occurrence of stacked defects within the potential barrier.
상기의 목적을 달성하기 위하여, 본 발명에 따른 반도체 기판에서의 전위 장벽을 형성하는 방법은,In order to achieve the above object, a method of forming a potential barrier in a semiconductor substrate according to the present invention,
(가) 매몰층의 하부에 붕소를 이온 주입하여 고농도 붕소층을 형성하는 단계; 및(A) implanting boron in the lower portion of the buried layer to form a high concentration boron layer; And
(나) 상기 고농도 붕소층의 하부에 4가 원자를 이온주입하는 단계를 포함하는 것을 특징으로 한다.(B) ion implanting tetravalent atoms in the lower portion of the high concentration boron layer.
본 발명에 따른 상기의 방법에 있어서, 단계(나)에서 4가 원자가 이온주입되는 깊이는 고농도 붕소층보다 약 2㎛ 이상 더 깊은 것이 바람직하다.In the above method according to the present invention, the depth of the tetravalent valence ion implantation in step (b) is preferably about 2 μm or more deeper than the high concentration boron layer.
그리고, 상기 4가의 원자는 실리콘 또는 게르마늄 것이 바람직하다.The tetravalent atom is preferably silicon or germanium.
또한, 상기의 단계(나)에서 4가 원자의 이온주입 농도는 10×1014ions/㎠ ∼ 10×1016ions/㎠인 것이 바람직하다.In addition, the ion implantation concentration of the tetravalent atom in the above step (b) is preferably 10 × 10 14 ions / cm 2 to 10 × 10 16 ions / cm 2.
그 밖에, 상기의 단계 (나) 이후에는 열처리 단계를 수행하는 것이 바람직하다.In addition, it is preferable to perform a heat treatment step after the step (b).
본 발명에 의하면, 붕소를 이온주입하여 고농도 붕소층을 형성한 후, 4가 원자를 붕소층보다 더 깊게 이온주입하여 붕소층 내의 적체형 결함을 붕소층 밖으로 이동시킴으로써, 붕소층 내에 적체형 결함이 없을 뿐만 아니라 충분히 높은 전위장벽을 형성할 수 있다.According to the present invention, after implanting boron to form a high concentration boron layer, the ion-implanted tetravalent atoms are implanted deeper than the boron layer to move the accumulated defects in the boron layer out of the boron layer, whereby the accumulated defects in the boron layer Not only is it possible to form a sufficiently high potential barrier.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 상세히 설명하기로한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제 1도 (가) 내지 (라)는 본 발명의 바람직한 실시예에 따른, 반도체 기판에서 매몰층과 매몰층 하부사이의 전위장벽을 형성하는 방법을 설명하기 위한 도면이다.1 (a) to (d) are diagrams for explaining a method for forming a potential barrier between a buried layer and a bottom of a buried layer in a semiconductor substrate according to a preferred embodiment of the present invention.
우선, 제 1 도(가)에서 도시된 바와같이, 실리콘 기판(10)의 상부에 부분산화막(12) 및 매몰층(14)을 형성한다.First, as shown in FIG. 1A, the partial oxide film 12 and the buried layer 14 are formed on the silicon substrate 10.
그런다음, 제 1 도(나)에서 도시된 바와같이, 고에너지 이온주입기(미도시)를 이용하여, 붕소를 화살표로 도시된 바와같이, 매몰층(14)의 바닥 부분보다 더 깊은 점선으로 도시된 부분의 깊이까지 이온주입하여 예비 전위장벽(16)을 형성한다. 이때, 이 예비전위장벽(16)을 확대하여 보면, 예비전위장벽(16)의 실리콘 격자 구조를 보여주는 도면인 제 2 도(가)에서 도시된 바와같이, 실리콘 격자(110)의 사이에 침입형 실리콘 원저(112)가 존재한다. 이렇게 침입형 실리콘원자(112)가 존재하는 예빈 전위장벽(16)을 열처리하는 경우에는 제 2도(나)에서 도시된 바와같이 적체형 결함(114)이 형성된다.Then, using a high energy ion implanter (not shown), as shown in FIG. 1 (b), boron is shown in a dotted line deeper than the bottom portion of the buried layer 14, as shown by the arrow. The preliminary potential barrier 16 is formed by ion implantation up to the depth of the portion. At this time, when the preliminary potential barrier 16 is enlarged, as shown in FIG. 2A, which is a view showing the silicon lattice structure of the prepotential barrier 16, an intrusion type is formed between the silicon lattice 110. There is a silicon original 112. When the preliminary potential barrier 16 in which the interstitial silicon atoms 112 are present is heat-treated, the accumulated defect 114 is formed as shown in FIG.
따라서, 상기의 적체형 결함(114)이 형성되는 것을 방지하기 위하여, 제 1 도(다)에서 도시된 바와같이, 바람직한 실리콘 또는 게르마늄과 같은 4가 원자를 10×1014ions/㎠ ∼ 10×1016ions/㎠의 농도에서, 예비전위장벽(16)의 깊이보다 더욱 깊은 또다른 점선으로 도시된 부분의 깊이 까지 이온주입한다. 이때, 4가 원자가 이온주입되는 깊이는 예비 전위장벽(16)보다 약 2㎛ 이상 더 깊은 것이 바람직하다.Therefore, in order to prevent the formation of the stacked defect 114, tetravalent atoms, such as silicon or germanium, which are preferable, as shown in FIG. 1 (c), are selected from 10 x 10 14 ions / cm 2 to 10 x At a concentration of 10 16 ions / cm 2, ion implantation is carried out to the depth of the portion shown by another dotted line deeper than the depth of the prepotential barrier 16. In this case, the depth of the tetravalent valence ion implantation is preferably about 2 μm or more deeper than the preliminary potential barrier 16.
이러한 4가 원자의 이온 주입후, 예비 전위장벽(16)을 확대하여 보면, 예비전위장벽(16)의 실리콘 격자 구조를 보여주는 도면인 제 3 도(가)에서 도시된 바와 같이, 침입형 실리콘원자(112)가 존재하고는 있었지만 빈자리(도면에서는 ×표시로 도시함)가 존재하고 있다.After the ion implantation of the tetravalent atom, the preliminary potential barrier 16 is enlarged, and as shown in FIG. 3 (a), which shows the silicon lattice structure of the prepotential barrier 16, the invasive silicon atom. There existed 112, but there exist an empty seat (shown by x mark in drawing).
그런다음, 열처리를 진행하여 제 1 도(라)에서 도시된 바와같이 전위장벽(16A)을 형성한다. 이때, 전위장벽(16A)을 확대하여 보면, 제 3 도(나)에서 도시된 바와같이 열처리전에 전위 장벽내에 존재하였던 침입형 실리콘 원자(112)가 빈자리를 채우고 있다.Then, heat treatment is performed to form the dislocation barrier 16A as shown in FIG. At this time, when the potential barrier 16A is enlarged, the invasive silicon atoms 112 that existed in the potential barrier before the heat treatment, as shown in FIG.
따라서, 전위 장벽(16A)에는 침입형 실리콘 원자로 인한 적체형 결함이 존재하고 있지 않다.Therefore, there is no accumulated defect due to the invasive silicon atom in the potential barrier 16A.
전위 장벽(16A)의 하부에서 떨어진 곳에서 적체형 결함(18)이 존재하고 있지만, 이는 전위 장벽에 아무런 영향을 주지 않는다.Although there are accumulated defects 18 at the bottom of the potential barrier 16A, this has no effect on the potential barrier.
이상에서와 같이, 본 실시예에 의하면, 붕소를 이온 주입하여 고농도 붕소층을 형성한 후, 4가 원자를 붕소층보다 더 깊게 이온주입하여 붕소층내의 적체형 결함을 붕소층 밖으로 이동시킴으로써 적체형 결함이 없는 전위장벽을 충분히 높게 형성할 수 있다. 또한, 붕소층 아래에 형성된 적체결함은 전위장벽에 전혀 영향을 미치지 않을 뿐만 아니라, 금속을 모으는 게터링 층으로 사용될 수 있다는 부수적인 효과를 제공한다.As described above, according to this embodiment, after implanting boron to form a high concentration boron layer, the tetravalent atoms are implanted deeper than the boron layer to move the stack-type defects in the boron layer out of the boron layer. A potential barrier free of defects can be formed sufficiently high. In addition, the accumulation defects formed under the boron layer not only affect the dislocation barrier at all, but also provide a side effect of being used as a gettering layer for collecting metal.
또한, 본 발명은 상기의 실시예에 한정되는 것은 아니면, 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously change and implement in the range which does not deviate from the summary.
제 1 도 (가) 내지 (라)는 본 발명의 바람직한 실시예에 따른, 반도체 기판에서 매몰층과 매몰층 하부사이의 전위장벽을 형성하는 방법을 설명하기 위한 도면.1A to 1D illustrate a method of forming a potential barrier between a buried layer and a bottom of a buried layer in a semiconductor substrate according to a preferred embodiment of the present invention.
제 2 도 (가) 및 (나)는 각각 붕소를 이온주입하였지만 본 발명의 바람직한 실시예에 따라 4가지 이온을 주입하는 단계를 수행하지 않았을 때 및 그 이후에 열처리 공정을 수행하였을 때 예비 전위장벽의 실리콘 격자 구조를 보여주는 도면.Figure 2 (a) and (b) shows the preliminary potential barrier when boron is ion implanted, respectively, but when the four ions are not implanted according to the preferred embodiment of the present invention and after the heat treatment process is performed. Showing the silicon lattice structure of the structure.
제 3 도 (가) 및 (나)는 각각, 본 발명의 실시예에 따라 4가 이온을 주입하였을 때 및 그 이후에 계속되는 열처리 공정후의 전위 장벽의 실리콘 격자 구조를 보여주는 도면.3 (a) and (b) show the silicon lattice structure of the dislocation barrier, respectively, after implantation of tetravalent ions and after the subsequent heat treatment process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 실리콘 기판 12 : 부분산화막10 silicon substrate 12 partial oxide film
14 : 매몰층 16 : 예비전위장벽14: investment layer 16: preliminary potential barrier
16A : 전위장벽 110 : 실리콘 격자16A: potential barrier 110: silicon lattice
112 : 침입형 실리콘원자 114 : 적체형 결함.112: invasive silicon atom 114: accumulated defect.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950069554A KR100365422B1 (en) | 1995-12-30 | 1995-12-30 | Method for forming potential barrier at semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970051949A KR970051949A (en) | 1997-07-29 |
| KR100365422B1 true KR100365422B1 (en) | 2003-03-03 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950069554A KR100365422B1 (en) | 1995-12-30 | 1995-12-30 | Method for forming potential barrier at semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100365422B1 (en) |
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1995
- 1995-12-30 KR KR1019950069554A patent/KR100365422B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970051949A (en) | 1997-07-29 |
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