KR100353402B1 - Method of fabricating a semiconductor device - Google Patents

Method of fabricating a semiconductor device Download PDF

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KR100353402B1
KR100353402B1 KR1019990013786A KR19990013786A KR100353402B1 KR 100353402 B1 KR100353402 B1 KR 100353402B1 KR 1019990013786 A KR1019990013786 A KR 1019990013786A KR 19990013786 A KR19990013786 A KR 19990013786A KR 100353402 B1 KR100353402 B1 KR 100353402B1
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insulating film
gate insulating
semiconductor substrate
gate electrode
forming
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KR20000066568A (en
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허기재
이득희
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주식회사 하이닉스반도체
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Priority to US09/434,521 priority patent/US6410382B1/en
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

본발명은 반도체 소자의 제조방법에 관한 것으로, 핫캐리어 내성의 개선과 동시에 p-채널 트랜지스터의 전기적인 특성 저하의 방지를 동시에 꾀할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of simultaneously improving the hot carrier resistance and preventing the deterioration of electrical characteristics of a p-channel transistor.

본발명의 목적을 달성하기 위한 제조방법은, 반도체 기판상에 게이트절연막을 형성하고, 상기 게이트 절연막 위에 게이트 전극을 형성하며, 상기 게이트전극 양측 반도체 기판내에 저농도의 불순물 이온을 주입하고, 상기 게이트전극 양측벽에 사이드월 스페이서를 형성하며, 상기 사이드월 스페이서를 마스크로하여 상기 반도체 기판내에 고농도의 불순물 이온을 주입하여 소스/드레인을 형성하는 공정을 포함하고, 상기 사이드월 스페이서를 형성하는 공정전에 또는 공정후에 게이트전극에 인접한 게이트 전극 바깥측 게이트절연막에 질소이온을 주입하는 공정을 추가로 실시하는 것을 특징으로하고, 결과적으로 트랜지스터의 채널영역 상부에는 실리콘 산화막의 게이트절연막을 갖고, 채널 바깥측 반도체 기판상면에는 질소를 포함하는 게이트절연막을 갖는 반도체 소자가 제조된다.A manufacturing method for achieving the object of the present invention, forming a gate insulating film on a semiconductor substrate, a gate electrode on the gate insulating film, implanting a low concentration of impurity ions into the semiconductor substrate on both sides of the gate electrode, Forming sidewall spacers on both sidewalls, implanting high concentrations of impurity ions into the semiconductor substrate using the sidewall spacers as a mask, and forming a source / drain; After the process, a process of injecting nitrogen ions into the gate insulating film outside the gate electrode adjacent to the gate electrode is further performed. As a result, the gate insulating film of the silicon oxide film is provided on the channel region of the transistor. Gate section containing nitrogen on the upper surface A semiconductor element having a film is prepared.

Description

반도체 소자의 제조방법{METHOD OF FABRICATING A SEMICONDUCTOR DEVICE}METHODS OF FABRICATING A SEMICONDUCTOR DEVICE

본발명은 반도체 소자의 제조방법에 관한 것으로, 특히 핫 캐리어 내성(immunity)을 개선할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving hot carrier immunity.

종래의 반도체 소자 특히 MOSFET 제조시, 게이트 절연막으로서 일반적으로 열산화법으로 형성한 SiO2막을 이용하여 왔다. 그러나, 소자의 집적도가 높아지면서 채널길이가 짧아지고 결과적으로 핫 캐리어 내성의 저하가 큰 문제로 대두되었다. 그러한 문제를 해결하기 위하여 채널과 게이트 절연막사이의 에너지 밴드를 높이는 방안이 제안되었고, 이를 위해 게이트 절연막을 SiO2에서 질소를 포함하는 산화막(NO 또는 N2O)으로 대체하는 방법이 연구되고 있다.In the manufacture of conventional semiconductor devices, particularly MOSFETs, SiO 2 films generally formed by thermal oxidation have been used as gate insulating films. However, as the integration degree of the device increases, the channel length becomes shorter, and as a result, a decrease in hot carrier resistance becomes a big problem. In order to solve the problem, a method of increasing the energy band between the channel and the gate insulating film has been proposed, and a method of replacing the gate insulating film with an oxide film (NO or N 2 O) containing nitrogen in SiO 2 has been studied.

현재 알려져 있는 질소를 포함하는 게이트 절연막으로 이용한 반도체 소자의 제조방법은 다음과 같다.A method of manufacturing a semiconductor device using a gate insulating film containing nitrogen currently known is as follows.

먼저 도1a와 같이 반도체 기판(100)상에 게이트 절연막(101)으로서 NO막 또는 N2O막을 형성한다. 다음으로 상기 게이트 절연막(101)위에 폴리실리콘층과 절연막을 형성한 다음 패터닝하여 게이트 전극(102) 및 절연막 패턴(103)을 형성한다. 다음으로, 상기 절연막 패턴(103)을 마스크로하여 상기 반도체 기판(100)내에 불순물을 주입하여 게이트 전극(102) 양측 반도체 기판내에 얕은 불순물층(LDD라고도 함.)(104)을 형성한다.First, as shown in FIG. 1A, an NO film or an N 2 O film is formed on the semiconductor substrate 100 as the gate insulating film 101. Next, a polysilicon layer and an insulating film are formed on the gate insulating film 101 and then patterned to form a gate electrode 102 and an insulating film pattern 103. Next, an impurity is injected into the semiconductor substrate 100 using the insulating film pattern 103 as a mask to form a shallow impurity layer 104 (also referred to as an LDD) 104 in the semiconductor substrate on both sides of the gate electrode 102.

다음으로, 도1a의 전체 구조위에 절연막으로서 Si3N4막등을 형성한 후 이방성 에칭을 실시하여 도1b와 같이, 게이트 전극(102)과 절연막 패턴(103)의 측면에 사이드월 스페이서(105)를 형성한다. 다음으로, 상기 사이드월 스페이서(105)를 마스크로하여 상기 반도체 기판(100)내에 다시 고농도의 불순물을 주입하여 깊은 불순물층(소드/드레인)(106)을 형성한다.Next, an Si 3 N 4 film or the like is formed over the entire structure of FIG. 1A and then anisotropically etched to form sidewall spacers 105 on the side surfaces of the gate electrode 102 and the insulating film pattern 103 as shown in FIG. 1B. To form. Next, a high impurity concentration is injected again into the semiconductor substrate 100 using the sidewall spacers 105 as a mask to form a deep impurity layer (sword / drain) 106.

그러나, 상기와 같이 게이트 절연막(101) 전체를 NO막 또는 N2O막으로 형성하는 것은 핫 캐리어 내성은 개선하지만, p-채널 트랜지스터의 홀의 이동성(mobility)을 떨어뜨려 p-채널 트랜지스터의 구동능력을 저하시키는 문제가 있었다. 따라서 p-채널 트랜지스터의 홀의 이동성을 떨어뜨리지 않으면서, 핫 캐리어 내성을 향상시키기 위한 방안이 필요해 진다.However, forming the entire gate insulating film 101 as the NO film or the N 2 O film as described above improves the hot carrier resistance, but reduces the mobility of the holes of the p-channel transistor, thereby driving the p-channel transistor. There was a problem of lowering. Therefore, there is a need for a method for improving hot carrier immunity without degrading the mobility of holes in a p-channel transistor.

한편, 반도체 메모리 소자는 크게 메모리셀부와 주변회로부로 나눌 수 있는데, 상기와 같은 핫 캐리어 내성이 좋은 NO막을 게이트 절연막으로 이용하는 것이 좋다. 그러나, 메모리 셀부를 구성하는 트랜지스터의 게이트 절연막은 실리콘 산화막을 사용하는 것이 유리하다. NO막을 게이트절연막으로 이용하면 핫 캐리어 내성은 좋아지지만, 정션 누설 전류가 커져서 리프레시 주기가 짧아지기 때문이다. 따라서, 메모리셀부와 주변회로부의 게이트 절연막을 서로 다른 재료로 형성해야 될 필요가 발생한다. 이 경우 종래와 같은 반도체 소자의 제조방법에 따르면, 메모리 셀부 또는 주변회로부의 게이트절연막중 어느 하나를 먼저 형성한 후, 포토 레지스트 마스크를 이용하여, 다른 한쪽의 게이트 절연막을 후에 형성하므로, 게이트 절연막 형성공정을 2회에 걸쳐 수행하게 되어, 공정상의 번거로움이 따르게 되는 문제점이 있었다.On the other hand, the semiconductor memory device can be largely divided into the memory cell portion and the peripheral circuit portion, it is preferable to use the above-described NO film having good hot carrier resistance as the gate insulating film. However, it is advantageous to use a silicon oxide film as the gate insulating film of the transistor constituting the memory cell portion. This is because when the NO film is used as the gate insulating film, the hot carrier resistance is improved, but the refresh cycle is shortened because the junction leakage current increases. Therefore, it is necessary to form the gate insulating films of the memory cell portion and the peripheral circuit portion with different materials. In this case, according to the conventional method of manufacturing a semiconductor device, since any one of the gate insulating films of the memory cell portion or the peripheral circuit portion is formed first, the other gate insulating film is formed later using a photoresist mask, thereby forming the gate insulating film. To perform the process twice, there was a problem that the process hassle.

본발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 핫 캐리어 내성을 개선하면서도, p-채널 트랜지스터의 소자 특성을 저하시키지 않기 위해, 트랜지스터의 채널영역 상부에는 실리콘 산화막의 게이트절연막을 갖고, LDD층 상부에는 질소를 포함하는 게이트 절연막을 갖는 반도체 소자의 제조방법을 제공하는 것을 목적으로 한다.The present invention has been made to solve the above problems, and in order to improve the hot carrier resistance and not deteriorate the device characteristics of the p-channel transistor, the transistor has a gate insulating film of a silicon oxide film on the channel region, and LDD An object of the present invention is to provide a method for manufacturing a semiconductor device having a gate insulating film containing nitrogen above the layer.

본발명은 메모리 셀부의 리프레시 특성을 향상시키고 주변회로부의 핫 캐리어 내성을 개선하기 위해, 메모리셀부와 주변회로부의 소자들의 게이트 절연막을 모두 실리콘 산화막으로 형성한 후, 주변회로부의 게이트 절연막에 질소이온을 부분적으로 주입하는 공정으로 주변회로부 게이트 절연막을 질소를 포함하는 산화막으로 만듦으로써, 메모리 셀부와 주변회로부의 게이트 절연막을 동시에 형성할 수 있도록 하여 보다 용이해진 반도체 소자의 제조방법을 제공하는 것을 목적으로 한다.According to the present invention, in order to improve the refresh characteristics of the memory cell portion and improve the hot carrier resistance of the peripheral circuit portion, both gate insulating films of the elements of the memory cell portion and the peripheral circuit portion are formed of a silicon oxide film, and then nitrogen ions are applied to the gate insulating layer of the peripheral circuit portion. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is made easier by forming the gate insulating film of the peripheral circuit part by an oxide film containing nitrogen in a partial injection process, thereby simultaneously forming the gate insulating film of the memory cell part and the peripheral circuit part. .

본발명의 목적을 달성하기 위하여, 반도체 기판상에 게이트절연막을 형성하고, 상기 게이트 절연막 위에 게이트 전극을 형성하며, 상기 게이트전극 양측 반도체 기판내에 저농도의 불순물 이온을 주입하고, 상기 게이트전극 양측벽에 사이드월 스페이서를 형성하며, 상기 사이드월 스페이서를 마스크로하여 상기 반도체 기판내에 고농도의 불순물 이온을 주입하여 소스/드레인을 형성하는 공정을 포함하는 반도체 소자의 제조방법에 있어서, 상기 사이드월 스페이서를 형성하는 공정전에 또는 공정후에 게이트전극에 인접한 게이트 전극 바깥측 게이트절연막에 질소이온을 주입하는 공정을 추가로 실시하는 반도체 소자의 제조방법을 제공한다.In order to achieve the object of the present invention, a gate insulating film is formed on a semiconductor substrate, a gate electrode is formed on the gate insulating film, a low concentration of impurity ions are injected into the semiconductor substrate on both sides of the gate electrode, and the gate electrodes are formed on both sidewalls of the gate electrode. A method of manufacturing a semiconductor device comprising forming a sidewall spacer, and forming a source / drain by implanting a high concentration of impurity ions into the semiconductor substrate using the sidewall spacer as a mask. A method of manufacturing a semiconductor device is further provided, wherein a step of implanting nitrogen ions into a gate insulating film outside the gate electrode adjacent to the gate electrode before or after the step is performed.

또한, 본발명의 목적을 달성하기 위해, 메모리셀부와 주변회로부로 구성된 반도체 기판전면에 절연막을 형성하는 공정과, 상기 게이트 절연막위에 각각 메모리셀부의 게이트전극과, 주변회로부의 게이트전극을 형성하는 공정과, 상기 각 게이트 전극 양측 반도체 기판내에 저농도의 불순물 이온을 주입하여 얕은 불순물층들을 형성하는 공정과, 상기 각 게이트 전극의 양측에 사이드월 스페이서들을 형성하는 공정과, 상기 메모리셀부에 상응하는 반도체 기판상의 전체구조위에 포토레지스트 마스크를 형성하는 공정과, 상기 주변회로부의 사이드월 스페이서하의 게이트절연막에 질소이온을 주입하는 공정과, 상기 포토레지스트 마스크를 제거하는 공정과, 상기 사이드월 스페이서 바깥측의 반도체 기판내에 고농도의 불순물을 주입하여 상기 얕은 불순물층보다 상대적으로 깊은 불순물층을 형성하는 공정을 포함하는 반도체 소자의 제조방법을 제공한다.In addition, in order to achieve the object of the present invention, the step of forming an insulating film on the front surface of the semiconductor substrate consisting of the memory cell portion and the peripheral circuit portion, and the process of forming a gate electrode of the memory cell portion and the gate electrode of the peripheral circuit portion on the gate insulating film, respectively And implanting low concentration of impurity ions into the semiconductor substrate on both sides of each gate electrode to form shallow impurity layers, forming sidewall spacers on both sides of the gate electrode, and a semiconductor substrate corresponding to the memory cell portion. Forming a photoresist mask over the entire structure of the phase, implanting nitrogen ions into the gate insulating film under the sidewall spacers of the peripheral circuit portion, removing the photoresist mask, and semiconductors outside the sidewall spacers The shallow concentration by implanting a high concentration of impurities into the substrate It provides a method for manufacturing a semiconductor device comprising the step of relatively forming a deep impurity layer than the impurity layer.

도1a 및 도1b는 종래 반도체 소자의 제조공정 순서를 도시한 것이다.1A and 1B show a manufacturing process procedure of a conventional semiconductor device.

도2a 내지 도2c는 본발명에 따른 반도체 소자의 제조공정 순서를 도시한 것이다.2A to 2C illustrate a manufacturing process sequence of a semiconductor device according to the present invention.

도3은 본발명에 따른 반도체 소자의 제조공정의 다른 실시례이다.3 is another embodiment of a manufacturing process of a semiconductor device according to the present invention.

도4a 내지 도4d는 본발명에 따른 반도체 소자 제조방법의 다른 실시례이다.4A to 4D are another embodiment of a method of manufacturing a semiconductor device according to the present invention.

도5a 내지 도5d는 본발명에 따른 반도체 소자 제조방법의 또다른 실시례이다.5A to 5D are still another embodiment of a method of manufacturing a semiconductor device according to the present invention.

***** 도면부호의 설명 ********** Explanation of Drawings *****

100 : 반도체 기판 101 : 게이트 절연막100 semiconductor substrate 101 gate insulating film

102 : 게이트 전극 103 : 절연막 패턴102 gate electrode 103 insulating film pattern

104 : 얕은 불순물층 105 : 사이드월 스페이서104: shallow impurity layer 105: sidewall spacer

106 : 소스/드레인 200 : 반도체 기판106 source / drain 200 semiconductor substrate

201 : 게이트 절연막 202 : 게이트 전극201: gate insulating film 202: gate electrode

203 : 절연막 패턴 204 : 얕은 불순물층203: insulating film pattern 204: shallow impurity layer

205 : 사이드월 스페이서 207 : 소스205: sidewall spacer 207: source

208 : 드레인 209 : 포토레지스트 패턴208: drain 209: photoresist pattern

400 : 반도체 기판 401 : 게이트 절연막400: semiconductor substrate 401: gate insulating film

402 : 게이트 전극 403 : 절연막 패턴402: gate electrode 403: insulating film pattern

404 : 얕은 불순물층 405 : 사이드월 스페이서404: shallow impurity layer 405: sidewall spacer

406 : 소스/드레인 500 : 반도체 기판406: source / drain 500: semiconductor substrate

501 : 게이트 절연막 502 : 게이트 전극501: gate insulating film 502: gate electrode

503 : 절연막 패턴 504 : 얕은 불순물층503: insulating film pattern 504: shallow impurity layer

505 : 사이드월 스페이서 506 : 소스/드레인505: sidewall spacer 506: source / drain

507 : 포토레지스트 마스크507 photoresist mask

본발명의 반도체 소자 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다. 본발명의 반도체 소자는 핫캐리어 내성을 개선하고, p-채널 트랜지스터의 홀 이동도 저하를 억제하여 트랜지스터의 특성을 열화시키지 않기 위해, 게이트 전극 아래(즉 채널영역의 상부)의 게이트 절연막으로는 실리콘 산화막을 이용하고, LDD층위의 게이트 절연막에는 질소이온을 포함하는 실리콘 산화막을 이용하는 것을 특징으로 한다. 그와 같은 본발명의 반도체 소자를 제조하기 위해, 먼저 도2a와 같이 반도체 기판(200)상에 게이트 절연막(201)으로서 열산화법으로 형성한 SiO2막을 형성한다, 다음으로 상기 게이트 절연막(201)위에 폴리실리콘층과 절연막을 형성한 다음 패터닝하여 게이트 전극(202) 및 절연막 패턴(203)을 형성한다. 상기 절연막패턴(203)의 재료는 고온저압 화학기상증착법(HL CVD; high temperature low pressure chemical vapor deposition)으로 형성한 산화막(HLD산화막이라 함)이다. 다음으로, 상기 절연막 패턴(203)을 마스크로하여 상기 반도체 기판(200)내에 저농도의 p-형 불순물을 주입하여 게이트 전극(202) 양측 반도체 기판내에 얕은 불순물층(LDD라고 함)(204)을 형성한다.Referring to the accompanying drawings, a semiconductor device manufacturing method of the present invention will be described. The semiconductor device of the present invention uses silicon as the gate insulating film under the gate electrode (i.e., in the upper portion of the channel region) to improve the hot carrier resistance, suppress the decrease in the hole mobility of the p-channel transistor, and thereby deteriorate the transistor characteristics. An oxide film is used, and a silicon oxide film containing nitrogen ions is used for the gate insulating film on the LDD layer. In order to manufacture such a semiconductor device of the present invention, first, a SiO 2 film formed by thermal oxidation is formed on the semiconductor substrate 200 as the gate insulating film 201, as shown in FIG. 2A. Next, the gate insulating film 201 is formed. A polysilicon layer and an insulating film are formed thereon, and then patterned to form a gate electrode 202 and an insulating film pattern 203. The material of the insulating film pattern 203 is an oxide film (referred to as an HLD oxide film) formed by high temperature low pressure chemical vapor deposition (HL CVD). Next, a low concentration of p-type impurities are implanted into the semiconductor substrate 200 using the insulating film pattern 203 as a mask to form a shallow impurity layer (LDD) 204 in the semiconductor substrate on both sides of the gate electrode 202. Form.

다음으로, 도2a의 전체 구조위에 절연막으로서 Si3N4막등을 형성한 후 이방성 에칭을 실시하여 도2b와 같이, 게이트 전극(202)과 절연막 패턴(203)의 측면에 사이드월 스페이서(205)를 형성한다. 한편 실리콘 기판을 이루는 실리콘과 식각 선택비가 큰 SiO2막으로도 사이드월 스페이서를 형성할 수 있다.Next, after forming an Si 3 N 4 film or the like as an insulating film over the entire structure of FIG. 2A, anisotropic etching is performed, and as shown in FIG. 2B, the sidewall spacers 205 are formed on the side surfaces of the gate electrode 202 and the insulating film pattern 203. To form. Meanwhile, the sidewall spacers may be formed of silicon constituting the silicon substrate and a SiO 2 film having a high etching selectivity.

다음으로, 도2b와 같이 상기 사이드월 스페이서(205)의 바깥측으로부터 질소를 경사각 이온주입(tilt angle ion implantation)을 실시하여 게이트전극(202)의 바깥쪽의 게이트 절연막(201) 즉, 사이드월 스페이서(205) 아래의 게이트 절연막(201)에 질소이온을 주입한다. 이때, 경사각 이온주입시의 경사각은 반도체기판으로부터 약 30°정도로 하고, 이온주입에너지는 약 50KeV 내지 60KeV 정도가 적당하고 100KeV이내의 약한 에너지로 주입하는 것이 바람직하다. 이온주입에너지가 너무 높으면 질소 이온이 반도체 기판내까지 주입될 수 있기 때문에 약한 에너지로 게이트 절연막에 주입될 수 있도록 한다. 또 이때, 이온주입 경사각이 너무 낮으면, 질소 이온이 사이드월 스페이서 아래의 게이트 절연막 뿐만이 아니라, 게이트 전극 아래에 까지 주입되므로 본발명의 효과를 얻을 수 없다.Next, as shown in FIG. 2B, a tilt angle ion implantation of nitrogen is performed from the outside of the sidewall spacer 205 to form a gate insulating film 201, that is, a sidewall outside the gate electrode 202. Nitrogen ions are implanted into the gate insulating film 201 under the spacer 205. In this case, the inclination angle at the time of ion implantation is about 30 degrees from the semiconductor substrate, and the ion implantation energy is preferably about 50 KeV to about 60 KeV, and implanted with a weak energy within 100 KeV. If the ion implantation energy is too high, nitrogen ions can be implanted into the semiconductor substrate so that the energy can be implanted into the gate insulating film with weak energy. At this time, when the ion implantation inclination angle is too low, nitrogen ions are implanted not only into the gate insulating film under the sidewall spacer but also under the gate electrode, so that the effect of the present invention cannot be obtained.

상기 질소이온 주입에 의하여, 주입된 질소이온은 실리콘 기판과 게이트 절연막의 계면에 Si-N결합을 이루게 되고, 이러한 Si-N 결합에 의해 에너지 배리어가 높아져 핫 캐리어가 게이트절연막으로 주입되는 것을 방지한다.By the nitrogen ion implantation, the implanted nitrogen ions form Si-N bonds at the interface between the silicon substrate and the gate insulating film, and the energy barrier is increased by the Si-N bonds to prevent hot carriers from being injected into the gate insulating film. .

다음으로, 상기 사이드월 스페이서(205)를 마스크로하여 상기 반도체 기판(200)내에 고농도의 p+형 불순물을 주입하여 도2c와 같이, 깊은 불순물층 즉 소스(207)/드레인(208)을 형성한다. 상기 불순물로서는 BF2를 주입한다.Next, a high concentration of p + type impurities are implanted into the semiconductor substrate 200 using the sidewall spacers 205 as a mask to form a deep impurity layer, that is, a source 207 / drain 208 as shown in FIG. 2C. . BF 2 is injected as the impurity.

한편 상기 질소의 이온주입 공정은, 도2b의 사이드월 스페이서(205)를 형성하는 공정전에 실시하여도 좋다. 즉 도2a와 같이 게이트전극(202)을 형성한 다음, 상기 게이트 전극(202) 인접한 부분의 양측 게이트 절연막에 질소이온을 주입한 후, 상기 게이트 전극(202) 측벽에 사이드월을 형성하면 된다. 이경우에는, 경사각 이온주입을 실시할 수도 있으나 일반적인 이온주입을 실시해도 좋다. 사이드월을 형성하기 전에 질소 이온을 주입하는 경우에는 이온주입에너지는 10~20KeV범위인 것이 바람직하다.The ion implantation step of nitrogen may be performed before the step of forming the sidewall spacers 205 in FIG. 2B. In other words, as shown in FIG. 2A, after the gate electrode 202 is formed, nitrogen ions are implanted into both gate insulating layers adjacent to the gate electrode 202, and a sidewall is formed on the sidewall of the gate electrode 202. In this case, inclination angle ion implantation may be performed, but general ion implantation may be performed. In the case of implanting nitrogen ions before forming the sidewalls, the ion implantation energy is preferably in the range of 10 to 20 KeV.

한편, 상기 질소이온의 경사이온 주입 공정은 즉 도2b의 사이드월 스페이서(205) 형성공정 이후에, 도3과 같이 소스가 형성될 LDD층 및 게이트전극(202)위에 포토레지스트 패턴(209)을 형성하고, 드레인이 형성될 LDD층 상면의 게이트 절연막에만 실시하여도 좋다. 즉, 전계가 가장 강한 드레인 근방에서 주로 핫 캐리어 문제가 발생하기 때문이다. 도3에서 상기 포토레지스트 패턴(209)이외의 다른 모든 구성요소들은 도2b의 모든 구성요소들과 같다.On the other hand, the gradient ion implantation process of nitrogen ions, that is, after the sidewall spacer 205 forming process of FIG. 2B, as shown in FIG. 3, the photoresist pattern 209 is formed on the LDD layer and the gate electrode 202 on which the source is to be formed. And the gate insulating film on the upper surface of the LDD layer where the drain is to be formed. That is, a hot carrier problem mainly occurs near the drain having the strongest electric field. All components other than the photoresist pattern 209 in FIG. 3 are the same as all the components of FIG. 2B.

한편 상기와 같은 게이트절연막에의 질소이온 주입공정을 반도체 메모리 소자에 적용하는 방법을 설명하면 다음과 같다.Meanwhile, a method of applying the nitrogen ion implantation process to the gate insulating film as described above will be described below.

도4a 내지 도4d에서 좌측은 메모리셀부의 트랜지스터의 제조공정순서이고, 우측은 주변회로부의 트랜지스터의 제조공정 순서이다.4A to 4D, the left side shows the manufacturing process sequence of the transistor of the memory cell portion, and the right side shows the manufacturing process sequence of the transistor of the peripheral circuit portion.

먼저, 도4a와 같이, 반도체 기판(400)위에 소자간 분리영역을 형성한다. 다음으로 상기 반도체 기판(400) 전면에 게이트 절연막으로서 실리콘 산화막(SiO2)(401)을 형성한다. 다음으로, 상기 실리콘 산화막(401)위에 폴리실리콘층과 절연막을 형성한 다음 패터닝하여 메모리셀부, 주변회로부 모두 트랜지스터의 게이트 전극(402) 및 게이트 전극(402)상면을 보호하는 절연막 패턴(403)을 각각 형성한다. 다음으로, 상기 절연막 패턴(403)을 마스크로하여 상기 반도체 기판(400)내에 저농도의 불순물 이온을 주입하여 상대적으로 얕은 불순물층(LDD; lightly doped region이라고도 함)(404)을 형성한다.First, as shown in FIG. 4A, an isolation region between elements is formed on the semiconductor substrate 400. Next, a silicon oxide film (SiO 2 ) 401 is formed on the entire surface of the semiconductor substrate 400 as a gate insulating film. Next, a polysilicon layer and an insulating film are formed on the silicon oxide film 401 and then patterned to form an insulating film pattern 403 that protects the gate electrode 402 and the gate electrode 402 upper surface of the transistor in both the memory cell part and the peripheral circuit part. Form each. Next, a low concentration of impurity ions are implanted into the semiconductor substrate 400 using the insulating film pattern 403 as a mask to form a relatively shallow impurity layer (LDD) (also referred to as a lightly doped region) 404.

다음으로, 도4b에 도시한 구조의 전면에 절연막으로서 실리콘 산화막 또는 실리콘 질화막을 형성한 후 이방성 에칭을 실시하여 게이트전극의 측벽에 사이드월 스페이서(405)를 형성한다.Next, after forming a silicon oxide film or a silicon nitride film as an insulating film on the entire surface of the structure shown in Fig. 4B, anisotropic etching is performed to form sidewall spacers 405 on the sidewalls of the gate electrodes.

다음으로, 도4c와 같이, 메모리셀부의 트랜지스터위에 포토레지스트 마스크(407)를 형성한 후, 주변회로부 트랜지스터의 사이드월 스페이서 아래의 게이트절연막(401) 부위에 경사각 이온 주입법으로 질소를 주입한다. 이때의 경사각은 약 30°정도가 적당하고, 이온주입 에너지는 50~60KeV정도가 적당하다.Next, as shown in FIG. 4C, after the photoresist mask 407 is formed over the transistor of the memory cell unit, nitrogen is implanted into the gate insulating layer 401 under the sidewall spacer of the transistor of the peripheral circuit unit by the inclination angle ion implantation method. At this time, the inclination angle is about 30 °, and the ion implantation energy is about 50 to 60 KeV.

다음으로 도4d와 같이, 상기 포토레지스트 마스크(407)를 제거한 후 상기 사이드월 스페이서(405)를 마스크로하여, 상기 반도체 기판(400)내에 고농도의 불순물을 주입하여 상기 얕은 불순물층(404) 보다 깊은 불순물층(406)을 형성한다. 상기 깊은 불순물층(406)은 트랜지스터의 소스/드레인으로 동작한다.Next, as shown in FIG. 4D, after the photoresist mask 407 is removed, a high concentration of impurities are injected into the semiconductor substrate 400 using the sidewall spacer 405 as a mask, and then the shallow impurity layer 404 is removed. A deep impurity layer 406 is formed. The deep impurity layer 406 acts as a source / drain of the transistor.

한편, 본발명의 다른 실시례에 따른 반도체 소자의 제조방법은 다음과 같다.Meanwhile, a method of manufacturing a semiconductor device according to another embodiment of the present invention is as follows.

도5a 내지 도5d에서 좌측은 메모리셀부의 트랜지스터의 제조공정순서이고, 우측은 주변회로부의 트랜지스터의 제조공정 순서이다.5A to 5D, the left side shows the manufacturing process sequence of the transistor of the memory cell portion, and the right side shows the manufacturing process sequence of the transistor of the peripheral circuit portion.

먼저, 도5a와 같이, 반도체 기판(500)위에 소자간 분리영역을 형성한다. 다음으로 상기 반도체 기판(500) 전면에 게이트 절연막으로서 실리콘 산화막(SiO2)(501)을 형성한다. 다음으로, 상기 실리콘 산화막(501)위에 폴리실리콘층과 절연막을 형성한 다음 패터닝하여 메모리셀부, 주변회로부 모두 트랜지스터의 게이트 전극(502) 및 게이트 전극(502)상면을 보호하는 절연막 패턴(503)을 각각 형성한다.First, as shown in FIG. 5A, an isolation region between elements is formed on the semiconductor substrate 500. Next, a silicon oxide film (SiO 2 ) 501 is formed over the semiconductor substrate 500 as a gate insulating film. Next, a polysilicon layer and an insulating film are formed on the silicon oxide film 501 and then patterned to form an insulating film pattern 503 that protects the gate electrode 502 and the gate electrode 502 top surface of the transistor in both the memory cell part and the peripheral circuit part. Form each.

다음으로, 도5b와 같이, 상기 메모리 셀부에 상응하는 반도체 기판상에 포토레지스트 마스크(507)를 형성하고, 주변회로부의 게이트 절연막(실리콘 산화막)에 질소이온을 경사각 이온주입 또는 일반적인 이온 주입법으로 주입한다. 이때의 이온주입 에너지는 10~20KeV정도의 약한 에너지가 좋다.Next, as shown in FIG. 5B, a photoresist mask 507 is formed on the semiconductor substrate corresponding to the memory cell portion, and nitrogen ions are implanted into the gate insulating film (silicon oxide film) of the peripheral circuit portion by an inclination angle ion implantation or a general ion implantation method. do. At this time, the ion implantation energy is about 10 ~ 20 KeV weak energy is good.

다음으로, 도5c와 같이, 상기 포토레지스트 마스크(507)를 제거한 후, 상기 절연막 패턴(503)을 마스크로하여 상기 메모리셀부 및 주변회로부의 반도체 기판(500)내에저농도의 불순물 이온을 주입하여 상대적으로 얕은 불순물층(LDD; lightly doped region이라고도 함)(504)을 형성한다.Next, as shown in FIG. 5C, after the photoresist mask 507 is removed, a low concentration of impurity ions are implanted into the semiconductor substrate 500 of the memory cell unit and the peripheral circuit unit using the insulating layer pattern 503 as a mask. As a result, a shallow impurity layer (also referred to as a lightly doped region) 504 is formed.

다음으로, 도5d에 도시한 구조의 전면에 절연막으로서 실리콘 산화막 또는 실리콘 질화막을 형성한 후 이방성 에칭을 실시하여 게이트전극(502)의 측벽에 사이드월 스페이서(505)를 형성한다. 다음으로, 상기 사이드월 스페이서(505)를 마스크로하여, 상기 반도체 기판(500)내에 고농도의 불순물을 주입하여 상기 얕은 불순물층(504) 보다 깊은 불순물층(506)을 형성한다. 상기 깊은 불순물층(506)은 트랜지스터의 소스/드레인으로 동작한다.Next, a silicon oxide film or a silicon nitride film is formed as an insulating film on the entire surface of the structure shown in FIG. 5D and then anisotropically etched to form sidewall spacers 505 on the sidewalls of the gate electrode 502. Next, using the sidewall spacer 505 as a mask, a high concentration of impurities are implanted into the semiconductor substrate 500 to form an impurity layer 506 deeper than the shallow impurity layer 504. The deep impurity layer 506 acts as a source / drain of the transistor.

종래 핫캐리어 내성을 개선하기 위해 게이트 절연막으로서 NO막을 형성한 후, NO막위에 게이트전극을 형성하였으나, 그러한 공정에 의하면 p-채널 트랜지스터의 홀 이동도를 감소시켜 p-채널 트랜지스터 전기적인 특성이 저하되는 문제가 있었다. 그러나 본발명에 따르면, 사이드월 스페이서 아래에만 게이트 절연막으로서 질소를 포함하는 산화막을 형성하고, 게이트전극의 아래의 게이트 절연막으로서는 실리콘 산화막을 형성하도록 하여, 핫 캐리어 내성을 개선하고 동시에 p-채널 트랜지스터의 동작 특성 저하를 방지하여 반도체 소자의 신뢰성을 향상시키는 효과가 있다.Conventionally, a gate electrode was formed on the NO film after the NO film was formed as a gate insulating film to improve the hot carrier resistance. However, such a process reduces the hole mobility of the p-channel transistor, thereby reducing the p-channel transistor electrical characteristics. There was a problem. However, according to the present invention, an oxide film containing nitrogen as a gate insulating film is formed only under the sidewall spacer, and a silicon oxide film is formed as a gate insulating film under the gate electrode, thereby improving hot carrier resistance and simultaneously There is an effect of preventing the deterioration of the operating characteristics to improve the reliability of the semiconductor device.

또한, 반도체 메모리 소자의 제조에 있어서 종래 메모리 셀부와 주변회로부의 게이트 절연막을 각각 실리콘 산화막과 NO막으로 다르게 형성하기 위해서는, 먼저 주변회로부에 포토레지스트 마스크를 형성한 후, 먼저 메모리 셀부의 게이트 절연막인 실리콘 산화막을 형성하고, 다시 상기 실리콘 산화막에 포로레지스트 마스크를 형성한 후, 주변회로부의 게이트 절연막인 NO막을 형성하므로, 게이트 절연막을 형성하기 위해 2회의 포토리소그라피 공정이 요구되므로 공정이 번잡하고, 그에 따른 세정공정등에 의해 게이트절연막이 손상되는 등의 문제가 있었다. 그러나 본발명에 따르면, 그러한 번잡함 없이, 메모리셀부와 주변회로부의 구분없이 게이트 절연막으로서 실리콘 산화막을 형성하고, 후속공정에서 필요에 따라 국부적으로 질소이온을 주입하는 방법을 적용하기 때문에 공정이 용이해지는 효과가 있다.In the manufacture of a semiconductor memory device, in order to form a gate insulating film of a conventional memory cell portion and a peripheral circuit portion differently from a silicon oxide film and a NO film, first, a photoresist mask is formed on the peripheral circuit portion, and then a gate insulating film of the memory cell portion is first used. Since a silicon oxide film is formed, a photoresist mask is formed on the silicon oxide film, and a NO film, which is a gate insulating film of a peripheral circuit portion, is formed, so that two photolithography processes are required to form a gate insulating film, the process is complicated. There is a problem that the gate insulating film is damaged by the cleaning process. However, according to the present invention, the process becomes easy because the silicon oxide film is formed as the gate insulating film without the complexity and the memory cell portion and the peripheral circuit portion are separated, and in the subsequent step, a method of locally injecting nitrogen ions as necessary is applied. There is.

Claims (8)

반도체 기판상에 실리콘 산화막으로 게이트절연막을 형성하고, 상기 게이트 절연막 위에 게이트 전극을 형성하는 공정과,Forming a gate insulating film on the semiconductor substrate with a silicon oxide film, and forming a gate electrode on the gate insulating film; 상기 게이트전극 양측 반도체 기판내에 저농도의 불순물 이온을 주입하는 공정과,Implanting a low concentration of impurity ions into the semiconductor substrate on both sides of the gate electrode; 상기 게이트전극 양측벽에 사이드월 스페이서를 형성하는 공정과,Forming sidewall spacers on both sidewalls of the gate electrode; 상기 사이드월 스페이서 아래의 게이트절연막내에 질소이온을 경사각 이온주입하는 공정과;Tilting ion implantation of nitrogen ions into the gate insulating film under the sidewall spacer; 상기 사이드월 스페이서를 마스크로하여 상기 반도체 기판내에 고농도의 불순물 이온을 주입하여 소스/드레인을 형성하는 공정을 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 제조방법.And implanting a high concentration of impurity ions into the semiconductor substrate using the sidewall spacers as a mask to form a source / drain. 삭제delete 제1항에 있어서, 상기 질소를 이온주입하는 공정은, 이온주입 에너지 10~20KeV의 조건에서 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the ion implantation of nitrogen is performed under conditions of 10 to 20 KeV ion implantation energy. 삭제delete 삭제delete 삭제delete 메모리셀부와 주변회로부로 구성된 반도체 기판 전면에 실리콘 산화막으로 게이트 절연막을 형성하는 공정과,Forming a gate insulating film with a silicon oxide film on the entire surface of the semiconductor substrate including the memory cell portion and the peripheral circuit portion; 상기 반도체 기판상의 메모리셀부와 상기 주변회로부의 게이트절연막 상면에 각각 게이트 전극을 형성하는 공정과,Forming a gate electrode on an upper surface of the gate insulating film of the memory cell portion and the peripheral circuit portion on the semiconductor substrate; 상기 각 게이트 전극 양측 반도체 기판내에 저농도의 불순물 이온을 주입하여 얕은 불순물층들을 형성하는 공정과,Implanting low concentration of impurity ions into the semiconductor substrate on both sides of the gate electrode to form shallow impurity layers; 상기 각 게이트 전극의 양측에 각각 사이드월 스페이서들을 형성하는 공정과,Forming sidewall spacers on both sides of each of the gate electrodes; 상기 메모리셀부에 상응하는 반도체 기판상의 전체구조위에 포토레지스트 마스크를 형성하는 공정과,Forming a photoresist mask on the entire structure on the semiconductor substrate corresponding to the memory cell portion; 상기 주변회로부의 사이드월 스페이서하의 게이트절연막에 질소이온을 경사각 이온 주입하는 공정과,Injecting nitrogen ions into the gate insulating film under the sidewall spacers of the peripheral circuit portion; 상기 포토레지스트 마스크를 제거하는 공정과,Removing the photoresist mask; 상기 사이드월 스페이서 바깥측의 반도체 기판내에 고농도의 불순물을 주입하여 상기 얕은 불순물층보다 상대적으로 깊은 불순물층을 형성하는 공정을 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 제조방법.And implanting a high concentration of impurities into the semiconductor substrate outside the sidewall spacer to form an impurity layer relatively deeper than the shallow impurity layer. 삭제delete
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