KR100349348B1 - Method of etching a silicon layer - Google Patents
Method of etching a silicon layer Download PDFInfo
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- KR100349348B1 KR100349348B1 KR1020000047458A KR20000047458A KR100349348B1 KR 100349348 B1 KR100349348 B1 KR 100349348B1 KR 1020000047458 A KR1020000047458 A KR 1020000047458A KR 20000047458 A KR20000047458 A KR 20000047458A KR 100349348 B1 KR100349348 B1 KR 100349348B1
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- 238000005530 etching Methods 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 18
- 239000010703 silicon Substances 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 60
- 229920005591 polysilicon Polymers 0.000 claims abstract description 60
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000012535 impurity Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000005468 ion implantation Methods 0.000 claims abstract description 17
- 238000000059 patterning Methods 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000002245 particle Substances 0.000 abstract description 28
- 238000001020 plasma etching Methods 0.000 abstract description 15
- 230000008569 process Effects 0.000 abstract description 8
- 230000008859 change Effects 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000027756 respiratory electron transport chain Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- Drying Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체장치의 실리콘층 식각방법에 관한 것으로, 특히, 반도체 CMOS 소자의 게이트형성용 플라즈마 식각공정중 폴리실리콘층의 도핑농도 변화에 따른 식각속도 차이를 이용하여 PMOS 소자의 외곽을 n형 불순물로 도핑시켜 플라즈마 식각을 진행하므로서 하전입자에 의한 게이트산화막과 기판의 손상을 방지하여 트랜지스터의 문턱전압, 포화전류 등을 개선하도록 한 반도체장치의 게이트 형성방법에 관한 것이다. 본 발명은 n형 웰과 p형 웰이 졍션을 이루고 상기 웰들의 경계면에 필드절연막이 형성되어 소자활성영역과 소자격리영역을 정의하는 반도체 기판상에 게이트절연막을 형성하는 제 1 단계와, 상기 게이트절연막상에 불순물이 도핑되지 않은 반도체층을 형성하는 제 2 단계와, 상기 소자활성영역의 상기 n형 웰상에 형성된 상기 반도체층을 덮는 제 1 이온주입마스크와 상기 제 1 이온주입마스크와 소정간격 이격되어 상기 필드절연막 상부의 상기 반도체층을 덮는 제 2 이온주입마스크를 형성하는 제 3 단계와, 상기 제 1, 제 2 이온주입마스크로 보호되지 않는 상기 반도체층을 n형 불순물로 도핑시키는 제 4 단계와, 상기 제 1, 제 2 이온주입마스크를 제거하는 제 5 단계와, 상기 반도체층상에 게이트패터닝용 식각마스크를 형성하는 제 6 단계와, 상기 식각마스크로 보호되지 않는 부위의 반도체층을 고밀도 플라즈마를 이용하여 패터닝하는 제 7 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon layer etching method of a semiconductor device. In particular, an n-type impurity is formed around an outside of a PMOS device by using a difference in etching rate according to a change in doping concentration of a polysilicon layer during a gate etching plasma forming process of a semiconductor CMOS device. The present invention relates to a method for forming a gate of a semiconductor device, which improves a threshold voltage, a saturation current, and the like of a transistor by preventing a gate oxide film and a substrate from being damaged by charged particles by performing plasma etching by doping. The present invention provides a first step of forming a gate insulating film on a semiconductor substrate defining a device active region and a device isolation region by forming a n-type well and a p-type well and forming a field insulating film at an interface between the wells. A second step of forming a semiconductor layer which is not doped with an impurity on the insulating film, and a first distance between the first ion implantation mask and the first ion implantation mask covering the semiconductor layer formed on the n-type well of the device active region; A third step of forming a second ion implantation mask covering the semiconductor layer on the field insulating layer, and a fourth step of doping the semiconductor layer not protected by the first and second ion implantation masks with n-type impurities. And a fifth step of removing the first and second ion implantation masks, a sixth step of forming a gate patterning etching mask on the semiconductor layer, and the etching mask. And a seventh step of patterning the semiconductor layer of the portion which is not protected by the scrub using a high density plasma.
Description
본 발명은 반도체장치의 실리콘층 식각방법에 관한 것으로, 특히, 반도체 CMOS 소자의 게이트형성용 플라즈마 식각공정중 폴리실리콘층의 도핑농도 변화에 따른 식각속도 차이를 이용하여 PMOS 소자의 외곽을 n형 불순물로 도핑시켜 플라즈마 식각을 진행하므로서 하전입자에 의한 게이트산화막과 기판의 손상을 방지하여 트랜지스터의 문턱전압, 포화전류 등을 개선하도록 한 반도체장치의 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon layer etching method of a semiconductor device. In particular, an n-type impurity is formed around an outside of a PMOS device by using a difference in etching rate according to a change in doping concentration of a polysilicon layer during a gate etching plasma forming process of a semiconductor CMOS device. The present invention relates to a method for forming a gate of a semiconductor device, which improves a threshold voltage, a saturation current, and the like of a transistor by preventing a gate oxide film and a substrate from being damaged by charged particles by performing plasma etching by doping.
반도체소자의 고집적화가 요구되고, 모스형 전계효과 트랜지스터(MOSFET)의 게이트선폭 축소기술은 이러한 고집적화에 가장 밀접하게 연관되어 있다. 게이트 미세패턴을 형성하기 위하여 식각속도를 높이고 로딩효과(loading effect)를 감소시키는 등의 많은 장점을 갖는 고밀도 플라즈마 식각장비를 사용한다.Higher integration of semiconductor devices is required, and the gate line width reduction technology of MOSFETs is most closely related to such high integration. In order to form the gate fine pattern, a high density plasma etching apparatus having many advantages, such as increasing an etching speed and reducing a loading effect, is used.
고밀도 플라즈마를 이용한 식각장비는 우수한 식각특성을 갖지만 최근 많은 연구가 진행중인 '차징손상(charging damage)'이라는 큰 단점을 동시에 갖고 있다.Etching equipment using high-density plasma has excellent etching characteristics, but at the same time, it has a big disadvantage of 'charging damage' which is being studied.
도 1은 플라즈마 식각시 플라즈마의 국부적인 불균일에 의하여 형성되는 전기장을 설명하기 위한 모식도이다.1 is a schematic diagram illustrating an electric field formed by local nonuniformity of plasma during plasma etching.
도 1을 참조하면, 플라즈마 식각장치내에 중성입자, 전자(-), 양이온(+)으로 이루어진 플라즈마(PLASMA)가 발생되어 있고, 이러한 플라즈마에 전계가 형성되어 하부에 위치한 실리콘기판(SUB)표면으로 플라즈마 입자들이 충돌하여 식각이 진행된다.Referring to FIG. 1, a plasma (PLASMA) consisting of neutral particles, electrons (−), and cations (+) is generated in a plasma etching apparatus, and an electric field is formed in the plasma to the surface of a silicon substrate (SUB) located below. Plasma particles collide to etch.
플라즈마 식각에 의하여 발생되는 프라즈마 손상의 원인은 다음과 같다.The causes of plasma damage caused by plasma etching are as follows.
플라즈마를 구성하는 전자와 이온을 비롯한 하전입자의 밀도가 높고, 식각장비내 플라즈마의 균일도가 낮을 경우, 하전입자의 분포가 불균일 하게 되어 국부적으로 전자밀도가 높은 영역(B)과 이온밀도가 높은 영역(A)으로 미세하게 나누어져, 결국 반도체 소자가 형성되는 실리콘 기판에는 국지적으로 전자와 이온간의 하전입자가 서로 균형을 이루지 못하고 어느 한쪽에서 상대적으로 한 종류의 하전입자가 우세한 상태를 초래하게 된다.When the density of charged particles including electrons and ions constituting the plasma is high and the plasma uniformity in the etching equipment is low, the distribution of charged particles becomes uneven, so that the region of high electron density (B) and the region of high ion density are localized. Finely divided into (A), the silicon substrate on which the semiconductor element is formed eventually causes the charged particles between electrons and ions to not be balanced with each other, resulting in a state in which one type of charged particles is predominant on either side.
이와 같이, 불균일하게 분포된 하전입자에 의하여 실리콘기판에는 국부적으로 전기장(EF)이 형성되고, 이러한 전기장(EF)은 하전입자중 가벼운 종류 즉, 전자가 얇은 게이트산화막을 F-N 터널링으로 통과하여 기판쪽으로 유입된다.In this way, the electric field (EF) is locally formed on the silicon substrate by the unevenly distributed charged particles, and the electric field (EF) is a light kind of charged particles, that is, electrons pass through the gate oxide film through FN tunneling and toward the substrate. Inflow.
도 2a 내지 도 2b는 플라즈마를 이용한 폴리실리콘층 식각시 하전입자가 기판으로 흐르는 상태를 설명하기 위한 식각공정 단면도로서, 도 1에서 설명한 이온밀도가 높은 영역(A)에서의 플라즈마 식각상태를 도시한 것이다.2A to 2B are cross-sectional views of an etching process for explaining a state in which charged particles flow to a substrate when the polysilicon layer is etched using plasma, and shows a plasma etching state in a region A having a high ion density described with reference to FIG. 1. will be.
도 2a를 참조하면, 필드산화막(21)으로 소자격리영역과 소자활성영역이 정의된 실리콘 기판(20)상에 게이트산화막(22)을 개재한 폴리실리콘층(23)이 형성되어 있고, 폴리실리콘층(23)상에는 게이트패터닝용 식각마스크(24)로 포토레지스트패턴(24)이 형성되어 있다.Referring to FIG. 2A, a polysilicon layer 23 is formed on the silicon substrate 20 in which the device isolation region and the device active region are defined as the field oxide layer 21, and the polysilicon layer 23 is interposed therebetween. A photoresist pattern 24 is formed on the layer 23 as an etching mask 24 for gate patterning.
식각마스크(24)로 보호되지 않는 부위의 폴리실리콘층(23)을 플라즈마 식각으로 패터닝하여 폴리실리콘층(23)의 일부가 제거되는 식각초기에서 식각중기에 해당하는 단계가 도시되어 있다.A step corresponding to the etching phase in the initial etching stage in which a portion of the polysilicon layer 23 is removed by patterning the polysilicon layer 23 in a portion not protected by the etching mask 24 is shown.
도핑된 폴리실리콘과 같이 도체에 가까운 도전성을 가진 층이 식각될 때는 도시된 바와 같이 하전입자들의 균형이 유지되어 게이트산화막이나 기판에 손상을 입히지 않는다.When the conductive layer close to the conductor, such as doped polysilicon, is etched, the charged particles are balanced as shown, so as not to damage the gate oxide film or the substrate.
도 2b를 참조하면, 식각단계가 식각중기에서 식각종료점(end point)에 이르게 되면, 식각마스크(24)로 보호되지 않는 잔류한 폴리실리콘층(230)의 두께가 아주 얇아져서 높은 이온밀도에 의하여 전자들이 게이트산화막(22)을 통과하여 기판(20)으로 유입된다.Referring to FIG. 2B, when the etching step reaches the end point of etching in the etching center, the thickness of the remaining polysilicon layer 230 which is not protected by the etching mask 24 becomes very thin, and thus, due to high ion density. Electrons pass through the gate oxide layer 22 and flow into the substrate 20.
도 2c를 참조하면, 식각종료점을 지나 기판의 표면이 완전히 노출되도록 과도식각을 실시한 후의 단면도이다. 결국, 도 2b 단계부터 차징 손상이 발생하여 게이트산화막(22)과 기판(20)이 손상되어 트랜지스터 문턱전압이나 포화전류가 저하된다.Referring to FIG. 2C, a cross-sectional view of the substrate after the excessive etching is performed so that the surface of the substrate is completely exposed after the etching end point. As a result, charging damage occurs in step 2b, which damages the gate oxide film 22 and the substrate 20, thereby lowering the transistor threshold voltage and saturation current.
도 3은 실리콘 기판과 게이트산화막 계면에서의 전자이동을 설명하기 위한 배리어 에너지 밴드 다이아그램으로, 도 2b 단계에서 형성된 전기장에 대한 것이다.FIG. 3 is a barrier energy band diagram for explaining electron transfer at a silicon substrate and a gate oxide film interface, and illustrates an electric field formed in FIG. 2B.
도 3을 참조하면, 폴리실리콘으로 이루어진 게이트(PS)에 집중된 하전입자는 게이트산화막(SOX)을 사이에 두고 실리콘기판(SUB)과 전기장을 형성하게 되고, 이러한 전기장의 크기가 증가하게 되면, 전자(-)가 게이트산화막(SOX)을 통과할 수 있는 구동력을 얻게되어 시리콘기판(SUB으로 기속되어 유입된다. 이때, 게이트산화막(SOX)에 유기된 전기장에 의해 가속된 전자가 기판과 충돌하여 '전자(-)-정공(hole)' 쌍을 생성하게 되고, '전자-정공'쌍은 게이트산화막(SOX)에 갇혀(trap) 트랩의 에너지 준위를 게이트산화막의 금지에너지대(forbidden energy gap)내에 위치하도록 변화시켜, 결국 트랜지스터 특성중 가장 중요한 요소들인 문턱전압(threshold voltage), 포화전류(IDSAT) 등의 특성을 열화시킨다.Referring to FIG. 3, the charged particles concentrated on the gate PS made of polysilicon form an electric field with the silicon substrate SUB with the gate oxide film SOX interposed therebetween. (-) Gains driving force to pass through the gate oxide film SOX and flows into the silicon substrate SUB, where electrons accelerated by the electric field induced in the gate oxide film SOX collide with the substrate. 'Electron-hole' pairs are generated, and the 'electron-hole' pairs are trapped in the gate oxide film (SOX) to trap the energy level of the trap and the forbidden energy gap of the gate oxide film. In the end, the characteristics of the transistors, such as the threshold voltage and the saturation current ID SAT , are degraded.
도 4는 종래 기술에 따른 CMOS 제작을 위한 듀알게이트 형성용 폴리실리콘층 식각중 식각종료점 부근에서 하전입자의 흐름으로 PMOS소자가 손상받는 상태를 도시하는 단면도이다.FIG. 4 is a cross-sectional view illustrating a state in which a PMOS device is damaged by a flow of charged particles near an etch end point during etching of a dual gate forming polysilicon layer for manufacturing a CMOS according to the related art.
도 4를 참조하면, n형 웰(41)과 p형 웰(42)이 졍션을 이루며 형성되고, 필드산화막(46)으로 소자격리영역과 소자활성영역이 정의된 실리콘 기판(40)상에게이트산화막(430,431)을 개재한 폴리실리콘층이 p형 게이트 및 n형 게이트 패터닝용 식각마스크(45)로 포토레지스트패턴(45)이 형성되어 있다.Referring to FIG. 4, an n-type well 41 and a p-type well 42 are formed in a caption, and a gate is formed on the silicon substrate 40 in which the device isolation region and the device active region are defined by the field oxide layer 46. The photoresist pattern 45 is formed of a polysilicon layer via the oxide films 430 and 431 as an etch mask 45 for p-type gate and n-type gate patterning.
식각마스크(45)로 보호되지 않는 부위의 폴리실리콘층을 플라즈마 식각으로 패터닝하여 폴리실리콘층의 일부가 제거되는 식각초기에서 식각중기에 해당하는 단계가 도시되어 있다. 이때, p형 웰(52)에 형성된 폴리실리콘층은 n형 불순물로 도핑되고, n형 웰(41)에 형성된 폴리실리콘층은 p형 불순물로 도핑되어 있다.The steps corresponding to the etching phase in the initial etching stage in which a portion of the polysilicon layer is removed by patterning the polysilicon layer of the portion not protected by the etching mask 45 by plasma etching are illustrated. At this time, the polysilicon layer formed in the p-type well 52 is doped with n-type impurities, and the polysilicon layer formed in the n-type well 41 is doped with p-type impurities.
도핑된 폴리실리콘은 그 식각특성상 도핑된 불순물에 따라 각각 식각속도가 다르게 나타난다. 일반적으로, n형으로 도핑된 폴리실리콘층의 식각속도가 p형으로 도핑된 폴리실리콘보다 빠르게 된다.The doped polysilicon exhibits different etching rates depending on the doped impurities due to its etching characteristics. In general, the etching rate of the n-type doped polysilicon layer is faster than the p-type doped polysilicon.
식각단계가 식각중기에서 식각종료점(end point)에 이르게 되면, n형 웰(41) 영역에서 식각마스크(45)로 보호되지 않는 잔류한 폴리실리콘층(440)의 두께가 아주 얇아져서 높은 이온밀도에 의하여 전자들이 게이트산화막(430)을 통과하여 웰(41)로 유입된다. 또한, 잔류한 폴리실리콘층(440)은 필드산화막(46)상에도 잔류하여 상기에서 설명한 바와 같이 기판과 실리콘사이의 전기장세기를 강화시킨다.When the etching step reaches the end point of etching in the etching center, the thickness of the remaining polysilicon layer 440 which is not protected by the etching mask 45 in the n-type well 41 region becomes very thin and thus high ion density. As a result, electrons pass through the gate oxide layer 430 and flow into the well 41. In addition, the remaining polysilicon layer 440 remains on the field oxide layer 46 to enhance the electric field strength between the substrate and the silicon as described above.
그러나, 동일한 단계에서 p형 웰(42) 영역에서는 식각이 빠르게 진행되어 각가의 패턴이 분리되어 게이트 패턴(441) 형성이 완료되고 게이트산화막(431) 표면이 노출된다.However, in the same step, the etching proceeds rapidly in the p-type well 42 region to separate the respective patterns, thereby completing the formation of the gate pattern 441, and exposing the surface of the gate oxide layer 431.
즉, 플라즈마 식각으로 듀얼 게이트를 적용할 경우, n형 불순물로 도핑된 n형 웰영역인 NMOS영역의 식각속도가 PMOS영역의 식각속도 보다 약 15-20% 정도 빠르게 진행되어 NMOS영역은 폴리실리콘이 식각되어 게이트산화막의 표면이 드러나고, PMOS영역은 폴리실리콘층이 식각속도 차이만큼 잔류하여 식각종료점 가까이에서 하전입자는 거의 PMOS영역으로 집중되어 이지역의 전기장을 국부적으로 강화하게 된다.In other words, when the dual gate is applied by plasma etching, the etching rate of the NMOS region, which is an n-type well region doped with n-type impurities, is about 15-20% faster than the etching rate of the PMOS region. Etching reveals the surface of the gate oxide film, and in the PMOS region, the polysilicon layer remains as much as the etching rate difference, and near the etch termination point, charged particles are almost concentrated in the PMOS region, thereby locally strengthening the electric field in this region.
따라서, 상술한 종래 기술은 플라즈마 식각시 차징 손상이 발생하여 게이트산화막과 기판이 손상되어 트랜지스터 문턱전압이나 포화전류를 열화시키는 문제점이 있다.Accordingly, the above-described conventional technology has a problem in that charging damage occurs during plasma etching, resulting in damage to the gate oxide layer and the substrate, thereby degrading the transistor threshold voltage or saturation current.
따라서, 본 발명의 목적은 반도체 CMOS 소자의 게이트형성용 플라즈마 식각공정중 폴리실리콘층의 도핑농도 변화에 따른 식각속도 차이를 이용하여 PMOS 소자의 외곽을 n형 불순물로 도핑시켜 플라즈마 식각을 진행하므로서 하전입자에 의한 게이트산화막과 기판의 손상을 방지하여 트랜지스터의 문턱전압, 포화전류 등을 개선하도록 한 반도체장치의 듀알 게이트 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to perform plasma etching by doping the outside of the PMOS device with n-type impurities using the etching rate difference according to the doping concentration change of the polysilicon layer during the gate etching plasma etching process of the semiconductor CMOS device. The present invention provides a method of forming a dual gate of a semiconductor device, which prevents damage to a gate oxide film and a substrate by all particles, thereby improving a threshold voltage, a saturation current, and the like of a transistor.
상기 목적들을 달성하기 위하여 본 발명은 n형 웰과 p형 웰이 졍션을 이루고 상기 웰들의 경계면에 필드절연막이 형성되어 소자활성영역과 소자격리영역을 정의하는 반도체 기판상에 게이트절연막을 형성하는 제 1 단계와, 상기 게이트절연막상에 불순물이 도핑되지 않은 반도체층을 형성하는 제 2 단계와, 상기 소자활성영역의 상기 n형 웰상에 형성된 상기 반도체층을 덮는 제 1 이온주입마스크와 상기 제 1 이온주입마스크와 소정간격 이격되어 상기 필드절연막 상부의 상기 반도체층을 덮는 제 2 이온주입마스크를 형성하는 제 3 단계와, 상기 제 1, 제 2 이온주입마스크로 보호되지 않는 상기 반도체층을 n형 불순물로 도핑시키는 제 4 단계와, 상기 제 1, 제 2 이온주입마스크를 제거하는 제 5 단계와, 상기 반도체층상에 게이트패터닝용식각마스크를 형성하는 제 6 단계와, 상기 식각마스크로 보호되지 않는 부위의 반도체층을 고밀도 플라즈마를 이용하여 패터닝하는 제 7 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method for forming a gate insulating film on a semiconductor substrate which defines a device active region and a device isolation region by forming a n-type well and a p-type well and forming a field insulating film at an interface between the wells. A first step of forming a semiconductor layer which is not doped with impurities on the gate insulating film, a first ion implantation mask covering the semiconductor layer formed on the n-type well of the device active region, and the first ion A third step of forming a second ion implantation mask spaced apart from an implantation mask and covering the semiconductor layer on the field insulating layer, and n-type impurities in the semiconductor layer not protected by the first and second ion implantation masks; Forming a etching mask for gate patterning on the semiconductor layer; A sixth step, a semiconductor layer that is not protected by the etch mask portion that comprises a seventh step of patterning using high-density plasma.
도 1은 플라즈마 식각시 플라즈마의 국부적인 불균일에 의하여 형성되는 전기장을 설명하기 위한 모식도1 is a schematic diagram illustrating an electric field formed by local nonuniformity of plasma during plasma etching.
도 2a 내지 도 2b는 플라즈마를 이용한 폴리실리콘층 식각시 하전입자가 기판으로 흐르는 상태를 설명하기 위한 식각공정 단면도2A to 2B are etch process cross-sectional views for explaining a state in which charged particles flow to a substrate when etching a polysilicon layer using plasma;
도 3은 실리콘 기판과 게이트산화막 계면에서의 전자이동을 설명하기 위한 배리어 에너지 밴드 다이아그램3 is a barrier energy band diagram for explaining electron transfer at the silicon substrate and the gate oxide film interface.
도 4는 종래 기술에 따른 폴리실리콘층 식각중 식각종료점 부근에서 하전입자의 흐름으로 PMOS소자가 손상받는 상태를 도시하는 단면도4 is a cross-sectional view showing a state in which a PMOS device is damaged by the flow of charged particles in the vicinity of an etching end point during polysilicon layer etching according to the prior art;
도 5a 내지 도 5c는 본 발명에 따른 폴리실리콘층 식각방법을 도시하는 공정 단면도5A to 5C are cross-sectional views illustrating a polysilicon layer etching method according to the present invention.
본 발명은 CMOS 소자제조에 있어서, NMOS소자 형성시 n형 게이트 형성영역과 PMOS 형성영역의 p형 게이트 주변부를 노출시키는 이온주입마스크를 폴리실리콘층상에 형성한 다음, n형 불순물로 이온주입을 실시한 후 어닐링을 실시하여 불순물들을 충분히 확산시킨 후, 후속공정으로 플라즈마 식각을 폴리실리콘층에 식각하여 상대적으로 식각속도가 늦은 PMOS 형성영역의 폴리실리콘층을 타영역과 겨리시키므로서, 식각종료점 시점에서 PMOS 영역으로 유입되는 하전입자량을 현격히 감소시킨다.According to the present invention, in the fabrication of a CMOS device, an ion implantation mask is formed on a polysilicon layer to expose an n-type gate formation region and a p-type gate periphery of a PMOS formation region when an NMOS device is formed, and then ion implantation is performed with n-type impurities. After annealing is performed to diffuse the impurities sufficiently, the plasma etching is etched to the polysilicon layer in a subsequent process, so that the polysilicon layer of the PMOS forming region having a relatively low etching rate is separated from the other regions, and thus the PMOS at the end point of etching Significantly reduce the amount of charged particles entering the area.
즉, 고밀도 플라즈마를 사용하는 건식식각은 미세패턴 형성을 위하여 여러 가지 장점을 갖고있지만, 하전입자의 밀도가 매우 높아서 '차징손상'이라는 치명적인 단점을 가지고 있다.That is, dry etching using a high density plasma has various advantages for forming a fine pattern, but has a fatal disadvantage of 'charging damage' because the density of charged particles is very high.
특히, 도체에 가까운 도전성을 갖는 폴리실리콘을 식각할 경우, 식각 초기에서 중기까지는 하전입자들이 웨이퍼에 균일하게 분포되어 문제가 없지만, 식각이 계속 진행되어 식각종료점 가까이 오면 하전입자들은 움직일 곳이 감소하여 결국 패터닝되는 잔류한 폴리실리콘으로 이루어진 게이트패턴으로 집중되어 게이트산화막에 포텐샬을 형성하게 되고, 특히 가벼운 하전입자인 전자가 게이트산화막을 통과하여 손상을 초래하게 된다. 이러한 손상을 '차징손상'이라 하며 트랜지스터 특성인 문턱전압과 포화전류 등을 저하시키게 된다.In particular, when etching polysilicon having conductivity close to the conductor, the charged particles are uniformly distributed on the wafer from the initial etching period to the middle phase, but there is no problem when the etching continues and the charged particles move closer to the end point of etching. Eventually, it is concentrated to the gate pattern made of the remaining polysilicon patterned to form a potential in the gate oxide film. In particular, electrons, which are lightly charged particles, pass through the gate oxide film and cause damage. Such damage is called 'charging damage' and reduces the transistor characteristics such as threshold voltage and saturation current.
그러나, n형 불순물로 도핑된 폴리실리콘영역은 p형 불순물로 도핑된 영역보다 식각속도가 빠르다는 사실을 이용하는 본 발명에 따른 방법으로 폴리실리콘층을 식각하게 되면, 하전입자들이 식각종료점 부근에서 소정영역상(본 발명의 실시예에서는 필드산화막상)에 고립되어 PMOS 형성용 폴리실리콘영역으로 하전입자들이 이동하는 것을 원천적으로 봉쇄하여 전기장형성을 방지하므로 게이트산화막의 손상을 방지한다.However, when the polysilicon layer is etched by the method according to the present invention utilizing the fact that the polysilicon region doped with the n-type impurity has a faster etching rate than the region doped with the p-type impurity, the charged particles are placed near the end point of etching. It is isolated on the region (in the field oxide layer in the embodiment of the present invention) to block the movement of the charged particles to the polysilicon region for PMOS formation, thereby preventing the formation of the electric field, thereby preventing damage to the gate oxide layer.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 5a 내지 도 5c는 고밀도 플라즈마를 사용하는 본 발명에 따른 폴리실리콘층 식각방법을 도시하는 공정 단면도이다.5A to 5C are cross-sectional views illustrating a polysilicon layer etching method according to the present invention using a high density plasma.
도 5a를 참조하면, n형 웰(51)과 p형 웰(52)이 졍션을 이루며 형성되고, 필드산화막(53)으로 소자격리영역과 소자활성영역이 정의된 실리콘 기판(50)상에 게이트산화막(540,541)을 개재한 폴리실리콘층(55)을 화학기상증착으로 형성한다. 이때, 폴리실리콘층은 불순물이 도핑되지 않은 것을 사용한다.Referring to FIG. 5A, an n-type well 51 and a p-type well 52 are formed in a caption, and a gate is formed on a silicon substrate 50 in which an element isolation region and an element active region are defined by a field oxide film 53. The polysilicon layer 55 via the oxide films 540 and 541 is formed by chemical vapor deposition. In this case, the polysilicon layer is one that is not doped with impurities.
그리고, n형 웰(51) 상부의 폴리실리콘층(55)만을 선택적으로 p형 불순물로 도핑시키거나, 후속공정에서 p형 웰(52) 영역 상부 및 n형 웰(51) 영역 외곽에 위치한 폴리실리콘층(55)을 n형 불순물로 도핑시킨 다음 n형 웰(51) 상부의 폴리실리콘층(55)만을 선택적으로 p형 불순물로 도핑시킬 수 있다.Then, only the polysilicon layer 55 on the n-type well 51 is selectively doped with a p-type impurity, or in a subsequent process, a poly is located on the upper portion of the p-type well 52 region and outside the n-type well 51 region. After the silicon layer 55 is doped with n-type impurities, only the polysilicon layer 55 on the n-type well 51 may be selectively doped with p-type impurities.
그 다음, 폴리실리콘층(55)상에 포토레지스트를 도포한 후, 노광 및 현상을 실시하여 p형 웰(52) 상의 n형 게이트 형성영역 폴리실리콘층과 필드산화막(53)상에서 n형 웰(51)상의 p형 게이트형성영역을 소정의 폭을 가지며 둘러싸는 형태를 갖도록 포토레지스트패턴(560, 561)을 형성한다. 즉, n형 게이트 형성영역의 포토레지스트패턴(560)과 필드산화막(53)상의 포토레지스트패턴(561)은 서로 분리되어 폴리실리콘층(55)의 일부를 띠 형태로 노출시키는 트렌치(T)를 갖도록 형성된다.Then, after the photoresist is applied on the polysilicon layer 55, exposure and development are performed to form the n-type well (on the n-type gate formation region polysilicon layer on the p-type well 52 and the field oxide film 53). The photoresist patterns 560 and 561 are formed to have a predetermined width and surround the p-type gate formation region on 51. That is, the photoresist pattern 560 in the n-type gate formation region and the photoresist pattern 561 on the field oxide film 53 are separated from each other to expose the trench T for exposing a portion of the polysilicon layer 55 in a band form. It is formed to have.
그리고, 포토레지스트패턴(560,561)으로 보호되지 않는 폴리실리콘층(55)에 n형 불순물로 도핑된 게이트를 형성하기 위한 n형 불순물 이온주입을 실시한다.Then, n-type impurity ion implantation is performed to form a gate doped with n-type impurity in the polysilicon layer 55 which is not protected by the photoresist patterns 560 and 561.
도 5b를 참조하면, n형 불순물 이온주입용 포토레지스트패턴을 산소애슁(O2ashing)등의 방법으로 제거하여 n형 웰(51)영역 상부에 위치한 폴리실리콘층(55)에 형성된 제 1 n형 불순물 이온매몰층(570)과 p형 웰(52) 상부에 위치한 폴리실리콘층(55)에 형성된 제 2 n형 불순물 이온매몰층(571)을 갖는 폴리실리콘층(55)의 전 표면을 노출시킨다. 이때, 이온매몰층(570,571)에 어닐링을 실시하여 불순물 이온들을 충분히 확산시킬 수 있다.Referring to FIG. 5B, the n-type impurity ion implantation photoresist pattern is removed by a method such as oxygen ashing (O 2 ashing) to form a first n formed on the polysilicon layer 55 located above the n-type well 51 region. Expose the entire surface of the polysilicon layer 55 having the second impurity ion buried layer 570 and the second n-type impurity ion buried layer 571 formed on the polysilicon layer 55 located above the p-type well 52. Let's do it. At this time, annealing may be performed on the ion buried layers 570 and 571 to sufficiently diffuse the impurity ions.
그리고, 폴리실리콘층(55)상에 포토레지스트를 도포한 후 노광 및 현상을 실시하여 PMOS와 NMOS로 구성되는 CMOS 트랜지스터 소자의 게이트를 패터닝하기 위한 게이트형성용 식각마스크(58)인 포토레지스트패턴(58)을 형성한다.After the photoresist is coated on the polysilicon layer 55, the photoresist pattern, which is a gate forming etching mask 58 for patterning the gate of the CMOS transistor element composed of PMOS and NMOS, is exposed and developed. 58).
도 5c를 참조하면, 고밀도 플라즈마를 사용하는 건식식각장비에서 식각마스크(58)로 보호되지 않는 부위의 폴리실리콘층을 p형 웰(52) 영역의 게이트산화막(541) 표면이 노출될 때까지 식각하여 제거한다.Referring to FIG. 5C, in a dry etching apparatus using a high density plasma, the polysilicon layer of a portion not protected by the etching mask 58 is etched until the surface of the gate oxide layer 541 of the p-type well 52 region is exposed. To remove it.
이때, 도핑된 폴리실리콘은 그 식각특성상 도핑된 불순물에 따라 각각 식각속도가 다르게 나타난다. 일반적으로, n형으로 도핑된 폴리실리콘층의 식각속도가 p형으로도핑된 폴리실리콘보다 빠르게 된다.At this time, the etch rate of the doped polysilicon is different depending on the doped impurities due to its etching characteristics. In general, the etching rate of the n-type doped polysilicon layer is faster than the p-type doped polysilicon.
즉, 플라즈마 식각으로 듀얼 게이트를 적용할 경우, n형 불순물로 도핑된 n형 웰영역인 NMOS영역의 식각속도가 PMOS영역의 식각속도 보다 약 15-20% 정도 빠르게 진행되어 NMOS영역은 폴리실리콘이 식각되어 게이트산화막(541)의 표면이 드러나고, 이때 PMOS영역과 필드산화막(53)상에는 폴리실리콘층(550, 552)이 식각속도 차이만큼 잔류하지만 두 폴리실리콘층(550,552) 사이에 n형 불순물로 도핑된 지역이 완전히 제거되어 필드산화막(53)의 일부 표면을 노출시키므로, 두 폴리실리콘층(550,552)은 서로 격리된다. 따라서, 식각종료점 가까이에서 하전입자는 거의 PMOS영역으로 이동도지 못하고 필드산화막(53)상의 잔류한 폴리실리콘층(552)에 갇히게 된다.In other words, when the dual gate is applied by plasma etching, the etching rate of the NMOS region, which is an n-type well region doped with n-type impurities, is about 15-20% faster than the etching rate of the PMOS region. Etched to reveal the surface of the gate oxide film 541, at which time the polysilicon layers 550, 552 remain on the PMOS region and the field oxide film 53 by the difference in the etching rate, but as n-type impurities between the two polysilicon layers (550,552) Since the doped regions are completely removed to expose some surfaces of the field oxide film 53, the two polysilicon layers 550, 552 are isolated from each other. Thus, near the etching end point, the charged particles hardly move to the PMOS region and are trapped in the remaining polysilicon layer 552 on the field oxide film 53.
또한, p형 웰(52)상에는 잔류한 폴리실리콘층으로 이루어진 n형으로 도핑된 게이트(551)가 패터닝된다.In addition, an n-type doped gate 551 consisting of the remaining polysilicon layer is patterned on the p-type well 52.
이후, 도시되지는 않았지만, 식각을 진행하여 잔류한 폴리실리콘층으로 이루어진 p형 게이트 형성을 포함한는 후속공정을 실시하여 CMOS 소자제조를 완료한다.Subsequently, although not shown, etching is performed to perform a subsequent process including forming a p-type gate formed of the remaining polysilicon layer to complete the manufacturing of the CMOS device.
따라서, 본 발명에 의한 반도체장치의 실리콘층 식각방법은 n형 불순물로 도핑된 폴리실리콘영역은 p형 불순물로 도핑된 영역보다 식각속도가 빠르다는 사실을 이용하는 본 발명에 따른 방법으로 폴리실리콘층을 식각하게 되면, 하전입자들이 식각종료점 부근에서 소정영역상(본 발명의 실시예에서는 필드산화막상)에 고립되어 PMOS 형성용 폴리실리콘영역으로 하전입자들이 이동하는 것을 원천적으로 봉쇄하여전기장형성을 방지하므로 게이트산화막과 실리콘기판의 손상을 방지는 장점이 있다.Therefore, the silicon layer etching method of the semiconductor device according to the present invention uses the fact that the polysilicon region doped with n-type impurity has a faster etching rate than the region doped with p-type impurity. When etched, the charged particles are isolated on a predetermined region (in the field oxide layer in the embodiment of the present invention) near the end point of etching, thereby blocking the movement of the charged particles to the polysilicon region for forming PMOS, thereby preventing electric field formation. There is an advantage in preventing damage to the gate oxide film and the silicon substrate.
Claims (5)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH023226A (en) * | 1988-06-20 | 1990-01-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR960039379A (en) * | 1995-04-27 | 1996-11-25 | 김광호 | Semiconductor Memory Device Manufacturing Method |
| JP2000012528A (en) * | 1998-06-26 | 2000-01-14 | Sony Corp | Method for etching film covering stepped parts |
| JP2000021999A (en) * | 1998-07-07 | 2000-01-21 | Matsushita Electron Corp | Semiconductor device and its manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH023226A (en) * | 1988-06-20 | 1990-01-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR960039379A (en) * | 1995-04-27 | 1996-11-25 | 김광호 | Semiconductor Memory Device Manufacturing Method |
| JP2000012528A (en) * | 1998-06-26 | 2000-01-14 | Sony Corp | Method for etching film covering stepped parts |
| JP2000021999A (en) * | 1998-07-07 | 2000-01-21 | Matsushita Electron Corp | Semiconductor device and its manufacture |
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