KR100335137B1 - Device for detecting signal - Google Patents
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- KR100335137B1 KR100335137B1 KR1020000004916A KR20000004916A KR100335137B1 KR 100335137 B1 KR100335137 B1 KR 100335137B1 KR 1020000004916 A KR1020000004916 A KR 1020000004916A KR 20000004916 A KR20000004916 A KR 20000004916A KR 100335137 B1 KR100335137 B1 KR 100335137B1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
- G01R31/3277—Testing of circuit interrupters, switches or circuit-breakers of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
- G01R31/3278—Testing of circuit interrupters, switches or circuit-breakers of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches of relays, solenoids or reed switches
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/12—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using diode rectifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
본 발명은 결상 및 역상신호 검출 장치에 관한 것으로 특히 계전기에서 결상 및 역상을 검출하여 트립신호를 주어 기기들을 보호하기에 적당하도록 한 계전기의 결상 및 역상신호 검출 장치에 관한 것이다. 이와 같은 결상 및 역상신호 검출 장치는 R,S,T 3상의 변류기(CT)에서 출력되는 교류(AC)를 각각 직류로 정류하는 제 1, 제 2, 제 3 정류소자(D1,D2,D3)와, 상기 제 1, 제 2, 제 3 정류소자에서 각각 정류된 직류를 전압으로 변환하는 제 1, 제 2, 제 3 부담저항(R1,R2,R3)과, 상기 제 1, 제 2 및 제 3 부담저항에서 각각 출력되는 전압에 따라 O 또는 1의 논리 값을 출력하는 제 1, 제 2, 제 3 논리소자(U1,U2,U3)와, 상기 제 1, 제 2, 제 3 논리소자에서 각각 출력되는 논리 값에 따라 각각 제 1, 제 2 논리값을 출력하는 제 4, 제 5, 제 6 논리소자(11.12.13)와, 상기 제 4, 제 5, 제 6 논리소자의 제 1 논리값에 따라 상기 R,S,T 3상의 역상 신호를 출력하는 제 7 논리소자(14)와, 상기 제 4, 제 5, 제 6 논리소자의 제 2 논리값에 따라 제 3 논리값을 출력하는 제 8 논리소자(15)와, 상기 제 8 논리소자의 출력값에 따라 상기 R,S,T 3상의 결상 신호를 출력하는 제 9 논리소자로 구성된다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an apparatus for detecting phase and reverse phase signals, and more particularly, to an apparatus for detecting phase and reverse phase of relays, which detects phase and reverse phases in relays and provides trip signals to protect devices. Such an image forming and reverse phase detection device includes first, second, and third rectifying elements D1, D2, and D3 rectifying each of the alternating currents AC output from the three-phase current transformers CT in DC. First, second, and third burden resistors R1, R2, and R3 for converting direct current rectified by the first, second, and third rectifiers into voltage; and the first, second, and third In the first, second and third logic elements U1, U2 and U3 outputting logic values of O or 1 according to the voltages output from the three burden resistors, respectively, and in the first, second and third logic elements. Fourth, fifth, and sixth logic elements (11.12.13) for outputting first and second logic values, respectively, according to the output logic values, respectively, and first logic of the fourth, fifth, and sixth logic elements. A seventh logic element 14 for outputting the R, S, and T three-phase inverse signals according to a value; and a third logic value for outputting the third logic value according to second logic values of the fourth, fifth, and sixth logic elements. The eighth logic element 15 and the exit of the eighth logic element And a ninth logic element which outputs the imaging signals of the R, S, and T phases according to the output value.
Description
본 발명은 결상 및 역상신호 검출 장치에 관한 것으로 특히 계전기에서 결상 및 역상을 검출하여 트립신호를 주어 기기들을 보호하기에 적당하도록 한 계전기의 결상 및 역상신호 검출 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an apparatus for detecting phase and reverse phase signals, and more particularly, to an apparatus for detecting phase and reverse phase of relays, which detects phase and reverse phases in relays and provides trip signals to protect devices.
국내의 모터보호 계전기는 종래의 열동형, 유도형 계전기에서 반도체 소자를이용한 정지형 계전기들이 많이 사용되고 있다.In the domestic motor protection relay, stationary relays using semiconductor devices are widely used in conventional thermal and inductive relays.
이에 따라 종래에 열동형, 유도형 계전기에서 과부하만 보호하던 기술에서 역상, 결상 등의 기능을 갖는 디지털화된 계전기들이 출시되고 있다.Accordingly, digitized relays having functions such as reverse phase and phase open have been released in the conventional technology that only protects the overload in a thermal or inductive relay.
이하, 첨부된 도면을 참조하여 종래 전자식 배선용 차단기를 설명하기로 한다.Hereinafter, a conventional electronic circuit breaker will be described with reference to the accompanying drawings.
도 1은 종래 과전류 감지회로를 나타낸 회로도이다.1 is a circuit diagram illustrating a conventional overcurrent sensing circuit.
종래 과전류 감지회로는 수 개의 저항(R1,R2,R3,R4)으로 전압분배하여 비교기(OP5,OP6,OP7,OP8)에 기준전압이 인가되도록 하고, 변류기(CT1,CT2,CT3)의 출력신호를 비교기(OP4)에 의해 검출 증폭항 비교기(OP8)를 제어함으로서 앤드 게이트(G3,G4)를 반전시켜 트랜지스터(TR1)를 제어하여 트립신호를 발생시켜 릴레이(RY)를 동작시킨다.The conventional overcurrent sensing circuit divides the voltage by several resistors R1, R2, R3, and R4 so that a reference voltage is applied to the comparators OP5, OP6, OP7, and OP8, and output signals of the current transformers CT1, CT2, and CT3. By controlling the detection amplification term comparator OP8 by the comparator OP4, the AND gates G3 and G4 are inverted to control the transistor TR1 to generate a trip signal to operate the relay RY.
즉, 변류기(CT1,CT2,CT3)에서 전류를 인식하여 전압으로 변환하여 정류 및 증폭(OP1,OP2,OP3)하여 수개의 저항(R1,R2,R3,R4)으로 전압분배하고 비교기(OP5,OP6,OP7,OP8)에 기준전압이 인가되도록 되어 있어, 변류기(CT1,CT2,CT3)의 출력신호인 OP1,OP2,OP3의 출력이 비교기(OP4)에 의해 검출증폭하여 비교기(OP8)를 제어한다.That is, currents are recognized by current transformers CT1, CT2, and CT3, converted into voltages, rectified and amplified (OP1, OP2, and OP3), and voltage is divided among several resistors R1, R2, R3, and R4. The reference voltage is applied to the OP6, OP7, and OP8, and the outputs of the OP1, OP2, and OP3, which are output signals of the current transformers CT1, CT2, and CT3, are detected and amplified by the comparator OP4 to control the comparator OP8. do.
도 2a는 종래 역상 신호 검출회로를 나타낸 회로도이다.2A is a circuit diagram illustrating a conventional reverse phase signal detection circuit.
종래 역상검출회로는 배타적 오아 케이트(XOR1,XOR2,XOR3) 또는 낸드 게이트(G7,G8,G9) 및 저항(R8,R9,R10)의 분배전압에 의해 비교기(OR9)로 비교된 신호를 콘덴서(C1)와 저항(R11)으로된 미분회로에 의해 비교기(OP10)로 비교하여 앤드 게이트(G1)로 트랜지스터를 제어한다. 여기서, 역상이란 3상(R,S,T)의 상이 바뀐 경우이다.In the conventional reverse phase detection circuit, an exclusive orate (XOR1, XOR2, XOR3) or a NAND gate (G7, G8, G9) and a divider voltage of the resistors (R8, R9, R10) are compared to the signal of the comparator (OR9). The transistor is controlled by the AND gate G1 by comparing with the comparator OP10 by a differential circuit composed of C1) and a resistor R11. Here, the reverse phase is a case where the phases of the three phases (R, S, T) are changed.
도 2b는 종래 결상신호 검출 회로를 나타낸 회로도이다.2B is a circuit diagram illustrating a conventional phase open signal detection circuit.
종래 결상검출 회로는 트랜지스터(TR3,TR4,TR5)의 콜렉터에 분배저항으로 전압분배 앤드게이트(G4)의 입력단과 다이오드(D11,D12,D13)를 통해 앤드 게이트(G23)의 입력단에 연결되고, 앤드 게이트(G6)를 통해 출력한다. 여기서, 결상이란 3상중 1상이 연결이 끊긴 경우이다.The conventional phase detection circuit is connected to the input terminal of the gate (G23) through the input terminal of the voltage distribution AND gate (G4) and the diodes (D11, D12, D13) with a distribution resistor to the collectors of the transistors (TR3, TR4, TR5), It outputs through the AND gate G6. Here, the open phase is when one of the three phases is disconnected.
이와같은 도 1 및 도 2a, 도 2b에 나타낸 종래 과전류 감지회로와 역상 및 결상 검출회로는 국내특허출원번호 제89-8463호(1989년 6월 20일 출원)의 결상 및 역상신호 검출 릴레이 장치를 설명한 것이다.1 and 2A and 2B, the conventional overcurrent detection circuit and the reverse phase and phase detection circuit include a phase and reverse phase detection relay device of Korean Patent Application No. 89-8463 (filed June 20, 1989). It is explained.
이와 같은 종래 결상 및 역상신호검출 릴레이 장치에 있어서는 다음과 같은 문제점이 있었다.Such a conventional phase open and reverse phase signal detection relay device has the following problems.
첫째, 역상 및 결상 검출회로가 2중화되어 있으므로 회로가 복잡하고 단가가 높아지는 문제점이 있었다.First, since the reverse phase and phase detection circuits are doubled, the circuit is complicated and the unit cost increases.
둘째, 결상회로에서 트랜지스터(TR3,TR4,TR5)를 거쳐 콘덴서(C7,C8,C9)로 충방전하도록 되어 있어 검출에 많은 시간이 소모되고 부정확하였다.Second, in the imaging circuit, the capacitors C7, C8, and C9 were charged and discharged through the transistors TR3, TR4, and TR5, which took a lot of time and was inaccurate.
셋째, 역상회로에서 입력(P1,P2,P3)의 크기에 따라 비교기(OP10)에 저항(R21, R22)으로 분압되어 기준전압으로 되어 있어 오동작의 영향 및 콘덴서(C2) 충방전 때문에 오차에 의한 검출시간이 많이 소요되며 부정확하였다.Third, in the reversed phase circuit, the comparator OP10 is divided by the resistors R21 and R22 according to the size of the inputs P1, P2, and P3 to become the reference voltage, which is caused by an error due to malfunction and charge / discharge of the capacitor C2. Detection time is long and inaccurate.
본 발명은 이상에서 언급한 종래 기술의 문제점을 감안하여 안출한 것으로서, 간단한 회로로 오차를 줄이고, 검출시간을 단축할 수 있는 결상 및 역상신호 검출 장치를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and an object thereof is to provide an imaging and reverse phase detection apparatus capable of reducing errors and shortening detection time with a simple circuit.
도 1은 종래 과전류 감지회로를 나타낸 회로도1 is a circuit diagram showing a conventional overcurrent detection circuit
도 2a는 종래 역상검출회로를 나타낸 도면Figure 2a is a diagram showing a conventional reverse phase detection circuit
도 2b는 종래 결상검출 회로를 나타낸 회로도Figure 2b is a circuit diagram showing a conventional phase detection circuit
도 3은 본 발명에 따른 역상 및 결상 검출회로를 나타낸 회로도3 is a circuit diagram showing a reverse phase and phase detection circuit according to the present invention;
도 4는 도 3의 전체 블록 구성도4 is a block diagram illustrating the entire block of FIG. 3.
도 5는 도 3에 나타낸 검출회로의 부분별 파형도FIG. 5 is a waveform diagram of parts of the detection circuit shown in FIG.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11, 12, 13 : 플립플롭 14 : 낸드 게이트11, 12, 13: flip-flop 14: NAND gate
15 : 노아 게이트 21 : 과부하 및 트립모듈15: Noah gate 21: Overload and trip module
본 발명의 특징은 R,S,T 3상의 변류기(CT)에서 출력되는 교류(AC)를 각각 직류로 정류하는 제 1, 제 2, 제 3 정류소자(D1,D2,D3)와, 상기 제 1, 제 2, 제 3 정류소자에서 각각 정류된 직류를 전압으로 변환하는 제 1, 제 2, 제 3 부담저항(R1,R2,R3)과, 상기 제 1, 제 2 및 제 3 부담저항에서 각각 출력되는 전압에 따라 O 또는 1의 논리 값을 출력하는 제 1, 제 2, 제 3 논리소자(U1,U2,U3)와, 상기 제 1, 제 2, 제 3 논리소자에서 각각 출력되는 논리 값에 따라 각각 제 1, 제 2 논리값을 출력하는 제 4, 제 5, 제 6 논리소자(11.12.13)와, 상기 제 4, 제 5, 제 6 논리소자의 제 1 논리값에 따라 상기 R,S,T 3상의 역상 신호를 출력하는 제 7 논리소자(14)와, 상기 제 4, 제 5, 제 6 논리소자의 제 2 논리값에 따라 제 3 논리값을 출력하는 제 8 논리소자(15)와, 상기 제 8 논리소자의 출력값에 따라 상기 R,S,T 3상의 결상 신호를 출력하는 제 9 논리소자로 구성됨에 있다.The present invention is characterized in that the first, second and third rectifying elements (D1, D2, D3) for rectifying the alternating current (AC) output from the three-phase current transformer (CT) of the R, S, T three phases, respectively, The first, second and third burden resistors R1, R2 and R3 for converting the direct current rectified by the first, second and third rectifier elements into voltages, and the first, second and third burden resistors First, second, and third logic elements U1, U2, and U3 outputting a logic value of O or 1 according to the output voltage, respectively, and logics respectively output from the first, second, and third logic elements. The fourth, fifth, and sixth logic elements 11.12.13 outputting the first and second logic values respectively according to the values, and the first, second, and sixth logic elements according to the first logic values of the fourth, fifth, and sixth logic elements. A seventh logic element 14 for outputting R, S, and T three-phase inverse signals; and an eighth logic element for outputting a third logic value according to the second logic value of the fourth, fifth, and sixth logic elements; 15 and R, S, and T 3 depending on the output value of the eighth logic element. And a ninth logic element for outputting an imaging signal of a phase.
이하 첨부된 도면을 참조하여 본 발명에 따른 결상 및 역상 신호 검출 장치를 설명하면 다음과 같다.Hereinafter, an imaging and reverse phase detection apparatus according to the present invention will be described with reference to the accompanying drawings.
도 3은 본 발명에 따른 결상 및 역상 신호 검출회로를 나타낸 회로도이고, 도 4는 도 3의 전체 블록 구성도이며, 도 5는 도 3에 나타낸 검출회로의 부분별 파형도이다.FIG. 3 is a circuit diagram illustrating an image forming and reverse phase detection circuit according to the present invention, FIG. 4 is a block diagram illustrating the entire block of FIG. 3, and FIG. 5 is a waveform diagram for each part of the detection circuit illustrated in FIG. 3.
본발명에 따른 결상 및 역상 검출 회로는 R,S,T 3상의 변류기(CT)에서 R,S,T 3상이 각각 제 1, 제 2, 제 3 다이오드(D1-D3)를 통과하여 부담저항(R1-R3)와 TTL로직(U1-U3)으로 입력된다.In the imaging and reverse phase detection circuit according to the present invention, the R, S, T three phases pass through the first, second, and third diodes D1-D3 in the R, S, and T three-phase current transformers CT, respectively. R1-R3) and TTL logic (U1-U3).
TTL로직(U1-U3) 출력은 각각의 제1부터 제 3 플립플롭(11,13,13)의 D와 CK으로 입력되고, 출력으로 Q는 낸드(NAND) 게이트(U7)로 들어가 출력으로 역상(REV)신호가 나오며 Q*(RQ*SQ*TQ*)는 노아(NOR) 게이트(U8)로 들어간다.The TTL logic (U1-U3) output is input to D and CK of each of the first to third flip-flops (11, 13, 13), and Q is output to the NAND gate (U7) to reverse the output. The (REV) signal is output and Q * (RQ * SQ * TQ *) enters the NOR gate U8.
그리고 노아 게이트(U8)의 출력은 인버터(U9)로 입력되어, 출력으로 결상(RPH) 신호가 나온다.The output of the NOR gate U8 is input to the inverter U9, and an image (RPH) signal is outputted to the output.
이와 같은 본 발명 결상 및 역상 검출 회로는 도 4의 전체 구성도를 보면 과부하 및 트립모듈(21)에서 역상(REV) 및 결상(RPH)의 신호를 받아 내부의 과부하와 오아(OR)되어 이상시 트립신호를 출력하여 기기에 전압을 차단하여 기기를 보호하게 된다.As described above, the phase-inversion and reverse-phase detection circuit of the present invention receives the signals of reverse phase (REV) and phase-out (RPH) from the overload and trip module 21, and when the overload and the phase of the internal phase are abnormal (OR). It outputs a trip signal to protect the device by cutting off the voltage to the device.
도 3을 좀더 상세히 설명하면 R, S, T 3상 CT에서 제 1, 제 2, 제 3 다이오드(D1-D3)를 통과하면, 3상 인 AC전류입력이 반파정류를 된다.Referring to FIG. 3 in detail, when the R, S, and T three-phase CTs pass through the first, second, and third diodes D1-D3, the three-phase AC current input is half-wave rectified.
이어서, 다이오드(D1-D3)를 통과하여 부담저항(R1-R3)과 연결되면 전류는 전압으로 변환되고 변화된 전압이 TTL 로직(U1,U2,U3)으로 입력된다.Subsequently, when the diodes D1-D3 are connected to the charge resistors R1-R3, the current is converted into a voltage and the changed voltage is input to the TTL logics U1, U2, and U3.
이때, 도 5의 검출회로의 부분별 파형도를 보면 Ra, Sa, Ta의 신호파형을 보면 TTL 로직(U1,U2,U3)소자를 거치면 출력으로 0또는 1인 로직으로 출력하게 된다. 이 출력이 도 5에서와 같이 RA, SA, TA의 파형으로 출력된다.At this time, when looking at the waveform diagram for each part of the detection circuit of FIG. 5, the signal waveforms of Ra, Sa, and Ta are output as logic 0 or 1 through the TTL logic (U1, U2, U3) elements. This output is output as a waveform of RA, SA, TA as shown in FIG.
TTL 로직(U1,U2,U3) 출력은 플립플롭(11,12,13)의 D와 플립플롭(11,12,13)의 CK으로 입력되고, TTL로직(U1,U2,U3)출력은 플립플롭(11,12,13)의 D와 플립플롭(11,12,13)의 CK으로 입력되며, TTL로직(U1,U2,U3)출력은 플립플롭(11,12,13)의 D와 플립플롭(11,12,13)의 CK로 입력된다.TTL logic (U1, U2, U3) outputs are input to D of flip-flops (11, 12, 13) and CK of flip-flops (11, 12, 13), and TTL logic (U1, U2, U3) outputs are flips. D of the flops 11, 12, 13 and CK of the flip flops 11, 12, 13 are inputted, and the TTL logic (U1, U2, U3) outputs are flipped with D of the flip flops 11, 12, 13; It is input to the CK of the flops 11, 12 and 13.
도 5에서는 정상동작시의 파형을 나타낸 것이며 아래의 표1의 정상 및 역상시의 동작상태와 같이 정상시에는 0(LOW),역상시에는 1(HIGH)를 출력하게 된다.FIG. 5 shows waveforms in normal operation and outputs 0 (LOW) in normal operation and 1 (HIGH) in reverse operation as in the normal and reverse phase operation states of Table 1 below.
또한 아래의 표2의 정상 및 S 상 결상시의 동작상태와 같이 정상시에는 0(LOW), 결상시에는 1(HIGH)을 출력한다. 즉 각상의 결상상태에 따라 플립플롭의 Q*의 출력이 각 상태에 따라서 달라진다.In addition, as in the normal and S phase open phases in Table 2 below, 0 (LOW) is displayed in normal operation and 1 (HIGH) is displayed in missing phase. In other words, the output of Q * of the flip-flop varies depending on the phase states of each phase.
이상의 설명에서와 같은 본 발명은 다음과 같은 효과가 있다.The present invention as described above has the following effects.
첫째, 결상 및 역상신호 검출 장치의 회로 구성이 단순하므로 검출장치의 단가를 낮출 수 있다.First, since the circuit configuration of the imaging and reversed phase detection device is simple, the unit cost of the detection device can be lowered.
둘째, 결상 및 역상 신호 검출시 플립플롭을 사용하여 논리적으로 검출하므로 신호검출이 정확하고 빠르다.Second, the detection of phase and reverse phase signals is done logically using flip-flops, so signal detection is accurate and fast.
셋째, 결상 및 역상신호 검출시 논리적으로 즉시 처리할 수 있으므로 기기에 공급되는 전원을 빠르게 차단할 수 있어 기기의 손상을 최소화할 수 있다.Third, because of the logical and immediate processing of the detection of phase and reverse signals, the power supply to the device can be cut off quickly, thereby minimizing damage to the device.
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| KR890019693U (en) * | 1988-03-22 | 1989-10-05 | 금성기전 주식회사 | Reverse and phase detection circuit of 3-phase power supply |
| JPH01305367A (en) * | 1988-06-03 | 1989-12-08 | Toshiba Corp | Phase relay |
| KR910002063A (en) * | 1989-06-20 | 1991-01-31 | 김인석 | Open phase and reverse phase detection relay device |
| KR920004850A (en) * | 1990-08-22 | 1992-03-28 | 백종영 | Phase detection circuit of 3-phase power supply |
| JPH07134154A (en) * | 1993-11-09 | 1995-05-23 | Mitsubishi Electric Corp | Abnormal current detecting device for three-phase load |
| KR970017757A (en) * | 1995-09-20 | 1997-04-30 | 김인석 | Phase detection method and apparatus for overload relay |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR890019693U (en) * | 1988-03-22 | 1989-10-05 | 금성기전 주식회사 | Reverse and phase detection circuit of 3-phase power supply |
| JPH01305367A (en) * | 1988-06-03 | 1989-12-08 | Toshiba Corp | Phase relay |
| KR910002063A (en) * | 1989-06-20 | 1991-01-31 | 김인석 | Open phase and reverse phase detection relay device |
| KR920004850A (en) * | 1990-08-22 | 1992-03-28 | 백종영 | Phase detection circuit of 3-phase power supply |
| JPH07134154A (en) * | 1993-11-09 | 1995-05-23 | Mitsubishi Electric Corp | Abnormal current detecting device for three-phase load |
| KR970017757A (en) * | 1995-09-20 | 1997-04-30 | 김인석 | Phase detection method and apparatus for overload relay |
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