KR100327538B1 - Voltage-to frequency converter circuit - Google Patents

Voltage-to frequency converter circuit Download PDF

Info

Publication number
KR100327538B1
KR100327538B1 KR1019980010591A KR19980010591A KR100327538B1 KR 100327538 B1 KR100327538 B1 KR 100327538B1 KR 1019980010591 A KR1019980010591 A KR 1019980010591A KR 19980010591 A KR19980010591 A KR 19980010591A KR 100327538 B1 KR100327538 B1 KR 100327538B1
Authority
KR
South Korea
Prior art keywords
voltage
output
circuit
offset
ladder
Prior art date
Application number
KR1019980010591A
Other languages
Korean (ko)
Other versions
KR19990076001A (en
Inventor
정용채
Original Assignee
구자홍
엘지전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, 엘지전자주식회사 filed Critical 구자홍
Priority to KR1019980010591A priority Critical patent/KR100327538B1/en
Publication of KR19990076001A publication Critical patent/KR19990076001A/en
Application granted granted Critical
Publication of KR100327538B1 publication Critical patent/KR100327538B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/70—Automatic control for modifying converter range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/78—Simultaneous conversion using ladder network
    • H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H01L2924/14211—Voltage-controlled oscillator [VCO]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2201/00—Aspects of oscillators relating to varying the frequency of the oscillations
    • H03B2201/02—Varying the frequency of the oscillations by electronic means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: A voltage-to-frequency converting circuit is provided to widen a control range by providing an offset to an output of a digital-to-analog converter. CONSTITUTION: An R-2R ladder circuit(111) receives digital output signals(A0-A7) of a microcomputer and outputs a multi-step voltage based on the respective digital signals. An offset power input part(113) adds a power supply voltage to an output voltage of the R-2R ladder circuit(111). An operational amplifier circuit(112) amplifies and outputs an output voltage of the R-2R ladder circuit(111) to which an offset voltage is applied through the offset power input part(113). A timer(20) varies a multi-step frequency input through a control pin based on an output of the operational amplifier circuit.

Description

전압/주파수 컨버터 회로{Voltage-to frequency converter circuit}Voltage-to-frequency converter circuit

본 발명은 전압/주파수(Voltage-to-Frequency, 이하 "V/F"라 칭함) 컨버터 회로에 관한 것으로, 특히 R-2R 래더(Ladder)형 디지털/아날로그 컨버터(Digital-to-Analog Converter, 이하 "DAC"라 칭함)를 갖는 V/F 컨버터 회로에서 DAC의 출력에 오프셋(Offset)을 주어 제어범위를 넓힌 V/F 컨버터 회로에 관한 것이다.The present invention relates to a voltage-to-frequency (hereinafter referred to as "V / F") converter circuit, in particular an R-2R ladder-type digital-to-analog converter (hereinafter referred to as "V / F"). In the V / F converter circuit having a "DAC", the offset of the output of the DAC to the V / F converter circuit to extend the control range.

종래 R-2R 래더형 DAC를 갖는 V/F 컨버터 회로는 도 1에 도시된 바와 같이,마이컴의 8비트 디지털 출력신호(A7∼A0)를 입력받아 각 디지털 신호에 따라 R-2R 래더회로(11)의 출력측에 나타나는 28(=256)단계의 출력전압을 연산증폭회로(12)를 통하여 소정의 이득으로 증폭하여 출력하는 R-2R 래더형 DAC(10)와, 제어단자(Control Pin)로 입력되는 상기 R-2R 래더형 DAC(10)의 출력에 따라 기 설정된 28(=256)단계의 주파수를 가변 출력하는 타이머(20)로 구성되어져 있다. 상기 래더회로(11)의 출력측에 연결된 저항(2R)은 전압을 분배하는 역할을 하고, 캐패시터(C1)은 전압을 유지하여 상기 연산증폭회로(12)로 안정된 전압을 공급하는 역할을 하는 것이다.As shown in FIG. 1, a conventional V / F converter circuit having an R-2R ladder type DAC receives an 8-bit digital output signal (A 7 to A 0 ) of a microcomputer and an R-2R ladder circuit according to each digital signal. R-2R ladder-type DAC 10 for amplifying and outputting the output voltage of 2 8 (= 256) steps to the predetermined gain through the operational amplifier circuit 12 and the control terminal (Control Pin) According to the output of the R-2R ladder-type DAC (10) is configured as a timer 20 for outputting a predetermined frequency of 2 8 (= 256) steps. The resistor 2R connected to the output side of the ladder circuit 11 distributes the voltage, and the capacitor C1 maintains the voltage to supply the stable voltage to the operational amplifier circuit 12.

이와 같이 구성된 종래 R-2R 래더형 DAC를 갖는 V/F 컨버터 회로의 동작을 첨부한 도 1을 참조하여 설명하면 다음과 같다.The operation of the V / F converter circuit having the conventional R-2R ladder type DAC configured as described above will be described with reference to FIG. 1.

먼저, 마이컴에서 8비트의 디지털 출력신호(A7∼A0)가 R-2R 래더형 DAC(10)의 R-2R 래더회로(11)로 입력되면 R-2R 래더회로(11)의 출력측에는 입력되는 디지털 신호의 변화에 따라 256단계의 전압이 나타나 연산증폭회로(12)의 (+)입력단자에 인가된다.First, when an 8-bit digital output signal A 7 to A 0 is input to the R-2R ladder circuit 11 of the R-2R ladder type DAC 10 by a microcomputer, the output side of the R-2R ladder circuit 11 In accordance with the change of the input digital signal, a voltage of 256 steps appears and is applied to the positive input terminal of the operational amplifier circuit 12.

즉, 마이컴의 전원전압이 5 V(Volt)일 때에 디지털 출력신호(A7∼A0)는 5 V(High) 또는 0 V(Low)로 나타나므로 이 신호를 입력받은 R-2R 래더회로(11)는 각각의 8비트 디지털 출력신호(A7∼A0)의 변화에 따라 0 V에서V(≒3.33 V)까지의 전압을 가변적으로 출력한다.That is, when the power supply voltage of the microcomputer is 5 V (Volt), the digital output signals A 7 to A 0 appear as 5 V (High) or 0 V (Low). Therefore, the R-2R ladder circuit ( 11) at 0 V according to the change of each 8-bit digital output signal (A 7 ~ A 0 ). Variable voltages up to V (3.33 V) are output.

이후, 이 출력전압은 R-2R 래더형 DAC(10)내 연산증폭회로(12)의 (+)입력단자로 인가되어의 이득(Gain)으로 궤환 증폭되어 타이머(20)의 제어단자(Control Pin)에 인가된다.This output voltage is then applied to the positive input terminal of the operational amplifier circuit 12 in the R-2R ladder type DAC 10. The feedback is amplified with a gain of and applied to the control pin of the timer 20.

그러면, 타이머(20)는 제어단자로 입력되는 R-2R 래더형 DAC(10)의 출력에 따라 기 설정된 256단계의 주파수를 가변적으로 출력한다.Then, the timer 20 variably outputs a preset frequency of 256 steps according to the output of the R-2R ladder type DAC 10 input to the control terminal.

그러나, 종래 실제의 R-2R 래더형 DAC를 갖는 V/F 컨버터 회로에서는 타이머(20)의 제어단자 전압이 일정전압 이상으로 올라가야만 안정된 동작을 나타내므로 256단계 중 약 30%에 해당하는 70∼80단계를 사용하지 못하는 문제점이 있었다.However, in the conventional V / F converter circuit having the R-2R ladder type DAC, since the control terminal voltage of the timer 20 rises above a certain voltage, it shows stable operation. There was a problem that can not use step 80.

상술하면, 가변 주파수를 출력하는 타이머(20)는 제어단자에 인가되는 전압이 커지면 출력주파수가 낮아져야 하는데 도 2에 도시된 바와 같이, 전압(타이머 제어단자 전압)이 낮은 소정의 인가전압 영역(비사용 영역)내에서 인가전압이 커지면 오히려 출력주파수가 올라가는 특성이 있기 때문이다.In detail, the timer 20 outputting the variable frequency should have a low output frequency as the voltage applied to the control terminal increases. As shown in FIG. 2, a predetermined applied voltage region having a low voltage (timer control terminal voltage) ( This is because the output frequency increases rather than the applied voltage in the non-use region).

이에, 출력주파수의 간격이 너무 넓어 종래의 V/F 컨버터 회로를 주파수제어를 통하여 출력을 제어하는 시스템(예: 유도가열조리기 등)에 적용하면 R-2R 래더형 DAC(10)의 각 출력단계별로 타이머(20)는 큰 출력의 변동을 가져오게 된다.Therefore, when the interval of the output frequency is too wide, if the conventional V / F converter circuit is applied to the system for controlling the output through the frequency control (for example, induction heating cooker, etc.) for each output step of the R-2R ladder type DAC (10) The furnace timer 20 will bring about a large output variation.

따라서 본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안한 것으로서, R-2R 래더형 DAC를 갖는 V/F 컨버터 회로에서 DAC의 출력에 오프셋(Offset)을 주어 제어범위를 넓힌 V/F 컨버터 회로를 제공하는데 그 목적이 있다.Therefore, the present invention has been proposed to solve the above problems of the prior art, in the V / F converter circuit having an R-2R ladder-type DAC in the V / F converter circuit by giving an offset (Offset) to the output of the DAC to widen the control range The purpose is to provide.

이러한 목적을 달성하기 위한 본 발명의 기술적 수단은, 마이컴의 디지털 출력신호를 입력받아 각 디지털 신호에 따라 다단계의 전압을 출력하는 R-2R 래더회로의 출력측 캐패시터에 일정 전원전압이 인가되는 저항이 병렬연결된 오프셋 전원입력부를 부가하여, R-2R 래더회로의 출력전압을 소정의 이득으로 증폭하는 연산증폭회로를 통해 제어단자로 입력되는 전압에 따라 기 설정된 다단계의 주파수를 가변 출력하는 타이머에서 제어단자에 입력되는 전압의 변동폭을 조절하는 것을 특징으로 한다.The technical means of the present invention for achieving the above object is that a resistor in which a constant power supply voltage is applied to an output capacitor of an R-2R ladder circuit that receives a digital output signal of a microcomputer and outputs a multi-level voltage according to each digital signal. In addition to the offset power input connected to the control terminal in the timer for outputting a variable multi-step frequency according to the voltage input to the control terminal through the operational amplifier circuit for amplifying the output voltage of the R-2R ladder circuit to a predetermined gain It is characterized by adjusting the fluctuation range of the input voltage.

도 1은 종래 R-2R 래더형 DAC를 갖는 V/F 컨버터 회로의 구성도.1 is a configuration diagram of a V / F converter circuit having a conventional R-2R ladder type DAC.

도 2는 도 1에 도시된 타이머의 동작 특성도.2 is an operation characteristic diagram of the timer shown in FIG. 1;

도 3은 본 발명에 의한 V/F 컨버터 회로의 구성도.3 is a configuration diagram of a V / F converter circuit according to the present invention.

*** 도면의 주요 부분에 대한 부호의 설명 ****** Explanation of symbols for the main parts of the drawing ***

110 : R-2R 래더형 DAC 111 : R-2R 래더회로110: R-2R ladder type DAC 111: R-2R ladder circuit

112 : 연산증폭회로 113 : 오프셋 전원입력부112: operational amplifier circuit 113: offset power input unit

이하, 본 발명을 첨부한 도면에 의거하여 설명하면 다음과 같다.Hereinafter, the present invention will be described with reference to the accompanying drawings.

도 3은 본 발명에 의한 V/F 컨버터 회로의 구성도를 나타낸 것으로서, 마이컴의 8비트 디지털 출력신호(A7∼A0)를 입력받아 각 디지털 신호에 따라 28(=256)단계의 전압을 출력하는 R-2R 래더회로(111)와, 상기 R-2R 래더회로(111)의 출력전압에 소정의 전원전압을 부가하여 오프셋(Offset)을 주는 오프셋 전원입력부(113)와, 상기 오프셋 전원입력부(113)에 의하여 오프셋이 주어진 상기 R-2R 래더회로(111)의 출력전압을 소정의 이득으로 증폭하여 출력하는 연산증폭회로(112)와, 제어단자(Control Pin)로 입력되는 상기 연산증폭회로(112)의 출력에 따라 기 설정된 28(=256)단계의 주파수를 가변 출력하는 타이머(20)로 구성되어져 있다.3 is a block diagram of a V / F converter circuit according to an embodiment of the present invention. The 8-bit digital output signals A 7 to A 0 of a microcomputer are inputted, and voltages of 2 8 (= 256) steps according to each digital signal are shown. An R-2R ladder circuit 111 for outputting an output, an offset power input unit 113 for providing an offset by adding a predetermined power supply voltage to the output voltage of the R-2R ladder circuit 111, and the offset power source An operational amplifier circuit 112 for amplifying and outputting the output voltage of the R-2R ladder circuit 111 given an offset by the input unit 113 to a predetermined gain, and the operational amplifier input to a control pin In accordance with the output of the circuit 112, the timer 20 is configured to variably output a preset frequency of 2 8 (= 256) steps.

즉, 상기 R-2R 래더회로(111)와 오프셋 전원입력부(113) 및 연산증폭회로(112)로 이루어진 본 발명의 R-2R 래더형 DAC(110)와 도 1에 도시된 종래의 R-2R 래더형 DAC를 비교하면, 종래에는 상기 R-2R 래더회로(111)의 출력측에 저항(2R)과 캐패시터(C1)를 단순히 병렬연결한데 반해 본 발명에서는 상기 저항(2R)에 일정 전원전압(V)을 인가함으로써 오프셋을 주는 오프셋 전원입력부(113)가 부가된다.That is, the R-2R ladder type DAC 110 according to the present invention including the R-2R ladder circuit 111, the offset power input unit 113, and the operational amplifier circuit 112, and the conventional R-2R shown in FIG. Comparing the ladder type DAC, the resistor 2R and the capacitor C1 are simply connected in parallel to the output side of the R-2R ladder circuit 111, whereas in the present invention, a constant power supply voltage (V) is applied to the resistor 2R. ), An offset power input unit 113 giving an offset is added.

이와 같이 구성된 본 발명에 의한 V/F 컨버터 회로의 동작 및 작용 효과를 첨부한 도면 도 3을 참조하여 설명하면 다음과 같다.Referring to Figure 3 attached to the operation and effect of the V / F converter circuit according to the present invention configured as described above are as follows.

먼저, 마이컴에서 8비트의 디지털 출력신호(A7∼A0)가 R-2R 래더형 DAC(110)의 R-2R 래더회로(111)로 입력되면 R-2R 래더회로(111)의 출력측에는 입력되는 디지털 신호의 변화에 따라 256단계의 전압이 나타난다.First, when an 8-bit digital output signal A 7 to A 0 is input to the R-2R ladder circuit 111 of the R-2R ladder type DAC 110 by a microcomputer, the output side of the R-2R ladder circuit 111 is provided. According to the change of the input digital signal, 256 steps of voltage appear.

즉, 마이컴의 전원전압이 5 V(Volt)일 때에 디지털 출력신호(A7∼A0)는 5 V(High) 또는 0 V(Low)로 나타나므로 이 신호를 입력받은 R-2R 래더회로(111)는 각각의 8비트 디지털 출력신호(A7∼A0)의 변화에 따라 0 V에서V(≒3.33 V)까지의 전압을 가변적으로 출력한다.That is, when the power supply voltage of the microcomputer is 5 V (Volt), the digital output signals A 7 to A 0 appear as 5 V (High) or 0 V (Low). Therefore, the R-2R ladder circuit ( 111) is at 0 V according to changes in each of the 8-bit digital output signal (a 7 ~A 0) Variable voltages up to V (3.33 V) are output.

이때, R-2R 래더회로(111) 출력측의 캐패시터(C1)와 병렬연결된 저항(2R)이 일정 전원전압(V)과 상기 캐패시터(C1) 사이에 연결된 오프셋 전원입력부(113)에 의하여 R-2R 래더회로(111)의 출력전압에 소정의 전원전압이 부가되어 오프셋(Offset)이 주어져 R-2R 래더형 DAC(110)내 연산증폭회로(112)의 (+)입력단자로 인가된다.At this time, the resistor 2R connected in parallel with the capacitor C1 at the output side of the R-2R ladder circuit 111 is connected to the constant power supply voltage V and the capacitor C1 by the offset power input unit 113 connected to the R-2R. A predetermined power supply voltage is added to the output voltage of the ladder circuit 111 to give an offset and applied to the positive input terminal of the operational amplifier circuit 112 in the R-2R ladder type DAC 110.

상술하면, 오프셋 전원입력부(113)의 저항(2R)에 인가되는 일정 전원전압(V)이 5 V일 때에 R-2R 래더회로(111)의 출력인 0 V에서V(≒3.33 V)까지의 전압에는V(≒1.67 V)의 오프셋이 가해진다. 따라서, 연산증폭회로(112)의 (+)입력단자로 인가되는 전압은V(≒1.67 V)에서 5 V까지의 변동폭을 갖게된다.In detail, when the constant power supply voltage V applied to the resistor 2R of the offset power supply input 113 is 5V, at 0V which is the output of the R-2R ladder circuit 111. Voltages up to V (≒ 3.33 V) An offset of V (# 1.67 V) is applied. Therefore, the voltage applied to the positive input terminal of the operational amplifier circuit 112 It has a variation range from V (≒ 1.67 V) to 5 V.

즉, 마이컴의 출력이 0 단계이면 연산증폭회로(112)의 (+)입력단자로 인가되는 전압은V(≒1.67 V)가 되고, 마이컴의 출력이 255 단계이면 연산증폭회로(112)의 (+)입력단자로 인가되는 전압은 5 V가 된다.That is, when the output of the microcomputer is 0, the voltage applied to the positive input terminal of the operational amplifier circuit 112 is V (≒ 1.67 V) and the output of the microcomputer is 255 steps, the voltage applied to the positive input terminal of the operational amplifier circuit 112 is 5V.

이후, 이 출력전압은 연산증폭회로(112)를 통하여의 이득(Gain)으로 궤환 증폭되어 타이머(20)의 제어단자(Control Pin)에 인가된다.This output voltage is then passed through the operational amplifier circuit 112. The feedback is amplified with a gain of and applied to the control pin of the timer 20.

그러면, 타이머(20)는 제어단자로 입력되는 R-2R 래더형 DAC(110)의 출력에 따라 기 설정된 256단계의 주파수를 가변적으로 출력한다.Then, the timer 20 variably outputs a preset frequency of 256 steps according to the output of the R-2R ladder type DAC 110 input to the control terminal.

이상에서 설명한 바와 같이 본 발명은 R-2R 래더형 DAC를 갖는 V/F 컨버터 회로에서 DAC의 출력에 오프셋(Offset)을 주어 제어범위를 넓힘으로써, 종래의 V/F 컨버터 회로와 대비하여 약 50%의 향상된 제어범위를 가질 뿐만 아니라 제어범위가 넓어짐에 따라 제어동작의 안정성이 향상되는 효과가 있다.As described above, the present invention provides an offset of the output of the DAC in the V / F converter circuit having the R-2R ladder type DAC to widen the control range, thereby increasing the control range by about 50 compared with the conventional V / F converter circuit. In addition to having an improved control range of%, as the control range is widened, stability of the control operation is improved.

Claims (2)

마이컴의 디지털 출력신호(A7∼A0)를 입력받아 각 디지털 신호에 따라 다단계의 전압을 출력하는 R-2R 래더회로(111)와,An R-2R ladder circuit 111 for receiving a micro-computing digital output signal A 7 to A 0 and outputting a multi-step voltage according to each digital signal, 상기 R-2R 래더회로(111)의 출력전압에 소정의 전원전압을 부가하여 오프셋(Offset)을 주는 오프셋 전원입력부(113)와,An offset power input unit 113 for providing an offset by adding a predetermined power supply voltage to the output voltage of the R-2R ladder circuit 111; 상기 오프셋 전원입력부(113)에 의하여 오프셋이 주어진 상기 R-2R 래더회로(111)의 출력전압을 소정의 이득으로 증폭하여 출력하는 연산증폭회로(112)와,An operational amplifier circuit 112 for amplifying and outputting the output voltage of the R-2R ladder circuit 111 given an offset by the offset power input unit 113 to a predetermined gain; 제어단자(Control Pin)로 입력되는 상기 연산증폭회로(112)의 출력에 따라 기 설정된 다단계의 주파수를 가변 출력하는 타이머(20)를 포함하여 구성된 것을 특징으로 하는 전압/주파수 컨버터 회로.And a timer (20) configured to variably output a preset multi-step frequency according to the output of the operational amplifier circuit (112) input to a control terminal (Control Pin). 제 1 항에 있어서,The method of claim 1, 상기 오프셋 전원입력부(113)는 상기 R-2R 래더회로(111)의 출력측 캐패시터(C1)에 일정 전원전압(V)이 인가되는 저항(2R)이 병렬연결된 것을 특징으로 하는 전압/주파수 컨버터 회로.The offset power input unit 113 is a voltage / frequency converter circuit, characterized in that the resistor (2R) is applied in parallel to the output side capacitor (C1) of the R-2R ladder circuit 111 is applied in parallel.
KR1019980010591A 1998-03-26 1998-03-26 Voltage-to frequency converter circuit KR100327538B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019980010591A KR100327538B1 (en) 1998-03-26 1998-03-26 Voltage-to frequency converter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980010591A KR100327538B1 (en) 1998-03-26 1998-03-26 Voltage-to frequency converter circuit

Publications (2)

Publication Number Publication Date
KR19990076001A KR19990076001A (en) 1999-10-15
KR100327538B1 true KR100327538B1 (en) 2002-04-17

Family

ID=37478422

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980010591A KR100327538B1 (en) 1998-03-26 1998-03-26 Voltage-to frequency converter circuit

Country Status (1)

Country Link
KR (1) KR100327538B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7535121B2 (en) 2003-05-14 2009-05-19 Samsung Electronics Co., Ltd. High voltage power supply apparatus and method of correcting current output from the apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4398179A (en) * 1980-12-03 1983-08-09 Sony Corporation Analog-to-digital converting circuit
US5034699A (en) * 1990-11-14 1991-07-23 Tektronix, Inc. Trimming of operational amplifier gain

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4398179A (en) * 1980-12-03 1983-08-09 Sony Corporation Analog-to-digital converting circuit
US5034699A (en) * 1990-11-14 1991-07-23 Tektronix, Inc. Trimming of operational amplifier gain

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7535121B2 (en) 2003-05-14 2009-05-19 Samsung Electronics Co., Ltd. High voltage power supply apparatus and method of correcting current output from the apparatus

Also Published As

Publication number Publication date
KR19990076001A (en) 1999-10-15

Similar Documents

Publication Publication Date Title
AU681642B2 (en) Power amplifier bias control circuit and method
US4814649A (en) Dual gate FET mixing apparatus with feedback means
US6333675B1 (en) Variable gain amplifier with gain control voltage branch circuit
US5422598A (en) High-frequency power amplifier device with drain-control linearizer circuitry
KR100327538B1 (en) Voltage-to frequency converter circuit
EP0532203B1 (en) Power controller
US5361048A (en) Pulse width modulator having a duty cycle proportional to the amplitude of an input signal from a differential transducer amplifier
KR930003522B1 (en) Amplifier with current mirror circuit
US5039887A (en) Circuit arrangement for controlling the level of electrical signals
US4642608A (en) Digital-to-analogue converter arrangement
EP1039362A1 (en) Direct voltage to PTAT current converter for multiple gain control slope for wide dynamic range VGA
KR100592599B1 (en) Temperature Compensation and Linear Gain Control Apparatus for RF Transceiver
KR200190642Y1 (en) Apparatus for controlling output of converter
KR102400167B1 (en) Rf transceiver having linear gain control function
EP0429402A2 (en) A device for supplying power to gas-discharge lamps for use in motor vehicles
CN110113017B (en) Variable gain amplifier device and power system
KR950008788B1 (en) Lcd brightness control circuit using d/a converter
SU1124425A2 (en) Power amplifier
SU1451670A1 (en) Stabilized d.c. voltage source
KR960013042B1 (en) Amp gain control circuit using impedance control
SU974357A1 (en) Precision pulse dc voltage source
JPS63220609A (en) High frequency variable output circuit
KR100358767B1 (en) Circuit for compensation signal in induction heating cooker
JPH03297099A (en) High frequency power supply device for high frequency acceleration cavity
KR940001794B1 (en) Attenuation control circuit of wireless telephone

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050126

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee