KR100325668B1 - A manufacturing method of thin film transistor array panel for liquid crystal display - Google Patents
A manufacturing method of thin film transistor array panel for liquid crystal display Download PDFInfo
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- KR100325668B1 KR100325668B1 KR1019990040084A KR19990040084A KR100325668B1 KR 100325668 B1 KR100325668 B1 KR 100325668B1 KR 1019990040084 A KR1019990040084 A KR 1019990040084A KR 19990040084 A KR19990040084 A KR 19990040084A KR 100325668 B1 KR100325668 B1 KR 100325668B1
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- 239000010409 thin film Substances 0.000 title claims description 19
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 230000001681 protective effect Effects 0.000 claims abstract description 23
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 15
- 239000011651 chromium Substances 0.000 claims description 13
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical group [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 12
- 229910052804 chromium Inorganic materials 0.000 claims description 12
- 238000004380 ashing Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 76
- 238000000034 method Methods 0.000 description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
게이트 배선을 이중층으로 형성하고, 게이트 절연막, 반도체층, 접촉층을 형성하고, 데이터 배선을 이중층으로 형성한다. 데이터 배선 위에 보호막을 적층하고 보호막 위에 감광막을 도포하고 노광, 현상하여 접촉구가 형성될 부분의 보호막을 노출시킨다. 노출된 보호막을 식각하여 1차 접촉구 패턴을 형성하고, 감광막을 애싱하여 1차 접촉구 패턴 주위의 보호막을 추가로 노출시킨다. 1차 접촉구 패턴을 통하여 노출되어 있는 게이트 패드, 데이터 패드 및 드레인 전극의 상부층을 식각하고 보호막을 다시 식각한다. ITO 또는 IZO를 적층하고 패터닝하여 화소 전극과 보조 패드를 형성한다. 이렇게 하면, 접촉구를 계단형으로 형성할 수 있고 이를 통해 접촉구를 통한 화소 전극과 드레인 전극 및 패드와 보조 패드 사이의 전기적 연결의 신뢰성을 향상시킬 수 있다.A gate wiring is formed in a double layer, a gate insulating film, a semiconductor layer, and a contact layer are formed, and a data wiring is formed in a double layer. A protective film is laminated on the data line, a photosensitive film is applied on the protective film, and the photoresist film is exposed and developed to expose the protective film of the portion where the contact hole is to be formed. The exposed protective film is etched to form a primary contact hole pattern, and the photosensitive film is ashed to further expose the protective film around the primary contact hole pattern. The upper layer of the gate pad, the data pad, and the drain electrode exposed through the first contact hole pattern is etched and the passivation layer is etched again. ITO or IZO are stacked and patterned to form pixel electrodes and auxiliary pads. In this way, the contact hole can be formed stepped, thereby improving the reliability of the electrical connection between the pixel electrode and the drain electrode and the pad and the auxiliary pad through the contact hole.
Description
본 발명은 액정 표시 장치용 박막 트랜지스터 기판의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device.
액정 표시 장치는 일반적으로 공통 전극과 컬러 필터(color filter) 등이 형성되어 있는 상부 기판과 박막 트랜지스터와 화소 전극 등이 형성되어 있는 하부 기판 사이에 액정 물질을 주입해 놓고 화소 전극과 공통 전극에 서로 다른 전위를 인가함으로써 전계를 형성하여 액정 분자들의 배열을 변경시키고, 이를 통해 빛의투과율을 조절함으로써 화상을 표현하는 장치이다.In general, a liquid crystal display device injects a liquid crystal material between an upper substrate on which a common electrode, a color filter, and the like are formed, and a lower substrate on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to adjust the transmittance of light to express the image.
액정 표시 장치에 있어서 박막 트랜지스터 기판이라 불리는 하부 기판에는 스위칭 소자인 박막 트랜지스터와 접촉구를 통하여 그에 연결되는 화소 전극이 형성된다.In the liquid crystal display, a lower electrode called a thin film transistor substrate is formed with a thin film transistor, which is a switching element, and a pixel electrode connected thereto through a contact hole.
그러면 도면을 참고로 하여 종래의 기술에 따른 박막 트랜지스터 기판에 대하여 살펴본다.Next, a thin film transistor substrate according to the related art will be described with reference to the accompanying drawings.
도 1은 종래의 기술에 따른 액정 표시 장치용 박막 트랜지스터 기판의 단면도이다.1 is a cross-sectional view of a thin film transistor substrate for a liquid crystal display device according to the related art.
절연 기판(100) 위에 크롬(Cr)층(210, 220)과 알루미늄-네오디늄(Al-Nd)층 (310, 320)의 2중층으로 이루어진 게이트 전극(210, 310)과 게이트 패드(220, 320)를 포함하는 게이트 배선이 형성되어 있고, 게이트 배선 위에 게이트 절연막(40)이 덮여 있다.Gate electrodes 210 and 310 and gate pads 220 formed of a double layer of chromium (Cr) layers 210 and 220 and aluminum-neodynium (Al-Nd) layers 310 and 320 on the insulating substrate 100. A gate wiring including 320 is formed, and a gate insulating film 40 is covered on the gate wiring.
게이트 절연막(40) 위에는 반도체층(500)이 형성되어 있고, 반도체층(500)의 위에는 양편으로 분리된 접촉층(610, 620)이 형성되어 있다.The semiconductor layer 500 is formed on the gate insulating layer 40, and the contact layers 610 and 620 separated on both sides are formed on the semiconductor layer 500.
접촉층(610, 620)의 위에는 크롬층(710, 720, 730)과 알루미늄-네오디늄층(810, 820, 830)의 이중층으로 이루어진 소스 전극(710, 810), 드레인 전극(720, 820) 및 데이터 패드(730, 830)를 포함하는 데이터 배선이 형성되어 있다.On the contact layers 610 and 620, the source electrodes 710 and 810 and the drain electrodes 720 and 820 formed of a double layer of chromium layers 710, 720 and 730 and aluminum-neodynium layers 810, 820 and 830. And data wirings including data pads 730 and 830.
데이터 배선의 위에는 접촉구(910, 920, 930)를 가지는 보호막(900)이 형성되어 있다.The passivation layer 900 having contact holes 910, 920, and 930 is formed on the data line.
보호막(900) 위에는 ITO(indium tin oxide) 등으로 이루어진 화소 전극(1100)과 보조 패드(1200, 1300)가 형성되어 있고, 화소 전극(1100)과 보조 패드(1200, 1300)는 각각 접촉구(910, 920, 930)를 통하여 드레인 전극의 하부층(720), 게이트 패드의 하부층(220) 및 데이터 패드의 하부층(730)과 연결되어 있다.The pixel electrode 1100 and the auxiliary pads 1200 and 1300 made of indium tin oxide (ITO) or the like are formed on the passivation layer 900, and the pixel electrode 1100 and the auxiliary pads 1200 and 1300 are respectively contact holes ( The lower layer 720 of the drain electrode, the lower layer 220 of the gate pad, and the lower layer 730 of the data pad are connected through the 910, 920, and 930.
이 때, 드레인 전극, 게이트 패드 및 데이터 패드의 상부층(820, 320, 830)은 접촉구(910, 920, 930) 하부에서 제거되어 화소 전극(1100) 및 보조 패드(1200, 1300)와의 사이에 공동(A, B, C)이 형성되어 있다.In this case, the upper layers 820, 320, and 830 of the drain electrode, the gate pad, and the data pad are removed from the lower portions of the contact holes 910, 920, and 930, and are disposed between the pixel electrode 1100 and the auxiliary pads 1200 and 1300. The cavities A, B, and C are formed.
이와 같이, 공동(A, B, C)이 형성되는 것은 접촉구(910, 920, 930) 형성 후에 알루미늄-네오디늄층(320, 820, 830)을 식각하여 제거하는 과정에서 과도 식각되기 때문이다. 그런데 이러한 공동(A, B, C)은 접촉구(910, 920, 930)를 통한 ITO층(1100, 1200, 1300)과 크롬층(220, 720, 730)의 연결을 나쁘게 한다. 이는 공동(A, B, C)에서 ITO층(1100, 1200, 1300)이 절단될 가능성이 높기 때문이다.As described above, the cavity A, B, and C are formed because they are excessively etched in the process of etching and removing the aluminum-neodynium layers 320, 820, and 830 after the formation of the contact holes 910, 920, and 930. . However, such cavities A, B, and C deteriorate the connection between the ITO layers 1100, 1200, and 1300 and the chromium layers 220, 720, and 730 through the contact holes 910, 920, and 930. This is because the ITO layers 1100, 1200, 1300 are more likely to be cut in the cavities A, B, and C.
본 발명이 이루고자 하는 기술적 과제는 접촉구를 통한 층간 연결의 신뢰성을 높이는 것이다.The technical problem to be achieved by the present invention is to increase the reliability of the interlayer connection through the contact hole.
도 1은 종래의 기술에 따른 액정 표시 장치용 박막 트랜지스터 기판의 단면도이고,1 is a cross-sectional view of a thin film transistor substrate for a liquid crystal display device according to the related art.
도 2는 본 발명의 실시예에 따른 액정 표시 장치용 박막 트랜지스터 기판의 단면도이고,2 is a cross-sectional view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.
도 3a 내지 도 3e는 도 2의 본 발명의 실시예에 따른 제조 방법에 따라 박막 트랜지스터 기판을 제조하는 과정을 나타내는 단면도이다.3A through 3E are cross-sectional views illustrating a process of manufacturing a thin film transistor substrate according to the manufacturing method of FIG. 2.
이러한 과제를 해결하기 위하여 본 발명에서는 2회의 식각을 통하여 보호막에 접촉구를 형성한다.In order to solve this problem, the present invention forms contact holes in the protective film through two etchings.
구체적으로는, 절연 기판 위에 2중층인 게이트 배선과 게이트 절연막, 반도체층, 접촉층 및 2중층인 데이터 배선을 형성하는 단계, 데이터 배선 위에 보호막을 적층하는 단계, 보호막 위에 감광막을 도포, 노광 및 현상하여 접촉구가 형성될 부분의 상기 보호막을 노출시키는 단계, 노출된 보호막과 그 하부의 게이트 절연막을 식각하여 1차 접촉구 패턴을 형성하는 단계, 감광막을 애싱하여 1차 접촉구 패턴 주위의 보호막을 노출시키는 단계, 1차 접촉구 패턴을 통하여 노출된 게이트 배선 및 데이터 배선의 상부층을 식각하는 단계, 보호막을 다시 식각하여 접촉구를 완성하는 단계, 접촉구를 통하여 상기 게이트 배선과 상기 데이터 배선의 노출되어 있는 부분과 연결되는 화소 전극 및 보조 패드를 형성하는 단계를 포함하는 과정을 통하여 박막 트랜지스터 기판을 제조한다.Specifically, forming a double layer gate wiring and a gate insulating film, a semiconductor layer, a contact layer and a double data layer on an insulating substrate, laminating a protective film on the data wiring, applying a photosensitive film on the protective film, exposure and development Exposing the passivation layer of the portion where the contact hole is to be formed, etching the exposed passivation layer and the gate insulating layer thereunder to form a primary contact hole pattern, and ashing the photoresist to protect the protective film around the primary contact hole pattern. Exposing the upper layers of the gate wiring and the data wiring exposed through the first contact hole pattern, etching the protective film again to complete the contact hole, and exposing the gate wiring and the data wire through the contact hole. A thin film transistor through a process including forming a pixel electrode and an auxiliary pad connected to a portion To prepare the foundation board.
이 때, 1차 접촉구 패턴을 통하여 노출된 게이트 배선 및 데이터 배선의 상부층을 식각하는 단계와 감광막을 애싱함으로써 1차 접촉구 패턴 주위의 보호막을 노출시키는 단계는 서로 순서를 바꿀 수 있다.At this time, the steps of etching the upper layers of the gate wiring and the data wiring exposed through the primary contact hole pattern and exposing the protective film around the primary contact hole pattern by ashing the photoresist may be reversed.
또, 화소 전극과 보조 패드는 ITO 또는 IZO로 이루어질 수 있으며, 게이트 배선과 데이터 배선의 상부층은 알루미늄-네오디늄층이고 하부층은 크롬층일 수 있다.In addition, the pixel electrode and the auxiliary pad may be made of ITO or IZO. The upper layer of the gate line and the data line may be an aluminum-neodynium layer, and the lower layer may be a chromium layer.
그러면 도면을 참고로 하여 본 발명의 실시예에 따른 액정 표시 장치용 박막 트랜지스터 기판의 구조에 대하여 설명한다.Next, a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.
도 2는 본 발명의 실시예에 따른 액정 표시 장치용 박막 트랜지스터 기판의 단면도이다.2 is a cross-sectional view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.
절연 기판(10) 위에 게이트 패드(22, 32)와 게이트 전극(21, 31) 및 게이트선(도시하지 않음)으로 이루어지는 게이트 배선이 형성되어 있다. 게이트 배선은 크롬층(21, 22)과 그 위의 알루미늄-네오디늄층(31, 32)의 이중층으로 이루어져 있다. 이 때, 게이트 패드(22, 32)의 알루미늄-네오디늄층(32)은 일부가 제거되어 하부의 크롬층(22)을 노출시키고 있다.Gate wirings including gate pads 22 and 32, gate electrodes 21 and 31, and gate lines (not shown) are formed on the insulating substrate 10. The gate wiring consists of a double layer of chromium layers 21 and 22 and aluminum-neodynium layers 31 and 32 thereon. At this time, the aluminum-neodynium layer 32 of the gate pads 22 and 32 is partially removed to expose the lower chromium layer 22.
게이트 배선의 위에는 질화규소(SiNx)로 이루어진 게이트 절연막(40)이 형성되어 있고, 게이트 전극(21, 31) 상부의 게이트 절연막(40) 위에는 수소화 비정질 규소 등으로 이루어진 반도체층(50)이 형성되어 있다.A gate insulating film 40 made of silicon nitride (SiNx) is formed on the gate wiring, and a semiconductor layer 50 made of hydrogenated amorphous silicon or the like is formed on the gate insulating film 40 on the gate electrodes 21 and 31. .
반도체층(50)의 위에는 게이트 전극(21, 31)을 중심으로 하여 양편으로 분리되어 있는 접촉층(61, 62)이 형성되어 있다. 접촉층(61, 62)은 인(P) 등의 5족 원소로 고농도로 도핑된 비정질 규소로 이루어져 있으며, 반도체층(50)과 그 위에 형성될 데이터 금속층 사이의 접촉 저항을 감소시키는 역할을 한다.On the semiconductor layer 50, contact layers 61 and 62 are formed on both sides of the gate electrodes 21 and 31, respectively. The contact layers 61 and 62 are made of amorphous silicon heavily doped with Group 5 elements such as phosphorus (P), and serve to reduce the contact resistance between the semiconductor layer 50 and the data metal layer to be formed thereon. .
접촉층(61, 62)의 위에는 소스 전극(71, 81)과 드레인 전극(72, 82)이 형성되어 있고, 소스 전극(71, 81)은 데이터선(도시하지 않음)과 연결되어 있다. 데이터선의 끝에는 데이터 패드(73, 83)가 형성되어 있다. 소스 전극(71, 81), 드레인 전극(72, 82), 데이터선 및 데이터 패드(73, 83)를 포함하여 데이터 배선이라 한다. 데이터 배선은 게이트 배선과 마찬가지로 크롬층(21, 22)과 그 위의 알루미늄-네오디늄층(31, 32)의 이중층으로 이루어져 있다. 이 때, 드레인 전극(72, 82)과 데이터 패드(73, 83)의 알루미늄-네오디늄층(82, 83)은 일부가 제거되어 그 하부의 크롬층(72, 73)을 노출시키고 있다.The source electrodes 71 and 81 and the drain electrodes 72 and 82 are formed on the contact layers 61 and 62, and the source electrodes 71 and 81 are connected to data lines (not shown). Data pads 73 and 83 are formed at the end of the data line. The data wirings include the source electrodes 71 and 81, the drain electrodes 72 and 82, the data lines and the data pads 73 and 83. As with the gate wiring, the data wiring is composed of a double layer of chromium layers 21 and 22 and aluminum-neodynium layers 31 and 32 thereon. At this time, part of the aluminum-neodynium layers 82 and 83 of the drain electrodes 72 and 82 and the data pads 73 and 83 are removed to expose the lower chromium layers 72 and 73.
데이터 배선의 위에는 질화규소 등으로 이루어진 보호막(90)이 형성되어 있다. 보호막(90)에는 드레인 전극(72, 82), 데이터 패드(73, 83) 및 게이트 패드(22, 32)의 크롬층(72, 73, 22)이 노출되어 있는 부분과 그 주위의 알루미늄-네오디늄층(82, 83, 32)을 노출시키는 제1 내지 제3 접촉구(91, 92, 93)가 형성되어 있다. 제2 접촉구(92)는 게이트 절연막(40)에도 동일한 모양으로 형성되어 있다.On the data line, a protective film 90 made of silicon nitride or the like is formed. The passivation layer 90 has exposed portions of the chromium layers 72, 73, and 22 of the drain electrodes 72 and 82, the data pads 73 and 83, and the gate pads 22 and 32, and aluminum-neo thereof. First to third contact holes 91, 92, and 93 exposing the dinium layers 82, 83, and 32 are formed. The second contact hole 92 is formed in the same manner in the gate insulating film 40.
보호막(90)의 위에는 ITO 또는 IZO(indium zinc oxide) 등의 투명한 도전 물질로 이루어진 화소 전극(110)과 보조 게이트 패드(120) 및 보조 데이터 패드(130)가 형성되어 있다. 화소 전극(110)과 보조 패드(120, 130)는 각각 제1 내지 제3 접촉구(91, 92, 93)를 통하여 드레인 전극(72, 82), 게이트 패드(22, 32) 및 데이터 패드(73, 83)와 연결되어 있다.The pixel electrode 110, the auxiliary gate pad 120, and the auxiliary data pad 130 made of a transparent conductive material such as ITO or indium zinc oxide (IZO) are formed on the passivation layer 90. The pixel electrode 110 and the auxiliary pads 120 and 130 are respectively connected to the drain electrodes 72 and 82, the gate pads 22 and 32, and the data pads through the first to third contact holes 91, 92, and 93, respectively. 73, 83).
여기서 접촉구(91, 92. 93)가 계단형으로 형성되어 있어서 단차로 인한 단절의 염려가 적다.Here, the contact holes 91 and 92. 93 are formed in a step shape, so there is little concern about disconnection due to the step.
그러면 이러한 구조의 박막 트랜지스터 기판을 제조하는 방법을 설명한다.Next, a method of manufacturing a thin film transistor substrate having such a structure will be described.
도 3a 내지 도 3e는 도 2의 본 발명의 실시예에 따른 제조 방법에 따라 박막 트랜지스터 기판을 제조하는 과정을 나타내는 단면도이다.3A through 3E are cross-sectional views illustrating a process of manufacturing a thin film transistor substrate according to the manufacturing method of FIG. 2.
도 3a에 나타낸 바와 같이, 절연 기판(10) 위에 크롬층과 알루미늄-네오디늄층을 각각 500Å과 2,500Å의 두께로 증착하고 제1 사진 식각 공정을 통하여 패터닝함으로써 게이트 배선을 형성한다. 게이트 배선 위에 게이트 절연막(40), 비정질 규소층, 도핑된 비정질 규소층을 차례로 증착하고 도핑된 비정질 규소층과 비정질 규소층을 제2 사진 식각 공정을 통하여 함께 패터닝하여 반도체층(50)과 분리되지 않은 접촉층(71, 72)을 형성한다. 접촉층(71, 72) 위에 크롬층과 알루미늄-네오디늄층을 각각 500Å과 2,500Å의 두께로 증착하고 제3 사진 식각 공정을 통하여 패터닝하여 데이터 배선을 형성한다. 데이터 배선 위에 보호막(90)을 적층한다.As shown in FIG. 3A, a gate wiring is formed by depositing a chromium layer and an aluminum-neodynium layer on the insulating substrate 10 to a thickness of 500 kPa and 2,500 kPa, respectively, and patterning them through a first photolithography process. The gate insulating layer 40, the amorphous silicon layer, and the doped amorphous silicon layer are sequentially deposited on the gate wirings, and the doped amorphous silicon layer and the amorphous silicon layer are patterned together through a second photolithography process to not be separated from the semiconductor layer 50. Contact layers 71 and 72 are formed. A chromium layer and an aluminum-neodynium layer are deposited on the contact layers 71 and 72 to a thickness of 500 mW and 2,500 mW, respectively, and patterned through a third photolithography process to form data lines. The protective film 90 is laminated on the data line.
다음, 도 3b에 나타낸 바와 같이, 보호막(90) 위에 감광막(PR)을 도포하고 제4 마스크를 통하여 노광 현상하여 접촉구(91, 92, 93)가 형성될 부분의 보호막(90)을 노출시킨다. 노출된 보호막(90)과 그 하부의 게이트 절연막(40)을 식각하여 접촉구(91, 92, 93)의 1차 패턴을 형성한다.Next, as shown in FIG. 3B, the photoresist film PR is coated on the protective film 90 and exposed to light through a fourth mask to expose the protective film 90 of the portion where the contact holes 91, 92, and 93 are to be formed. . The exposed protective layer 90 and the gate insulating layer 40 below are etched to form primary patterns of the contact holes 91, 92, and 93.
도 3c에 나타낸 바와 같이, 감광막(PR)을 애싱(ashing)하여 감광막(PR)의 두께를 얇게 한다. 이 때, 접촉구(91, 92, 93)의 1차 패턴 주변의 감광막(PR)이 제거되면서 접촉구(91, 92, 93)의 1차 패턴 주변의 보호막(90)이 추가로 노출된다.As shown in FIG. 3C, the photoresist film PR is ashed to reduce the thickness of the photoresist film PR. At this time, the photoresist film PR around the primary patterns of the contact holes 91, 92, and 93 is removed, and the protective film 90 around the primary pattern of the contact holes 91, 92, and 93 is further exposed.
도 3d에 나타낸 바와 같이, 접촉구(91, 92, 93)의 1차 패턴을 통하여 노출되어 있는 알루미늄-네오디늄층(32, 82, 83)을 식각한다. 이 때, 알루미늄-네오디늄층(32, 82, 83)은 보호막(90) 또는 게이트 절연막(40) 하부로도 식각되어 공동을 형성하게 된다.As shown in FIG. 3D, the aluminum-neodynium layers 32, 82, and 83 exposed through the primary patterns of the contact holes 91, 92, and 93 are etched. In this case, the aluminum-neodynium layers 32, 82, and 83 may also be etched into the lower portion of the passivation layer 90 or the gate insulating layer 40 to form a cavity.
여기서, 알루미늄-네오디늄층(32, 82, 83)을 식각하는 것은 후에 형성될 ITO 또는 IZO층이 알루미늄과 직접 접촉하면 109정도의 높은 접촉 저항을 갖기 때문이다.The etching of the aluminum-neodynium layers 32, 82, and 83 is because the ITO or IZO layer to be formed later has a high contact resistance of about 10 9 when it is in direct contact with aluminum.
이상에서 감광막(PR)의 애싱과 알루미늄-네오디늄층(32, 82, 83)의 식각은 서로 순서를 바꿀 수도 있다. 즉, 접촉구(91, 92, 93)의 1차 패턴을 형성한 후에알루미늄-네오디늄층(32, 82, 83)을 식각한 다음에 감광막(PR)의 애싱을 할 수도 있다.As described above, the ashing of the photoresist film PR and the etching of the aluminum-neodynium layers 32, 82, and 83 may be reversed. That is, after forming the primary patterns of the contact holes 91, 92, and 93, the aluminum-neodynium layers 32, 82, and 83 may be etched and then ashed of the photoresist film PR.
도 3e에 나타낸 바와 같이, 애싱을 통하여 노출되어 있는 접촉구(91, 92, 93)의 1차 패턴 주변의 보호막(90)과 그 하부의 게이트 절연막(40)을 다시 한 번 식각함으로써 계단 모양의 접촉구(91, 92, 93)를 형성한다.As shown in FIG. 3E, the protective film 90 around the primary pattern of the contact holes 91, 92, and 93 exposed through ashing and the gate insulating film 40 below are etched once again to form a stepped shape. Contact holes 91, 92, and 93 are formed.
마지막으로 ITO 또는 IZO를 증착하고 제5 사지 식각 공정을 통하여 패터닝하여 화소 전극(110)과 보조 패드(120, 130)를 형성한다.Finally, ITO or IZO is deposited and patterned through a fifth lithography process to form the pixel electrode 110 and the auxiliary pads 120 and 130.
이상과 같이 보호막을 2회에 걸쳐 식각함으로써 접촉구를 계단형으로 형성할 수 있고 이를 통해 접촉구를 통한 화소 전극과 드레인 전극 및 패드와 보조 패드 사이의 전기적 연결의 신뢰성을 향상시킬 수 있다.By etching the protective film twice as described above, the contact hole may be formed in a stepped shape, thereby improving reliability of the electrical connection between the pixel electrode and the drain electrode, and the pad and the auxiliary pad through the contact hole.
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| US10170502B2 (en) | 2016-04-29 | 2019-01-01 | Samsung Display Co., Ltd. | Transistor array panel and manufacturing method thereof |
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| KR100897487B1 (en) * | 2001-06-05 | 2009-05-14 | 엘지디스플레이 주식회사 | Array Substrate of Liquid Crystal Display Device and Fabricating Method Thereof |
| KR100701658B1 (en) * | 2001-06-14 | 2007-03-30 | 비오이 하이디스 테크놀로지 주식회사 | Method of fabricating liquid crystal display |
| KR20030042080A (en) * | 2001-11-21 | 2003-05-28 | 삼성전자주식회사 | A thin film transistor array panel and a manufacturing method of the same |
| KR100864490B1 (en) * | 2002-06-07 | 2008-10-20 | 삼성전자주식회사 | A contact portion of a wires, and thin film transistor substrate including the contact portion |
| TWI272641B (en) * | 2002-07-16 | 2007-02-01 | Semiconductor Energy Lab | Method of manufacturing a semiconductor device |
| KR100906634B1 (en) * | 2003-01-20 | 2009-07-10 | 삼성전자주식회사 | Method Of Manufacturing Thin Film Transistor Of Liquid Crystal Display Device Using The Same |
| US11081507B2 (en) * | 2017-07-12 | 2021-08-03 | Sakai Display Products Corporation | Semiconductor device and method for manufacturing same |
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| US10170502B2 (en) | 2016-04-29 | 2019-01-01 | Samsung Display Co., Ltd. | Transistor array panel and manufacturing method thereof |
| US10741589B2 (en) | 2016-04-29 | 2020-08-11 | Samsung Display Co., Ltd. | Transistor array panel and manufacturing method thereof |
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