KR100318468B1 - Method for forming titanium polycide - Google Patents
Method for forming titanium polycide Download PDFInfo
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- KR100318468B1 KR100318468B1 KR1019980041371A KR19980041371A KR100318468B1 KR 100318468 B1 KR100318468 B1 KR 100318468B1 KR 1019980041371 A KR1019980041371 A KR 1019980041371A KR 19980041371 A KR19980041371 A KR 19980041371A KR 100318468 B1 KR100318468 B1 KR 100318468B1
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- amorphous silicon
- silicon film
- polysilicon film
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- 239000010936 titanium Substances 0.000 title claims abstract description 70
- 229910052719 titanium Inorganic materials 0.000 title claims abstract description 33
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 229920005591 polysilicon Polymers 0.000 claims abstract description 46
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 230000008569 process Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 abstract description 14
- 230000009467 reduction Effects 0.000 abstract description 4
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 206010010144 Completed suicide Diseases 0.000 abstract 1
- 229910008484 TiSi Inorganic materials 0.000 description 32
- 239000004065 semiconductor Substances 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 238000005054 agglomeration Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 캐패시터의 하부전극을 티타늄 폴리사이드로 형성하는 경우 티타늄 실리사이드와 그 하부의 도핑된 폴리실리콘막의 접촉 저항을 감소시킬 수 있으며, 티타늄 실리사이드의 열적 안정성을 증가시킬 수 있는 티타늄 폴리사이드 형성 방법에 관한 것으로, 도핑된 폴리실리콘막 상에 Ti막을 형성하기 전에 폴리실리콘막보다 Ti와 반응성이 우수한 비정질 실리콘막을 형성하고, 비정질 실리콘막 상에 티타늄 막을 형성한 후 열처리하여 티타늄 실리사이드를 형성하는 것을 특징으로 한다. 이에 의해 티타늄실리사이드 하부 폴리실리콘막 내의 불순물 농도 감소 정도를 줄일 수 있고, 티타늄 실리사이드의 열적안정성을 향상시킬 수 있어, 캐패시터의 하부전 극을 티타늄 폴리사이드로 형성하는 경우 티타늄 실리사이드와 그 하부의 도핑된 폴리실리콘막의 접촉 저항과 누설전류를 감소시킬 수 있으며, Ta2O5, BST 및 PZT 등과 같은 고유전 물질을 유전막으로 사용하는 캐패시터의 하부전극을 본 발명에 따른 티타늄 폴리사이드 형성 방법으로 형성할 경우 소자의 특성을 향상시킬 수 있다.The present invention relates to a titanium polycide forming method capable of reducing contact resistance between a titanium silicide and a doped polysilicon film beneath the titanium silicide and increasing the thermal stability of the titanium silicide when the lower electrode of the capacitor is formed of titanium polycide An amorphous silicon film which is more reactive with Ti than a polysilicon film is formed on the doped polysilicon film before the Ti film is formed, a titanium film is formed on the amorphous silicon film, and then a heat treatment is performed to form titanium suicide do. As a result, the degree of reduction of the impurity concentration in the titanium silicide lower polysilicon film can be reduced and the thermal stability of the titanium silicide can be improved. In the case where the lower electrode of the capacitor is formed of titanium polycide, the titanium silicide and the doped The contact resistance and leakage current of the polysilicon film can be reduced and the lower electrode of the capacitor using the high dielectric material such as Ta 2 O 5 , BST and PZT as the dielectric film is formed by the titanium polycide formation method according to the present invention The characteristics of the device can be improved.
Description
본 발명은 반도체 장치 제조 분야에 관한 것으로, 특히 티타늄 실리사이드와그 하부의 도핑된 폴리실리콘막의 접촉 저항을 감소시킬 수 있으며, 티타늄 실리사이드의 열적 안정성을 증가시킬 수 있는 티타늄 폴리사이드 형성 방법에 관한 것이다.Field of the Invention [0002] The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method of forming a titanium polycide capable of reducing contact resistance between a titanium silicide and a doped polysilicon film below the titanium silicide and increasing the thermal stability of the titanium silicide.
256M DRAM(dynamic random access memory) 이상의 집적도를 가지는 반도체 기억 소자에서 캐패시터의 정전용량을 증가시키기 위하여 유전막으로 탄탈륨산화막 (Ta2O5)을 사용한다. 정전용량을 더욱 증가시키기 위하여 유전막을 얇게 형성하여야 하는데, 캐패시터의 하부전극을 폴리실리콘막으로 형성하고, 폴리실리콘막 상에 30 Å 이하의 두께로 Ta2O5막을 형성할 경우 캐패시터의 누설전류 특성이 열화되어 실제 소자에 적용하기 어렵기 때문에 캐패시터의 하부전극을 TiN, WN, TiSi2, W 등의 금속막으로 형성하는 기술이 제안되고 있다. 이 중에서 TiSi2막은 비교적 열적 안정성이 뛰어나기 때문에 Ta2O5막을 유전막으로 사용하는 캐패시터의 하부전극으로 적당하다.A tantalum oxide (Ta 2 O 5 ) film is used as a dielectric film to increase the capacitance of a capacitor in a semiconductor memory device having an integration degree of 256M dynamic random access memory (DRAM) or more. When the lower electrode of the capacitor is formed of a polysilicon film and the Ta 2 O 5 film is formed on the polysilicon film to a thickness of 30 Å or less, the leakage current characteristic of the capacitor Is difficult to apply to practical devices, a technique has been proposed in which a lower electrode of a capacitor is formed of a metal film of TiN, WN, TiSi 2 , W or the like. Among these, the TiSi 2 film is suitable as a lower electrode of a capacitor using a Ta 2 O 5 film as a dielectric film because of its excellent thermal stability.
그러나, TiSi2막 형성은 도핑된 폴리실리콘막 상에 Ti막을 증착하고 실리사이드(silicide) 형성을 위한 급속열처리(rapid thermal annealing)를 실시하여 C-49 상의 TiSi2막을 형성한 후, C-49 상의 TiSi2막을 저항값이 작은 C-54 상으로 상전이 시키기 위하여 후속 열처리 공정을 실시하는 과정으로 이루어지는데, 열처리 단계에서 폴리실리콘막 내에 도핑되었던 인(P) 등의 불순물이 Ti막으로 확산되어 실리사이드 형성 후 도1에서 보이는 바와 같이 폴리실리콘막 내의 불순물 농도가TiSi2막과 폴리실리콘막의 계면에서 비교적 많이 감소한다. 이로 인해 폴리실리콘막과 TiSi2막의 접촉저항 증가에 따른 전하저장전극의 저항이 증가로 소자의 속도가 감소하는 문제점이 있다.However, TiSi 2 film formation is performed by depositing a Ti film on a doped polysilicon film and forming a TiSi 2 film on C-49 by performing rapid thermal annealing for silicide formation, And a subsequent heat treatment process is performed to transition the TiSi 2 film to a C-54 phase having a small resistance value. In the heat treatment step, impurities such as phosphorus (P) doped in the polysilicon film are diffused into the Ti film to form silicide As shown in FIG. 1, the impurity concentration in the polysilicon film is relatively decreased at the interface between the TiSi 2 film and the polysilicon film. As a result, the resistance of the charge storage electrode increases with an increase in the contact resistance between the polysilicon film and the TiSi 2 film.
또한, TiSi2막 내에 도핑 농도가 높아질 경우 TiSi2막의 열적 안정도가 저하되고 TiSi2막의 응집(agglomeration) 현상이 발생하여 TiSi2막 하부의 폴리실리콘막이 노출되고 캐패시터의 누설전류가 증가하는 문제점이 있다.Further, when the higher the doping concentration in the TiSi 2 layer has a problem of lowering a TiSi 2 film thermal stability and TiSi 2 film cohesion (agglomeration) it happens to TiSi 2 in the film the lower polysilicon film is exposed to increase the leakage current of the capacitor .
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 캐패시터의 하부전극을 티타늄 폴리사이드로 형성하는 경우 티타늄 실리사이드와 그 하부의 도핑된 폴리실리콘막의 접촉 저항을 감소시킬 수 있으며, 티타늄 실리사이드의 열적 안정성을 증가시킬 수 있는 티타늄 폴리사이드 형성 방법을 제공하는데 그 목적이 있다.In order to solve the above-described problems, the present invention can reduce the contact resistance between the titanium silicide and the underlying doped polysilicon film when the lower electrode of the capacitor is formed of titanium polycide, and can improve the thermal stability of the titanium silicide The present invention provides a method for forming a titanium polycide.
도1은 종래 기술에 따라 형성된 티타늄 폴리사이드에서 폴리실리콘막의 불순물 농도 분포를 보이는 그래프,1 is a graph showing the impurity concentration distribution of a polysilicon film in a titanium polycide formed according to the prior art,
도2a 내지 도2c는 본 발명의 일실시예에 따른 티타늄 폴리사이드 형성 공정 단면도,FIGS. 2A to 2C are cross-sectional views illustrating a process of forming a titanium polycide according to an embodiment of the present invention.
도3은 본 발명에 따라 형성된 티타늄 폴리사이드에서 폴리실리콘막의 불순물 농도 분포를 보이는 그래프,3 is a graph showing the impurity concentration distribution of the polysilicon film in the titanium polycide formed according to the present invention,
도4a 내지 도4c는 본 발명의 일실시예에 따른 티타늄 폴리사이드 형성 공정 단면도.4A to 4C are cross-sectional views illustrating a process of forming a titanium polycide according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 도면 부호의 설명Description of Reference Numerals to Main Parts of the Drawings
10, 20: 반도체 기판 11, 21: 폴리실리콘막10, 20: semiconductor substrate 11, 21: polysilicon film
12, 22: 비정질 실리콘막 13, 23: Ti막12, 22: amorphous silicon film 13, 23: Ti film
14, 24: TiSi2막14, 24: TiSi 2 film
상기 목적을 달성하기 위한 본 발명은 기판 상에 도핑된 폴리실리콘막을 형성하는 제1 단계; 상기 폴리실리콘막 상에 비정질 실리콘막을 형성하는 제2 단계; 상기 비정질 실리콘막 상에 티타늄막을 형성하는 제3 단계; 및 상기 제3 단계가 완료된 전체 구조를 열처리하여 상기 비정질 실리콘막과 상기 티타늄막을 반응시켜 티타늄 실리사이드를 형성하는 제4 단계를 포함하는 티타늄 폴리사이드 형성 방법을 제공한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a doped polysilicon film on a substrate; A second step of forming an amorphous silicon film on the polysilicon film; A third step of forming a titanium film on the amorphous silicon film; And a fourth step of thermally treating the entire structure in which the third step is completed to react the amorphous silicon film and the titanium film to form titanium silicide.
본 발명은 도핑된 폴리실리콘막 상에 비정질 실리콘막 및 Ti막을 차례로 증착한 후 후속 열처리 공정을 실시하여 폴리실리콘막 내의 불순물 감소를 최소화화는 방법이다.The present invention is a method for minimizing impurity reduction in a polysilicon film by sequentially depositing an amorphous silicon film and a Ti film on a doped polysilicon film and then performing a subsequent heat treatment process.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.
도2a 내지 도2c는 본 발명의 일실시예에 따른 티타늄 폴리사이드 형성 공정 단면도이다.2A to 2C are cross-sectional views illustrating a process of forming a titanium polycide according to an embodiment of the present invention.
도2a는 반도체 기판(10) 상에 600 ℃ 이상의 온도에서 저압화학기상증착법 (low pressure chemical vapor deposition, LPCVD)으로 도핑된 폴리실리콘막(11)을 형성하고, 폴리실리콘막(11) 상에 100 Å 내지 300 Å 두께의 도핑된 비정질 실리콘막(12)을 형성한 후, 비정질 실리콘막(12) 상에 화학기상증착법으로 150 Å 내지 400 Å 두께의 비정질 Ti막(13)을 차례로 형성한 것을 보인다.2A is a plan view of a polysilicon film 11 doped with a low pressure chemical vapor deposition (LPCVD) at a temperature of 600 캜 or higher on a semiconductor substrate 10, A doped amorphous silicon film 12 having a thickness of 300 to 300 angstroms is formed and an amorphous Ti film 13 having a thickness of 150 ANGSTROM to 400 ANGSTROM is sequentially formed on the amorphous silicon film 12 by chemical vapor deposition .
이와 같이 폴리실리콘막(11) 상에 폴리실리콘막보다 원자간 결합력이 작아 Ti와 보다 용이하게 반응할 수 있는 비정질 실리콘막(12)을 형성하여, 이후의 열처리 공정에서 비정질 실리콘막(12)과 Ti막(13)의 반응을 향상시킨다. 또한, 이후의 TiSi2형성을 위한 열처리 공정에서 Ti막(13)으로 확산되는 불순물의 양을 감소시키고, 비정질 실리콘막(12) 하부의 폴리실리콘막(11)과 Ti막(13)의 반응을 억제하기 위하여, 상기 폴리실리콘막(11)의 불순물 농도는 5×1019원자/㎤ 내지 3×1021원자/㎤가 되도록 하고, 비정질 실리콘막(12)의 불순물 농도는 폴리실리콘막(11)의 농도보다 낮은 5×1010원자/㎤ 내지 2×1019원자/㎤가 되도록 한다.As described above, the amorphous silicon film 12 is formed on the polysilicon film 11 so that the interatomic bonding force is smaller than that of the polysilicon film, so that the amorphous silicon film 12 can react with Ti more easily. Thereby improving the reaction of the Ti film 13. The amount of impurities diffused into the Ti film 13 in the subsequent heat treatment for TiSi 2 formation is reduced and the reaction between the polysilicon film 11 and the Ti film 13 under the amorphous silicon film 12 is suppressed The impurity concentration of the polysilicon film 11 is set to be 5 x 10 19 atoms / cm 3 to 3 x 10 21 atoms / cm 3 and the impurity concentration of the amorphous silicon film 12 is set to be the polysilicon film 11, of so that the lower 5 × 10 10 atoms / ㎤ to 2 × 10 19 atoms / ㎤ than the concentration.
또한, 상기 비정질 실리콘막(12)은 SiH4가스 또는 Si2H6가스 및 PH3가스를 이용하여 저압화학기상증착법으로 530 ℃ 이하의 온도에서 형성하며, 상기 비정질 Ti막(13)은 TiCl4가스를 450 ℃ 이하의 온도에서 열분해하여 형성한다.The amorphous silicon film 12 is formed using SiH 4 gas, Si 2 H 6 gas, and PH 3 gas at a temperature of 530 ° C. or lower by a low-pressure chemical vapor deposition method. The amorphous Ti film 13 is formed of TiCl 4 Gas is formed by pyrolysis at a temperature of 450 DEG C or less.
도2b는 도2a와 같이 비정질 Ti막(13)을 형성한 후, 전체구조를 N2분위기에서 675 ℃ 내지 700 ℃ 온도 조건으로 20초간 급속열처리하여 비정질 실리콘막(12)과 비정질 Ti막(13)이 반응되도록 함으로써 C-49 상의 TiSi2막(14)을 형성한 것을 보이고 있다. 이때, Si과 반응하지 않은 Ti막(13)의 일부가 TiSi2막(14) 상에 잔류한다.2A, after the amorphous Ti film 13 is formed as shown in FIG. 2A, the entire structure is subjected to rapid thermal annealing for 20 seconds at a temperature of 675 ° C. to 700 ° C. in an N 2 atmosphere to form an amorphous silicon film 12 and an amorphous Ti film 13 ) To react to form a TiSi 2 film 14 on the C-49. At this time, a part of the Ti film 13 which has not reacted with Si remains on the TiSi 2 film 14.
도2c는 TiSi2막(14) 형성 후 잔류한 Ti막(13)을 NH4OH, H2O2및 H2O가 NH4OH:H2O2:H2O=1:1:5의 비율로 혼합된 용액으로 제거하여 TiSi2막(14)을 노출시킨 상태를 보이고 있다.2C shows a case where the Ti film 13 remaining after forming the TiSi 2 film 14 is replaced with NH 4 OH, H 2 O 2, and H 2 O in a ratio of NH 4 OH: H 2 O 2 : H 2 O = 1: 1: 5 To remove the TiSi 2 film 14 from the mixed solution to expose the TiSi 2 film 14.
도3은 전술한 바와 같이 이루어지는 본 발명의 일실시예에 따라 티타늄 폴리사이드를 형성한 후, 폴리실리콘막(11) 내의 불순물 분포를 측정한 결과이다. 도1과 도3의 비교를 통하여, 도핑된 폴리실리콘막 상에 Ti막을 직접 형성하고 열처리하여 TiSi2막을 형성하는 종래기술보다 도핑된 폴리실리콘막 상에 비정질 실리콘막을 형성하고, Ti막을 형성한 후 열처리하여 TiSi2막을 형성하는 본 발명의 경우에 폴리실리콘막 내의 불순물 농도 감소 정도가 줄어든다는 것을 알 수 있다.3 is a result of measuring the distribution of impurities in the polysilicon film 11 after the formation of the titanium polycide according to an embodiment of the present invention as described above. 1 and 3, the amorphous silicon film is formed on the doped polysilicon film and the Ti film is formed on the doped polysilicon film by forming the Ti film directly on the doped polysilicon film and then performing the heat treatment to form the TiSi 2 film It can be seen that the degree of reduction of the impurity concentration in the polysilicon film is reduced in the case of the present invention in which the TiSi 2 film is formed by heat treatment.
전술한 본 발명의 일실시예에서 상기 비정질 실리콘막(12) 상에 상기 비정질 Ti막(13)을 대신하여 다결정 Ti막을 형성할 수도 있다. 다결정 Ti막은 TiCl4가스를 사용하여 500 ℃ 내지 600 ℃의 온도 및 300 mTorr 이하의 압력에서 증착하며, 이 경우에는 Ti막 증착과 동시에 비정질 실리콘의 실리콘과 Ti가 반응하여 TixSiy가 형성된다.In one embodiment of the present invention, a polycrystalline Ti film may be formed on the amorphous silicon film 12 instead of the amorphous Ti film 13. The polycrystalline Ti film is deposited using TiCl 4 gas at a temperature of 500 ° C to 600 ° C and a pressure of 300 mTorr or less. In this case, Si and Ti of amorphous silicon react with Ti film to form Ti x Si y .
이하, 도4a 내지 도4b를 참조하여 본 발명의 다른 실시예에 따른 티타늄 폴리사이드 형성 방법을 설명한다.Hereinafter, a method of forming a titanium polycide according to another embodiment of the present invention will be described with reference to FIGS. 4A to 4B.
먼저, 도4a에 도시한 바와 같이 반도체 기판(20) 상에 도핑된 폴리실리콘막 (21)을 형성하고, 상기 폴리실리콘막(21) 상에 폴리실리콘막보다 Ti와의 반응성이 뛰어난 비도핑 비정질 실리콘막(22)을 형성하고, 상기 비정질 실리콘막(22) 상에 Ti막(23)을 형성한다.First, as shown in FIG. 4A, a doped polysilicon film 21 is formed on a semiconductor substrate 20, and a non-doped amorphous silicon film 21, which is superior in reactivity with Ti to the polysilicon film 21, And a Ti film 23 is formed on the amorphous silicon film 22. Then,
일 예로, 상기 폴리실리콘막은 캐패시터의 하부전극 형성을 위하여 캐패시터의 형태에 따라 실린더(cylinder)형, 핀(fin)형, 단순 블록(block)형 등의 구조로 형성된 것일 수 있다.For example, the polysilicon film may be formed of a cylinder, a fin, a simple block or the like depending on the shape of the capacitor for forming the lower electrode of the capacitor.
상기 비정질 실리콘막(22)의 두께는 100 Å 내지 300 Å 이며, 비정질 실리콘막의 두께는 이후에 비정질 실리콘막 상에 형성될 Ti막과 반응하여 형성되는 TiSi2의 두께와 폴리실리콘막으로부터 불순물이 확산되는 정도에 의해 결정된다.The amorphous silicon film 22 has a thickness of 100 Å to 300 Å. The thickness of the amorphous silicon film is determined by the thickness of TiSi 2 formed by reaction with the Ti film to be formed later on the amorphous silicon film, Is determined by the degree to which
또한, Ti막(23)은 150 Å 내지 400 Å 두께로 형성한다. 일반적으로 Ti막은 화학기상증착법이나 스퍼터링(sputtering) 방법으로 형성된다. 화학기상증착법은 TiCl4가스를 열분해하여 Ti막을 형성하는 것으로 스텝커버리지(step coverage) 특성이 우수하고, 스퍼터링 방법은 우수한 스텝 커버리지 특성이 요구되지 않는 단순한 블록 형태의 구조 상에 Ti막을 형성할 때 이용된다.Also, the Ti film 23 is formed to a thickness of 150 ANGSTROM to 400 ANGSTROM. Generally, a Ti film is formed by a chemical vapor deposition method or a sputtering method. The chemical vapor deposition method is used to form a Ti film by thermally decomposing TiCl 4 gas to form a Ti film. The step coverage is excellent. The sputtering method is used when forming a Ti film on a simple block type structure requiring no excellent step coverage characteristics. do.
다음으로, 도4b에 도시한 바와 같이 Ti막(23) 형성이 완료된 후에는 675 ℃ 내지 700 ℃ 온도 조건으로 20초간 급속열처리하여 비정질 실리콘막과 Ti막이 반응하도록 함으로써 C-49 상을 갖는 TiSi2막(24)을 형성한다. 이때, Ti와 반응하지 않은 비도핑 비정질 실리콘막(22)의 일부는 폴리실리콘막(21)과 TiSi2막(22) 사이에 그대로 잔류하고, Si과 반응하지 않은 Ti막(23)의 일부는 TiSi2막(24) 상에 잔류한다.Next, as shown in FIG. 4B, after the formation of the Ti film 23 is completed, the amorphous silicon film and the Ti film are allowed to react with each other by rapid thermal annealing for 20 seconds at a temperature of 675 to 700 ° C to form TiSi 2 Film 24 is formed. At this time, a part of the undoped amorphous silicon film 22 which has not reacted with Ti remains as it is between the polysilicon film 21 and the TiSi 2 film 22, and a part of the Ti film 23 which has not reacted with Si And remains on the TiSi 2 film 24.
다음으로, 열처리 후 실리콘과 반응하지 않은 Ti막(23)을 NH4OH, H2O2및 H2O가 NH4OH:H2O2:H2O=1:1:5의 비율로 혼합된 용액으로 제거하여 TiSi2막(24)을 노출시킨다.Next, the Ti film 23, which has not reacted with silicon after the heat treatment, is oxidized with NH 4 OH, H 2 O 2 and H 2 O in a ratio of NH 4 OH: H 2 O 2 : H 2 O = 1: 1: The mixed solution is removed to expose the TiSi 2 film (24).
다음으로, C-49 상의 TiSi2(24)를 저항값이 낮은 C-54상으로 상전이 시키기 위하여 800 ℃ 내지 850 ℃ 온도, N2분위기에서 열처리를 실시한다. 이때, 폴리실리콘막(21) 내에 도핑되었던 인(P) 등의 불순물이 TiSi2막(24)으로 확산되면서 재분포되어 폴리실리콘막(21) 내의 불순물 농도가 감소하는 현상이 발생하는데, 폴리실리콘막(21)과 TiSi2막(24) 사이에 비도핑 비정질 실리콘막(22)을 소정 두께로 잔류시켜 불순물의 확산장벽(diffusion barrier) 역할을 하도록 하여 인 등의 불순물이 TiSi2막(24)으로 확산됨으로 인한 열적안정성 저하를 방지한다. 이에 의해 TiSi2막 (24)의 응집(agglomeration)현상 발생에 따른 누설전류의 증가를 방지할 수 있다.Next, the TiSi 2 (24) on C-49 is subjected to heat treatment in a N 2 atmosphere at a temperature of 800 ° C to 850 ° C in order to cause the phase transition to a C-54 phase having a low resistance value. At this time, impurities such as phosphorus (P) which have been doped in the polysilicon film 21 are diffused into the TiSi 2 film 24 and redistributed to cause the impurity concentration in the polysilicon film 21 to decrease. film 21 and TiSi impurities such as phosphorus and to the remaining non-doped amorphous silicon film 22, between the second film 24 to a predetermined thickness to the diffusion barrier of the impurity (diffusion barrier) serves TiSi 2 film 24 Thereby preventing deterioration of thermal stability. As a result, an increase in leakage current due to the agglomeration of the TiSi 2 film 24 can be prevented.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be apparent to those of ordinary skill in the art.
상기와 같이 이루어지는 본 발명은 TiSi2막 하부 폴리실리콘막 내의 불순물 농도 감소 정도를 줄일 수 있고, TiSi2막의 열적안정성을 향상시킬 수 있어, 캐패시터의 하부전극을 티타늄 폴리사이드로 형성하는 경우 티타늄 실리사이드와 그 하부의 도핑된 폴리실리콘막의 접촉 저항과 누설전류를 감소시킬 수 있다. 이에 의해, Ta2O5, BST 및 PZT 등과 같은 고유전 물질을 유전막으로 사용하는 캐패시터의 하부전극을 본 발명에 따른 티타늄 폴리사이드 형성 방법으로 형성할 경우 소자의 특성을 향상시킬 수 있다.The present invention composed as described above can reduce a reduction in the impurity concentration level in the TiSi 2 film underlying polysilicon film, TiSi can be 2 film improves the thermal stability, in the case of forming the lower electrode of the capacitor to a titanium polycide titanium silicide and The contact resistance and the leakage current of the doped polysilicon film below it can be reduced. Accordingly, when a lower electrode of a capacitor using a high dielectric material such as Ta 2 O 5 , BST and PZT as a dielectric film is formed by the titanium polycide formation method according to the present invention, the characteristics of the device can be improved.
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