KR100314809B1 - A method for forming damascene gate of semiconductor device - Google Patents
A method for forming damascene gate of semiconductor device Download PDFInfo
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- KR100314809B1 KR100314809B1 KR1019990065881A KR19990065881A KR100314809B1 KR 100314809 B1 KR100314809 B1 KR 100314809B1 KR 1019990065881 A KR1019990065881 A KR 1019990065881A KR 19990065881 A KR19990065881 A KR 19990065881A KR 100314809 B1 KR100314809 B1 KR 100314809B1
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 46
- 238000005468 ion implantation Methods 0.000 description 9
- 239000010410 layer Substances 0.000 description 9
- 239000007789 gas Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005336 cracking Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000003389 potentiating effect Effects 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
Abstract
본 발명은 반도체 제조 기술에 관한 것으로, 특히 대머신(damascene) 게이트 형성방법에 관한 것이며 대머신 게이트 내부의 갈라짐이나 보이드 발생을 방지할 수 있는 대머신 게이트 형성방법을 제공하는데 그 목적이 있다. 상기 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 작은 선폭의 게이트용 홈과 큰 선폭의 게이트용 홈을 포함하는 하부 구조를 형성하는 제1 단계; 원자층증착법으로 전체 구조 상부에 제1 금속막을 증착하여 상기 작은 선폭의 게이트용 홈을 완전히 매립하고, 상기 큰 선폭의 게이트용 홈의 일부를 매립하는 제2 단계; 화학기상증착법으로 상기 제1 금속막 상부에 제2 금속막을 증착하여 상기 큰 선폭의 게이트용 홈을 완전히 매립하는 제3 단계; 및 상기 제2 금속막 및 상기 제1 금속막을 리세싱하여 상기 제1 및 제2 금속막이 상기 작은 선폭의 게이트용 홈과 상기 큰 선폭의 게이트용 홈내에 잔류되도록 하는 제4 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to a damascene gate formation method, and to provide a damascene gate formation method capable of preventing cracks and voids in a damascene gate. According to an aspect of the present invention, there is provided a semiconductor device comprising: a first step of forming a lower structure including a gate having a small line width and a groove having a large line width on a semiconductor substrate; A second step of depositing a first metal film over the entire structure by atomic layer deposition to completely fill the gate grooves having a small line width, and filling a portion of the gate grooves having a large line width; Depositing a second metal film on the first metal film by chemical vapor deposition to completely fill the groove for the gate having a large line width; And a fourth step of recessing the second metal film and the first metal film so that the first and second metal films remain in the gate groove of the small line width and the gate groove of the large line width.
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 대머신(damascene) 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for forming a damascene gate.
일반적으로, 모스 트랜지스터의 게이트 전극을 형성함에 있어서, 도핑된 폴리실리콘(doped polysilicon)을 사용해 왔다. 그러나, 반도체 소자의 고집적화에 따라 소자를 이루는 패턴이 미세화 되고 있으며, 최근에는 0.15㎛ 선폭 이하까지 미세화가 진행되고 있다. 이에 따라, 통상적인 전극 형성시 사용되어 온 도핑된 폴리실리콘은 그 자체의 높은 비저항 특성으로 인하여 지연 시간이 길기 때문에 빠른 동작을 요구하는 반도체 소자에 적용하기가 어려운 문제점이 있었다.In general, doped polysilicon has been used in forming the gate electrode of the MOS transistor. However, with the higher integration of semiconductor devices, the patterns constituting the devices have been miniaturized, and in recent years, miniaturization has been progressed to 0.15 µm or less. Accordingly, the doped polysilicon used in conventional electrode formation has a problem in that it is difficult to be applied to a semiconductor device requiring fast operation because of a long delay time due to its high resistivity.
이러한 문제점은 반도체 장치의 고집적화에 따라 더욱 심각한 문제로 대두되고 있으며, 이를 개선하기 위하여 1기가 디램(DRAM)급 이상의 반도체 소자 제조시 전극 재료로서 비저항이 낮은 텅스텐(W)과 같은 금속계 물질의 적용이 유력시되고 있다.This problem is becoming more serious due to the high integration of semiconductor devices. In order to improve this problem, the application of metal-based materials such as tungsten (W), which has low specific resistance, is an electrode material in the manufacture of semiconductor devices of 1 Gigabit DRAM or more. Being potent.
그러나, 이와 같은 비저항이 낮은 금속계 물질을 사용하여 게이트 전극을 형성할 경우에는 다음과 같은 근본적인 문제를 안고 있다. 게이트 산화막(gate oxide) 상에 금속계 물질막을 포함하는 게이트 전극 물질을 증착하고, 게이트 전극 마스크를 이용하여 이들을 패터닝할 때 게이트 산화막의 열화가 발생하는데, 이를 보상하기 위하여 게이트 구조를 재산화시키게 된다. 그런데, 게이트 재산화 공정시 금속계 물질막의 이상산화 현상이 유발되어 부도체를 형성하고 패터닝된 게이트 전극의 프로파일을 열화시키는 문제점이 있었다.However, when forming a gate electrode using such a low resistivity metal-based material has the following fundamental problems. Degradation of the gate oxide film occurs when depositing a gate electrode material including a metal-based material film on the gate oxide and patterning the gate electrode material by using a gate electrode mask, thereby recalculating the gate structure. However, in the gate reoxidation process, an abnormal oxidation phenomenon of the metal-based material film is induced to form an insulator and deteriorate the profile of the patterned gate electrode.
대머신 게이트 기술은 이러한 문제점들을 해결할 수 있는 대안으로 부각되고있다. 또한, 대머신 게이트에는 고유전율 박막을 게이트 절연막으로 적용할 수 있어 향후 차세대 반도체 소자에의 적용이 유망하다.Alternative machine gate technology is emerging as an alternative to solve these problems. In addition, since the high dielectric constant thin film can be applied as a gate insulating film to the large-machine gate, it is promising to be applied to the next generation semiconductor device in the future.
첨부된 도면 도 1a 내지 도 1g는 종래기술에 따른 대머신 게이트형 모스 트랜지스터 제조 공정도로서, 더미(dummy) 게이트를 사용한 공정을 도시하고 있다.1A to 1G are diagrams illustrating a process of manufacturing a damascene gate type MOS transistor according to the prior art, and illustrating a process using a dummy gate.
종래기술에 따른 대머신 게이트형 모스 트랜지스터 제조 공정은, 우선 도 1a에 도시된 바와 같이 실리콘 기판(10) 상에 열산화막(11) 및 폴리실리콘막을 증착하고, 폴리실리콘막을 패터닝하여 더미 게이트(12)를 형성한다.In the process of manufacturing a large-scale gate type MOS transistor according to the prior art, first, as shown in FIG. 1A, a thermal oxide film 11 and a polysilicon film are deposited on a silicon substrate 10, and a polysilicon film is patterned to form a dummy gate 12. ).
다음으로, 도 1b에 도시된 바와 같이 더미 게이트(12) 패턴 형성 시 더미 게이트(12) 및 열산화막(11)이 받은 손상을 회복시키고, LDD(Lightly Doped Drain) 이온주입 시 스크린 산화막 역할을 수행할 수 있도록 하기 위하여 LDD 산화공정을 실시한 후 LDD 이온주입(n-이온주입) 및 열처리를 실시한다. 도면부호 '13'은 LDD 산화공정에 의해 더미 게이트(12) 표면에 형성된 열산화막을 나타낸 것이다.Next, as shown in FIG. 1B, the damage received by the dummy gate 12 and the thermal oxide layer 11 when the dummy gate 12 pattern is formed is restored, and the screen oxide layer serves as the LDD (Lightly Doped Drain) ion implantation. LDD ion implantation (n - ion implantation) and heat treatment are performed after the LDD oxidation process. Reference numeral 13 denotes a thermal oxide film formed on the surface of the dummy gate 12 by an LDD oxidation process.
다음으로, 도 1c에 도시된 바와 같이 더미 게이트(12) 측벽에 질화막 스페이서(14)을 형성하고, 소오스/드레인 형성을 위한 고농도 이온주입(n+이온주입) 및 열처리를 실시한다.Next, as shown in FIG. 1C, a nitride film spacer 14 is formed on the sidewalls of the dummy gate 12, and high concentration ion implantation (n + ion implantation) and heat treatment are performed for source / drain formation.
계속하여, 도 1d에 도시된 바와 같이 전체 구조 상부에 층간절연막(15)를 증착하고, 화학적·기계적 연마(Chemical Mechanical Polishing, CMP) 공정을 실시하여 더미 게이트(12)가 노출될 정도로 층간절연막(15)을 평탄화한다.Subsequently, as illustrated in FIG. 1D, an interlayer insulating film 15 is deposited on the entire structure, and a chemical mechanical polishing (CMP) process is performed to expose the dummy gate 12. Flatten 15).
이어서, 도 1e에 도시된 바와 같이 더미 게이트(12)를 건식식각법 또는 습식식각법을 사용하여 선택적으로 제거한다.Subsequently, the dummy gate 12 is selectively removed using a dry etching method or a wet etching method as shown in FIG. 1E.
계속하여, 도 1f에 도시된 바와 같이 노출된 열산화막(11, 13)을 제거한 후 노출된 실리콘 기판(10) 표면에 게이트 절연막(16)을 형성하고, 이어서 게이트 전극용 금속막(17)을 차례로 증착한다. 이때, 게이트 전극용 금속막(17)은 텅스텐(W)을 화학적 기상 증착(Chemical Vapor Deposition, CVD)법으로 증착한다.Subsequently, as shown in FIG. 1F, the exposed thermal oxide films 11 and 13 are removed, and then a gate insulating film 16 is formed on the exposed silicon substrate 10, and then the metal film 17 for the gate electrode is formed. Deposition in turn. At this time, the gate electrode metal film 17 deposits tungsten (W) by chemical vapor deposition (CVD).
다음으로, 도 1g에 도시된 바와 같이 층간절연막(15)이 노출될 정도로 CMP 공정을 실시하여 평탄화를 이룬다.Next, as shown in FIG. 1G, the CMP process is performed to the extent that the interlayer insulating film 15 is exposed to planarization.
그러나, 상기와 같이 종래의 더미 게이트 형성공정은 게이트 전극용 금속막(17) 증착 시 더미 게이트(12)가 형성되어 있던 게이트 전극용 홈에 게이트 전극용 금속막(17)이 완전히 매립되지 못하고, 갈라짐(seam, A)이나 보이드(void, B)가 발생한다.(도 1f 참조)However, in the conventional dummy gate forming process as described above, the gate electrode metal film 17 is not completely embedded in the gate electrode groove in which the dummy gate 12 was formed when the gate electrode metal film 17 was deposited. Cracks (A) or voids (B) occur (see FIG. 1F).
이러한 갈라짐(A)이나 보이드(B)는 대머신 게이트용 홈이 0.07㎛ 이하의 선폭과 1500 ~4000Å 정도의 깊이로 단차비가 증가하는 것에 기인하는 것이다.Such cracks (A) and voids (B) are caused by the step difference ratio being increased to a line width of 0.07 µm or less and a depth of about 1500 to 4000 mm in the groove for the gate of the large machine.
이와 같은 갈라짐과 보이드가 발생하게 되면, 후속 CMP 공정 시 CMP용 캐미컬(chemical)의 침투에 의해 갈라짐(A)과 보이드(B)가 더욱 더 커져 게이트 특성의 열화가 심화되는 문제점이 있었다.(도 1g 참조)When such cracks and voids occur, cracks (A) and voids (B) become larger due to infiltration of CMP chemicals during the subsequent CMP process, resulting in a worsening of gate characteristics. 1G)
본 발명은 대머신 게이트 내부의 갈라짐이나 보이드 발생을 방지할 수 있는 대머신 게이트 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a damascene gate, which can prevent cracking or voiding inside the damascene gate.
도 1a 내지 도 1g는 종래기술에 따른 대머신 게이트형 모스 트랜지스터 제조 공정도.1A to 1G are diagrams illustrating a process of manufacturing a gate-type MOS transistor according to the prior art.
도 2a 내지 도 2i는 본 발명의 일실시예에 따른 대머신 게이트형 모스 트랜지스터 제조 공정도.2A to 2I are process diagrams illustrating a manufacturing gate type MOS transistor according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 간단한 설명* Brief description of symbols for the main parts of the drawings
20 : 실리콘 기판 21 : 열 산화막20 silicon substrate 21 thermal oxide film
24 : 절연막 스페이서 25 : 층간절연막24 insulating film spacer 25 interlayer insulating film
27 : 제1텅스텐막 28 : 제2텅스텐막27: first tungsten film 28: second tungsten film
상기 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 작은 선폭의 게이트용 홈과 큰 선폭의 게이트용 홈을 포함하는 하부 구조를 형성하는 제1 단계; 원자층증착법으로 전체 구조 상부에 제1 금속막을 증착하여 상기 작은 선폭의 게이트용 홈을 완전히 매립하고, 상기 큰 선폭의 게이트용 홈의 일부를 매립하는 제2 단계; 화학기상증착법으로 상기 제1 금속막 상부에 제2 금속막을 증착하여 상기 큰 선폭의 게이트용 홈을 완전히 매립하는 제3 단계; 및 상기 제2 금속막 및 상기 제1 금속막을 리세싱하여 상기 제1 및 제2 금속막이 상기 작은 선폭의 게이트용 홈과 상기 큰 선폭의 게이트용 홈내에 잔류되도록 하는 제4 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a semiconductor device comprising: a first step of forming a lower structure including a gate having a small line width and a groove having a large line width on a semiconductor substrate; A second step of depositing a first metal film over the entire structure by atomic layer deposition to completely fill the gate grooves having a small line width, and filling a portion of the gate grooves having a large line width; Depositing a second metal film on the first metal film by chemical vapor deposition to completely fill the groove for the gate having a large line width; And a fourth step of recessing the second metal film and the first metal film so that the first and second metal films remain in the gate groove of the small line width and the gate groove of the large line width.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
첨부된 도면 도 2a 내지 도 2i는 본 발명의 일실시예에 따른 대머신 게이트형 모스 트랜지스터 제조 공정도로서, 더미(dummy) 게이트를 사용한 공정을 일례로 하였다.2A to 2I are manufacturing process diagrams of a damascene gate type MOS transistor according to an exemplary embodiment of the present invention, and a process using a dummy gate is used as an example.
본 실시예는 먼저, 도 2a에 도시된 바와 같이 실리콘 기판(20) 상에 열산화막(21)을 형성한 후 폴리실리콘막을 증착하고, 이를 패터닝하여 더미 게이트(22) 를 형성한다. 이때, 더미 게이트(22)는 그 선폭이 큰 것과 작은 것이 형성된다. 이는 메모리셀 영역과 주변회로 영역의 트랜지스터 크기가 다른데 기인하는 것이다.In the present embodiment, first, as shown in FIG. 2A, a thermal oxide film 21 is formed on a silicon substrate 20, and then a polysilicon film is deposited and patterned to form a dummy gate 22. At this time, the dummy gate 22 has a large line width and a small width line. This is due to the difference in transistor size between the memory cell region and the peripheral circuit region.
다음으로, 도 2b에 도시된 바와 같이 더미 게이트(22) 패터닝 시 더미 게이트(22) 및 열산화막(21)이 받은 손상을 회복시키고, LDD(Lightly Doped Drain) 이온주입 시 스크린 산화막 역할을 수행할 수 있도록 하기 위하여 LDD 산화공정을 실시하고 LDD 이온주입(n-이온주입) 및 열처리를 실시한다. 도면부호 '23'은 LDD 산화공정에 의해 더미 게이트(22) 표면에 형성된 열산화막을 나타낸 것이다.Next, as shown in FIG. 2B, the damage received by the dummy gate 22 and the thermal oxide layer 21 during the patterning of the dummy gate 22 may be restored, and the screen oxide layer may serve as the LDD implantation. In order to be able to do so, LDD oxidation process is performed, and LDD ion implantation (n - ion implantation) and heat treatment are performed. Reference numeral 23 denotes a thermal oxide film formed on the surface of the dummy gate 22 by an LDD oxidation process.
다음으로, 도 2c에 도시된 바와 같이 더미 게이트(22) 측벽에 질화막 스페이서(24)를 형성하고, 소오스/드레인 형성을 위한 고농도 이온주입(n+이온주입) 및 열처리를 실시한다.Next, as illustrated in FIG. 2C, a nitride spacer 24 is formed on the sidewalls of the dummy gate 22, and high concentration ion implantation (n + ion implantation) and heat treatment are performed to form a source / drain.
계속하여, 도 2d에 도시된 바와 같이 전체 구조 상부에 층간절연막(25)를 증착하고, CMP 공정을 실시하여 더미 게이트(22) 패턴이 노출될 정도로 층간절연막(25)을 평탄화한다.Subsequently, as shown in FIG. 2D, the interlayer insulating layer 25 is deposited on the entire structure, and the CMP process is performed to planarize the interlayer insulating layer 25 to expose the dummy gate 22 pattern.
이어서, 도 2e에 도시된 바와 같이 더미 게이트(22) 패턴을 건식식각법 또는 습식식각법을 사용하여 선택적으로 제거한다.Subsequently, as shown in FIG. 2E, the dummy gate 22 pattern is selectively removed using a dry etching method or a wet etching method.
계속하여, 도 2f에 도시된 바와 같이 노출된 열산화막(21, 23)을 제거한 다음 노출된 실리콘 기판(20)을 세정한 후 노출된 실리콘 기판(20) 표면에 게이트 절연막(26)을 형성한다. 이때, 게이트 절연막(26)은 SiO2, Al2O3, Ta2O5를 단독 또는 이들을 조합하여 20 ~ 100Å 정도의 두께로 형성한다.Subsequently, as illustrated in FIG. 2F, the exposed thermal oxide films 21 and 23 are removed, and then the exposed silicon substrate 20 is cleaned, and then a gate insulating film 26 is formed on the exposed silicon substrate 20 surface. . At this time, the gate insulating film 26 is formed of SiO 2 , Al 2 O 3 , Ta 2 O 5 with a thickness of about 20 to 100 kPa alone or in combination thereof.
다음으로, 도 2g에 도시된 바와 같이 게이트 절연막(26) 상부에 층덮힘성이100％로 알려진 원자층 증착(Atomic Layer Deposition, ALD)법으로 게이트 전극용 전도막 형성을 위한 제1텅스텐막(27)을 증착한다. 이때, 제1텅스텐막(27)은 작은 게이트 전극 선폭의 반이상의 두께(300 ~ 500Å)로 증착하여, 작은 선폭의 대머신 게이트용 홈이 완전히 매립되도록 하며, WOCl3를 소오스 가스로 사용하여 200 ~ 500℃ 정도의 온도에서 증착한다. 여기서, ALD법을 사용한 제1텅스텐막(27)의 형성에 대해 구체적으로 살펴보면, WOCl3가스를 챔버에 주입하여 기판 전체 구조 표면에 WOCl3가스를 흡착시킨 후 N2, Ar과 같은 불활성 가스를 주입하여 미반응 WOCl3가스를 퍼지(purge)하고, 다시 WOCl3가스 주입 및 퍼지를 반복하여 원하는 두께만큼의 제1텅스텐막(27)을 형성하게 되는 것이다.Next, as shown in FIG. 2G, the first tungsten film 27 for forming a conductive film for the gate electrode by atomic layer deposition (ALD), which has a layer coverage of 100%, is formed on the gate insulating film 26. E). At this time, the first tungsten film 27 is deposited to a thickness (300 to 500 mW) of at least half the line width of the small gate electrode, so that the groove for the gate of the small line width is completely filled, and 200 using WOCl 3 as the source gas. Deposit at a temperature of ~ 500 ℃. Here, the formation of the first tungsten film 27 using the ALD method will be described in detail. After injecting the WOCl 3 gas into the chamber to adsorb the WOCl 3 gas to the surface of the entire structure of the substrate, an inert gas such as N 2 or Ar may be used. After injection, the unreacted WOCl 3 gas is purged, and the WOCl 3 gas is injected and purged again to form the first tungsten film 27 having a desired thickness.
다음으로, 도 2h에 도시된 바와 같이 제1텅스텐막(27) 상부에 통상적인 화학 기상 증착(Chemical Vapor Deposition, CVD)법을 사용하여 게이트 전극용 전도막 형성을 위한 제2텅스텐막(28)을 증착하여, 큰 선폭의 게이트용 홈이 완전히 매립되도록 한다. 이때, 제2텅스텐막(28)은 WF6가스를 소오스 가스로 하여 대머신 게이트용 홈의 깊이보다 두껍게 3000 ~ 8000Å 정도의 두께로 형성한다. 여기서, 층덮힘성이 100％로 알려진 ALD법으로 게이트 전극용 전도막을 모두 형성하지 않고 일부만 ALD법으로 형성하고 나머지는 통상적인 CVD법으로 형성하는 이유는, ALD법의 증착속도가 10 ~ 100 Å/min 정도로 매우 느리므로 본 실시예에서와 같이 500Å 이상의 두께로 증착하는 것은 반도체 소자의 생산성 측면을 고려할 때 바람직하지 않기 때문이다.Next, as shown in FIG. 2H, a second tungsten film 28 for forming a conductive film for the gate electrode using a conventional chemical vapor deposition (CVD) method on the first tungsten film 27. Is deposited so that the gate groove of the large line width is completely buried. At this time, the second tungsten film 28 is formed to have a thickness of about 3000 to 8000 Å thicker than the depth of the groove for the gate of the dam using the WF 6 gas as the source gas. Here, the ALD method, which has a layer covering property of 100%, does not form all of the conductive films for the gate electrode, but only a part of it is formed by the ALD method, and the rest is formed by the conventional CVD method. The deposition rate of the ALD method is 10 to 100 Å / Since it is very slow, such as min, deposition to a thickness of 500 kPa or more, as in this embodiment, is not preferable in view of the productivity of the semiconductor device.
다음으로, 도 2i에 도시된 바와 같이 층간절연막(25)이 노출될 정도로 CMP 공정을 실시하여 평탄화를 이룬다.Next, as shown in FIG. 2I, a CMP process is performed to expose the interlayer insulating layer 25 to planarize.
이렇듯, 본 발명은 대머신 게이트용 홈 내에 매립하기 위한 게이트 전극용 금속을 증착함에 있어서, 일차로 ALD법을 사용하여 작은 선폭의 대머신 게이트용 홈을 매립하고, 이차로 통상적인 CVD법을 사용하여 큰 선폭의 게이트용 홈까지 완전히 매립함으로써, 반도체 소자의 고집적화에 따라 단차비가 증가된 대머신 게이트용 홈을 갈라짐이나 보이드 없이 매립할 수 있다.As described above, in the present invention, in depositing a metal for a gate electrode for embedding in a trench for a damascene gate, first, a trench for a damascene gate having a small line width is filled by using the ALD method, and a second conventional CVD method is used. As a result, the gate grooves with large line widths are completely filled, so that the grooves for the large-machine gates with increased step ratios can be buried without cracking or voids due to high integration of semiconductor devices.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 대머신 게이트용 홈에 게이트 전극용 전도막을 매립함에 있어서, 갈라짐이나 보이드를 방지하는 효과가 있으며, 이에 따라 게이트 특성 및 수율을 향상시키는 효과가 있다.The present invention has the effect of preventing cracks and voids in filling the conductive film for the gate electrode in the groove for the gate of the dam machine, thereby improving the gate characteristics and yield.
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