KR100308396B1 - Manufacturing method of semiconductor package - Google Patents
Manufacturing method of semiconductor package Download PDFInfo
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- KR100308396B1 KR100308396B1 KR1019980052924A KR19980052924A KR100308396B1 KR 100308396 B1 KR100308396 B1 KR 100308396B1 KR 1019980052924 A KR1019980052924 A KR 1019980052924A KR 19980052924 A KR19980052924 A KR 19980052924A KR 100308396 B1 KR100308396 B1 KR 100308396B1
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- lead
- mounting plate
- chip mounting
- chip
- encapsulant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Laser Beam Processing (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 패키지의 제조방법에 관한 것으로서, 칩탑재판과, 상기 칩탑재판을 지지하는 타이바와, 상기 칩탑재판의 외주연에 일정거리 이격되어 대략 방사상으로 배열된 다수의 리드 등으로 이루어진 리드프레임을 제공하는 단계와; 상기 리드프레임의 칩탑재판에 반도체칩을 접착하는 단계와; 상기 반도체칩과 리드를 도전성와이어로 상호 접속하는 단계와; 상기 반도체칩, 칩탑재판, 리드 및 도전성 와이어 등을 봉지재로 봉지하는 단계와; 상기 칩탑재판, 리드 등의 저면에 형성된 봉지재 찌꺼기를 제거하는 디플래시 단계와; 상기 봉지재 상면에 소정 문자, 도형 등을 마킹하는 단계와; 상기 플래시가 제거된 리드 저면에 도전성볼을 융착하는 단계로 이루어진 반도체패키지의 제조 방법에 있어서, 상기 디플래시 단계는 레이저 빔을 이용하여 일정폭과 일정깊이로 리드 저면에 형성된 봉지재 찌꺼기를 제거하는 단계인 것을 특징으로 함.The present invention relates to a method for manufacturing a semiconductor package, comprising a chip mounting plate, a tie bar for supporting the chip mounting plate, and a plurality of leads arranged substantially radially at a predetermined distance from an outer circumference of the chip mounting plate. Providing a leadframe; Bonding a semiconductor chip to the chip mounting plate of the lead frame; Interconnecting the semiconductor chip and the lead with conductive wires; Encapsulating the semiconductor chip, the chip mounting plate, the lead and the conductive wire with an encapsulant; Deflashing step of removing the encapsulant residue formed on the bottom surface of the chip mounting plate, lead; Marking predetermined characters, figures, etc. on an upper surface of the encapsulant; In the method of manufacturing a semiconductor package comprising the step of fusion bonding the conductive ball on the bottom surface of the lead is removed, the deflashing step to remove the encapsulant residue formed on the bottom surface of the lead with a predetermined width and a predetermined depth using a laser beam Characterized in that it is a step.
Description
본 발명은 반도체 패키지의 제조방법에 관한 것으로, 보다 상세하게 설명하면 레이저를 이용하여 봉지재 찌꺼기인 플래시를 제거함은 물론, 레이저 마킹 작업을 하면서 동시에 플레시 제거 작업을 할 수 있는 반도체 패키기의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor package, and in more detail, a method of manufacturing a semiconductor package capable of removing a flash as an encapsulant residue using a laser, as well as performing a flash removal operation while laser marking. It is about.
일반적으로 반도체 패키지는 그 종류에 따라 수지밀봉 패키지, TCP(Tape Carrier Package)패키지, 글래스밀봉패키지, 금속밀봉 패키지 등이 있다.In general, semiconductor packages include resin sealing packages, tape carrier packages (TCP), glass sealing packages, and metal sealing packages.
이와 같은 반도체패키지는 실장 방법에 따라 삽입형과 표면실장(Surface Mount Technology, SMT)형으로 분류하게 되는데, 삽입형으로서 대표적인 것은 DIP (Dual In-Line Package), PGA(Pin Grid Array)등이 있고, 표면실장형으로서 대표적인 것은 QFP(Quad Flat Package), BGA(Ball Grid Array)등이 있다.Such semiconductor packages are classified into insert type and surface mount technology (SMT) types according to the mounting method. Representative types of insert types include DIP (Dual In-Line Package) and PGA (Pin Grid Array). Typical examples of the mounting type include a quad flat package (QFP) and a ball grid array (BGA).
최근에는 전자제품의 소형화에 따라 인쇄회로기판의 부품 장착도를 높이기 위해 삽입형 반도체패키지 보다는 표면실장형 반도체패키지가 널리 사용되고 있는데, 이러한 종래의 반도체 패키지에 대한 구조를 도 1과 도 2를 참조하여 설명하면 다음과 같다.Recently, in order to increase the mounting degree of components of a printed circuit board according to the miniaturization of electronic products, surface mount type semiconductor packages are widely used rather than insert type semiconductor packages. The structure of such a conventional semiconductor package will be described with reference to FIGS. 1 and 2. Is as follows.
도 1은 종래의 일반적인 반도체 패키지로서, 그 구조는 전자회로가 집적되어 있는 반도체칩(1)과, 상기 반도체칩(1)이 에폭시(2)에 의해 부착되는 칩탑재판(3)과, 상기 반도체칩(1)의 신호를 외부로 전달할 수 있는 다수의 리드(4)와, 상기 반도체칩(1)과 리드(4)를 연결시켜 주는 와이어(5)와, 상기 반도체칩(1)과 그 주변 구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 봉지재(6)로 이루어져 있다.1 is a conventional general semiconductor package, the structure of which is a semiconductor chip 1 in which an electronic circuit is integrated, a chip mounting plate 3 to which the semiconductor chip 1 is attached by an epoxy 2, and A plurality of leads 4 capable of transmitting signals of the semiconductor chip 1 to the outside, wires 5 connecting the semiconductor chips 1 and the leads 4, the semiconductor chips 1, and their In order to protect the surrounding components from external oxidation and corrosion, the encapsulant 6 is enclosed.
그러나, 상기의 반도체 패키지는 반도체칩이 점차적으로 고성능화되어 가면서 핀의 수가 더욱 더 많아지게 되는 데 비하여, 핀과 핀 사이의 거리를 일정치 이하로 좁히는 것은 기술적으로 어려움이 있기 때문에 많은 핀을 모두 수용하기 위해서는 패키지가 커지는 단점이 있다. 이것은 반도체패키지의 소형화 추세에 역행하는 결과를 낳는 문제점이 된다.However, in the semiconductor package described above, the number of the pins increases even more as the semiconductor chip is gradually improved in performance. However, it is technically difficult to narrow the distance between the pins to a predetermined value or less, so that many pins are accommodated. In order to achieve this, there is a disadvantage in that the package becomes large. This is a problem that results in the contrary to the trend of miniaturization of semiconductor packages.
이와 같이 소형화에 따른 기술적 요구를 해결하기 위해서 등장한 것이 도 2에 도시된 반도체 패키지로서, 이는 입출력수단으로 반도체패키지의 일면전체에 융착된 도전성볼을 이용함으로써 도 1에 도시된 반도체패키지보다 많은 수의 입출력 수단을 수용할 수 있음은 물론, 그 크기도 보다 작게 형성할 수 있다.The semiconductor package shown in FIG. 2 has emerged to solve the technical demands of the miniaturization as described above, which uses a conductive ball fused to the entire surface of the semiconductor package as an input / output means. The input / output means can be accommodated, and the size thereof can also be made smaller.
이러한 반도체 패키지의 구성은 도 2에 도시된 바와 같이 전자회로가 집적되어 있는 반도체 칩과(1), 상기 반도체 칩(1)을 에폭시를 통해 중앙에 부착하는 칩 탑재판(7)과, 상기 칩 탑재판(7)의 측부에 하프 에칭 처리하여 형성된 다수의 리드 (4)와, 상기 리드(4)에 반도체 칩(1)의 전기적인 신호를 입출력할 수 있도록 본딩 처리한 와이어(5)와, 상기 리드(4)의 저면(랜드) 부위에 융착되어 외부의 전기적인 신호가 전달될 수 있도록 하는 도전성볼(8)과, 상기 반도체 칩(1)과 그 주변 구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 봉지재(6)로 구성되어 있다.The semiconductor package includes a semiconductor chip 1 in which electronic circuits are integrated as shown in FIG. 2, a chip mounting plate 7 attaching the semiconductor chip 1 to the center through epoxy, and the chip. A plurality of leads 4 formed by half-etching the side of the mounting plate 7, wires 5 bonded to enable the input and output of an electrical signal of the semiconductor chip 1 to the leads 4, The conductive ball 8 is fused to the bottom (land) of the lid 4 so that an external electrical signal can be transmitted, and the semiconductor chip 1 and its peripheral components are protected from external oxidation and corrosion. It consists of the encapsulation material 6 wrapped to the outside thereof.
그러나, 이러한 반도체 패키지는 현행 반도체 패키지 제조공정상 봉지 작업후에 리드를 덮고 있는 봉지재의 찌꺼기나 기타 성분들을 제거하기 위해 황산 혹은 염산과 같은 화학 성분을 이용하고, 이도 충분치 않아 작은 쇠구슬 혹은 물분사 같은 기계적인 디플래쉬(deflash) 방법이 이용되고 있다. 더구나, 이때 사용되는 화학성분을 이용하게 될 경우 환경 문제를 야기시킬 수 있고 생산 자재도 화학성분과의 접촉으로 인한 부식 및 품질의 저하도 예상되며, 특히 기계적인 디플래시방법은 자재의 깨짐 혹은 불완전한 디플래시로 인한 수율 저하 문제가 대두되고 있다.However, these semiconductor packages use chemical components such as sulfuric acid or hydrochloric acid to remove the residue or other components of the encapsulation material covering the lid after encapsulation in the current semiconductor package manufacturing process. A conventional deflash method is used. In addition, the use of chemicals used in this case may cause environmental problems, and the production materials may also cause corrosion and deterioration of quality due to contact with the chemicals. In particular, the mechanical deflecting method may cause material cracking or incompleteness. Yields due to deflation are emerging.
본 발명은 이와 같은 종래의 제반 문제점을 해결하기 위기 위해 안출한 것으로서, 그 목적은 현재 반도체패키지 제조 방법중 마킹 공정에서 사용되는 레이저빔을 마킹 공정과 병행하여 리드부위에 덮혀 있는 봉지재의 찌꺼기(플래시)를 제거함으로써 별도의 장비없이 기존의 장비만으로도 봉지재의 플래시를 제거할 수 있도록 하여 추가적인 투자비가 절감되도록 하고, 환경오염을 미연에 방지할 수 있도록 하는 데 있다.The present invention has been made in order to solve such a conventional problem, the object of the present invention is the packaging of the encapsulant (flash) covered in the lead portion in parallel with the marking process of the laser beam used in the marking process of the semiconductor package manufacturing method By eliminating), it is possible to remove the flash of the encapsulant with only the existing equipment without additional equipment so that additional investment cost can be saved and environmental pollution can be prevented in advance.
도 1 및 도 2은 종래의 반도체 패키지를 도시한 단면도이다.1 and 2 are cross-sectional views showing a conventional semiconductor package.
도 3은 본 발명의 제조 방법에 의해 제조된 반도체패키지를 도시한 단면도이다.3 is a cross-sectional view showing a semiconductor package manufactured by the manufacturing method of the present invention.
도 4는 본 발명에 의한 반도체패키지의 제조 방법을 도시한 순차 설명도이다.4 is an explanatory diagram sequentially illustrating a method of manufacturing a semiconductor package according to the present invention.
* 도면의 주요부분에 대한 부호설명* Explanation of symbols on the main parts of the drawings
1,10 ; 반도체 칩 2,20 ; 에폭시1,10; Semiconductor chips 2,20; Epoxy
3,30 ; 칩탑재판 4,40 ; 리드3,30; Chip mounting plate 4,40; lead
5,50 ; 와이어 6,60 ; 봉지재5,50; Wire 6,60; Encapsulant
7,70 ; 회로기판 8,80 ; 도전성볼7,70; Circuit board 8,80; Conductive ball
상기한 목적을 달성하기 우해 본 발명에 의한 반도체패키지의 제조 방법은 칩탑재판과, 상기 칩탑재판을 지지하는 타이바와, 상기 칩탑재판의 외주연에 일정거리 이격되어 대략 방사상으로 배열된 다수의 리드 등으로 이루어진 리드프레임을 제공하는 단계와; 상기 리드프레임의 칩탑재판에 반도체칩을 접착하는 단계와; 상기 반도체칩과 리드를 도전성와이어로 상호 접속하는 단계와; 상기 반도체칩, 칩탑재판, 리드 및 도전성와이어 등을 봉지재로 봉지하는 단계와; 상기 칩탑재판, 리드 및 리드 저면에 형성된 봉지재 찌꺼기를 제거하는 디플래시 단계와; 상기 봉지재 상면에 소정 문자, 도형 등을 마킹하는 단계와; 상기 플래시가 제거된 리드 저면에 도전성볼을 융착하는 단계로 이루어진 반도체패키지의 제조 방법에 있어서, 상기 디플래시 단계는 레이저빔을 이용하여 일정폭과 일정깊이로 리드 저면에 형성된 봉지재 찌꺼기를 제거하는 단계인 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention includes a chip mounting plate, a tie bar supporting the chip mounting plate, and a plurality of substantially radially spaced apart from the outer circumference of the chip mounting plate. Providing a lead frame including a lead and the like; Bonding a semiconductor chip to the chip mounting plate of the lead frame; Interconnecting the semiconductor chip and the lead with conductive wires; Encapsulating the semiconductor chip, the chip mounting plate, the lead and the conductive wire with an encapsulant; Deflashing step of removing the encapsulant residue formed on the chip mounting plate, lead and the bottom surface of the lead; Marking predetermined characters, figures, etc. on an upper surface of the encapsulant; In the method of manufacturing a semiconductor package comprising the step of fusion bonding the conductive ball on the bottom surface of the lead is removed, the deflashing step using a laser beam to remove the encapsulant residue formed on the bottom surface of the lead with a predetermined width and a predetermined depth It is characterized by the steps.
여기서, 상기 디플래시 단계는 마킹 단계에서 동시에 수행함이 바람직하다.Here, the deflashing step is preferably performed simultaneously in the marking step.
또한, 상기 디플래시 단계는 리드와 리드 저면뿐만 아니라, 칩탑재판, 타이바, 게이트에도 수행함이 바람직하다.In addition, the deflashing step may be performed not only on the lead and the bottom of the lead, but also on the chip mounting plate, tie bar, and gate.
이하, 본 발명이 속하는 기술적 분야에서 통상의 지식을 가진 자가 이 발명을 용이하게 실시할 수 있을 정도로, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.
도 3은 본 발명의 실시예에 따른 레이저에 의해 플래쉬가 제거된 반도체 패키지의 단면도이고, 도 4는 본 발명의 실시예에 따른 레이저에 의해 플래쉬가 제거하는 반도체 패키지 제조방법을 도시한 순차 설명도이다.3 is a cross-sectional view of a semiconductor package from which a flash is removed by a laser according to an embodiment of the present invention, and FIG. 4 is a sequential diagram illustrating a method of manufacturing a semiconductor package from which a flash is removed by a laser according to an embodiment of the present invention. to be.
먼저, 도 3에서 보는 바와 같이 본 발명의 제조 방법에 의해 제조된 반도체 패키지는 전자회로가 집적되어 있는 반도체 칩(10)과 상기 반도체 칩(10)을 에폭시를 통해 중앙에 부착하는 칩 탑재판(70)과, 상기 칩 탑재판(70)의 측부에 하프 에팅 처리되어 형성된 리드(40)와, 상기 리드(40)에 반도체 칩(10)의 전기적인 신호를 입출력할 수 있도록 본딩한 와이어(50)와, 상기 리드(40)의 저면(랜드)에 융착되어 외부의 전기적인 신호가 전달될 수 있도록 하는 도전성볼(80)과, 상기 반도체칩(10)과 그 주변 구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 봉지재(60)로 구성되어 있으며, 이러한 구성은 종래와 유사하다.First, as shown in FIG. 3, the semiconductor package manufactured by the manufacturing method of the present invention includes a semiconductor chip 10 having an electronic circuit integrated thereon and a chip mounting plate attaching the semiconductor chip 10 to the center through epoxy. 70, a lead 40 formed by half etching on the side of the chip mounting plate 70, and a wire 50 bonded to the lead 40 to input and output electrical signals of the semiconductor chip 10. ), The conductive ball 80 is fused to the bottom (land) of the lead 40 so that an external electrical signal can be transferred, and the semiconductor chip 10 and its peripheral components are externally oxidized and corroded. It is composed of an encapsulant 60 wrapped around the outside thereof to protect it from such a configuration, which is similar to the conventional art.
이러한 반도체패키지를 제조하기 위한 본 발명의 제조 방법은 도 4에 도시된 바와 같이 전자회로가 집적된 반도체칩(10)을 에폭시 재질의 접착제로 칩탑재판(70) 상면에 접착하고, 상기 칩 탑재판(70)을 중심으로 방사상 배열되고, 하프에칭(Half Etching) 처리된 리드(40)에 상기 반도체칩(10)과 전기적인 신호를 입출력할 수 있도록 도전성 와이어(50)를 본딩하고, 상기 반도체칩(10)과 리드가 외부로 노출되지 않도록 봉지재(60)로 봉지하고, 상기 봉지재(60)로 봉지된 리드 (40)의 저면(랜드) 부위를 레이저빔을 이용하여 일정 깊이로 깍아 봉지재찌꺼기(플래시)를 제거함과 동시에 봉지재(60)의 상부를 레이저빔으로 마킹처리하고, 상기 레이저빔에 의해 깍여진 리드(40)의 랜드 부위에 금(Au), 은(Ag) 및 니켈(Ni) 등을 도금 처리하고, 이어서 도전성볼(80)을 융착시키는 방법으로 이루어져 있다.In the manufacturing method of the present invention for manufacturing such a semiconductor package, as shown in Figure 4, the semiconductor chip 10, the electronic circuit is integrated is bonded to the upper surface of the chip mounting plate 70 with an adhesive of epoxy material, the chip mounting Bonding the conductive wire 50 to the semiconductor chip 10 and the electrical signal to the semiconductor chip 10 in the radially arranged around the plate 70, the half-etched lead 40, and the semiconductor The chip 10 and the lid are encapsulated with the encapsulant 60 so as not to be exposed to the outside, and the bottom (land) portion of the lid 40 encapsulated with the encapsulant 60 is cut to a predetermined depth using a laser beam. While removing the encapsulant residue (flash), at the same time marking the upper portion of the encapsulant 60 with a laser beam, gold (Au), silver (Ag) and on the land portion of the lead 40 cut by the laser beam Nickel (Ni) or the like is plated, and then the conductive balls 80 are fused. It consists of the law.
여기서, 상기 수지물이 흘러 들어가는 게이트(도시되지 않음), 칩탑재판 및 리드를 포함하는 리드프레임은 종래와 같이 상기 칩탑재판을 지지하기 위한 타이바가 형성되고(도시되지 않음), 또한 상기 리드를 지지하기 위해 댐바(도시되지 않음)도 구비되어 있다. 물론, 상기 댐바 등은 제조 공정중 제거된다. 또한, 상기 칩탑재판 없이 직접 반도체칩이 위치되고, 상기 반도체칩이 봉지재 저면으로 노출될 수도 있다.Here, a lead frame including a gate (not shown) through which the resin flows, a chip mounting plate, and a lead is formed with a tie bar for supporting the chip mounting plate as shown in the related art (not shown), and also the lead Dam bars (not shown) are also provided to support them. Of course, the dam bar and the like are removed during the manufacturing process. In addition, the semiconductor chip may be directly positioned without the chip mounting plate, and the semiconductor chip may be exposed to the bottom surface of the encapsulant.
이와 같이 구성된 본 발명의 작용효과를 상세히 설명하면 다음과 같다.Referring to the effects of the present invention configured as described above in detail.
본 발명의 핵심적인 요지는 반도체패키지의 제조시 레이저 빔으로 봉지재 찌꺼기인 플래시를 제거하는 방법이며, 이를 위주로 설명한다.A key aspect of the present invention is a method of removing a flash, which is an encapsulant residue, with a laser beam in the manufacture of a semiconductor package.
도면 도 3 및 도4를 참조하여 설명하면 먼저, 칩탑재판과, 상기 칩탑재판을 지지하는 타이바와, 상기 칩탑재판의 외주연에 일정거리 이격되어 대략 방사상으로 배열된 다수의 리드 등으로 이루어진 리드프레임을 제공한 후, 상기 칩탑재판(70)상에 전자회로가 집적된 반도체칩(10)을 접착제로 접착한다.Referring to FIGS. 3 and 4, first, a chip mounting plate, a tie bar supporting the chip mounting plate, and a plurality of leads arranged substantially radially at a predetermined distance from an outer circumference of the chip mounting plate. After providing the lead frame is made, the semiconductor chip 10, the electronic circuit is integrated on the chip mounting plate 70 is bonded with an adhesive.
상기 반도체칩(10)과 리드(40)는 도전성 와이어(50)로 상호 접속시킴으로써 반도체칩의 전기적 신호가 상기 리드와 도통되도록 한다.The semiconductor chip 10 and the lead 40 are interconnected by conductive wires 50 so that electrical signals of the semiconductor chip are conducted with the leads.
상기 도전성 와이어(50)가 본딩된 반도체칩(10), 칩 탑재판(70), 리드(40) 등은 외부의 열, 수분, 충격 등으로부터 보호되어 제품의 성능이 최적, 극대화되도록 에폭시수지로 구성된 봉지재(60) 예를 들면 에폭시몰딩컴파운드(Epoxy Molding Compound)와 같은 봉지재로 봉지한다.The semiconductor chip 10, the chip mounting plate 70, the lead 40, etc., to which the conductive wire 50 is bonded, are protected from external heat, moisture, impact, etc., so that the performance of the product is optimized and maximized with epoxy resin. The encapsulation material 60 constituted, for example, is encapsulated with an encapsulant such as an epoxy molding compound.
이어서, 상기 봉지재(60) 상면에는 제조회사 및 반도체 패키지의 번호 등을 식각하여 마킹할 수 있도록 일정한 진동파장을 갖는 CO2 레이저나 인조고체봉으로 불려지는 Nd레이저 혹은 다이오드레이저 및 엑시머레이저 등을 이용한 레이저빔으로 마킹함과 동시에 봉지 공정중 발생된 리드(40), 칩탈재판(70), 타이바 등의 저면에 발생된 플래시를 제거한다.Subsequently, on the upper surface of the encapsulant 60, Nd lasers or diode lasers and excimer lasers, which are called CO2 lasers or artificial solid rods having a constant vibration wavelength, may be used to etch and mark numbers of manufacturers and semiconductor packages. At the same time as marking with a laser beam, the flash generated on the bottom surface of the lead 40, the chip removing plate 70, the tie bar, etc. generated during the encapsulation process is removed.
상기 리드(40), 칩탑재판(70), 타이바 또는 반도체칩(10)이 봉지재(60) 저면으로 노출되는 경우에는 그 반도체칩(10)의 저면에 덮여진 플래시를 제거하기 위해서, 상기 각각의위치와 크기 등을 고려하여 레이저 빔을 발사하게 된다.When the lead 40, the chip mounting plate 70, the tie bar or the semiconductor chip 10 is exposed to the bottom surface of the encapsulant 60, in order to remove the flash covered on the bottom surface of the semiconductor chip 10, The laser beam is fired in consideration of the respective positions and sizes.
특히, 리드(40)의 랜드 부위에 형성된 플래시를 제거할 경우에는 그 리드의 랜드에 융착될 도전성볼(80)의 위치와 크기를 고려하여 리드(40)의 랜드 부위를 레이저 빔으로 일정한 폭과 깊이로 깍아 플래시를 제거하게 된다.In particular, when removing the flash formed on the land portion of the lead 40, the land portion of the lead 40 is fixed with a laser beam in consideration of the position and size of the conductive ball 80 to be fused to the land of the lead. The depth will be removed to remove the flash.
플래시가 제거된 리드(40)는 도전성볼(80)을 융착시키기 위해 랜드 부위에 금, 은 및 니켈 등이 함유된 얇은 막의 도금층을 입힐 수 있으며, 도전성볼(80)을 융착하는 것으로 도전성볼(10)은 반도체 칩(10)과 외부 장치의 전기적 신호를 원활하게 입출력하게 된다.The lead 40 from which the flash is removed may coat a thin film-plated layer containing gold, silver, nickel, or the like on the land portion in order to fusion the conductive ball 80, and the conductive ball 80 may be fused by the conductive ball 80. 10 smoothly inputs and outputs electrical signals from the semiconductor chip 10 and an external device.
또한 도전성볼(80)이 융착된 반도체 패키지는 싱귤레이션등의 공정을 거처 상품의 가치를 지닌 제품으로 완성되어 유통된다.In addition, the semiconductor package in which the conductive balls 80 are fused is completed and distributed as a product having a product value through a process such as singulation.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않고, 본 발명의 범주와 사상을 벗어나지 않는 범위내에서 여러가지 다른 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto and various other embodiments may be possible without departing from the scope and spirit of the present invention.
이와 같이 작용하는 본 발명은 반도체패키지 공정 단계중 마킹공정에서 사용되는 레이저빔을 마킹 공정과 병행하여 리드, 칩탑재판, 타이바, 댐바 또는 반도체 칩의 일면 영역에 덮혀 있는 봉지재의 찌꺼기를 제거함으로서 별도의 장비없이 기존의 장비만으로도 봉지재의 플래쉬를 용이하게 제거하여 추가적인 투자비를 절감시키고, 레이저 빔에 의한 비접촉 플래시 제거로 정전기 발생 및 환경오염 발생을 제거하는 효과를 갖는다.The present invention, which acts as described above, removes the residues of the encapsulant covered in the lead, chip mounting plate, tie bar, dam bar, or one region of the semiconductor chip in parallel with the marking process in the laser beam used in the marking process during the semiconductor package process step. Without additional equipment, the existing equipment can be easily removed by removing the flash of the encapsulant, thereby reducing additional investment costs, and eliminating the generation of static electricity and environmental pollution by removing the non-contact flash by the laser beam.
Claims (3)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980052924A KR100308396B1 (en) | 1998-12-03 | 1998-12-03 | Manufacturing method of semiconductor package |
| US09/444,035 US6448633B1 (en) | 1998-11-20 | 1999-11-19 | Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant |
| JP11330293A JP2000164788A (en) | 1998-11-20 | 1999-11-19 | Lead frame for semiconductor package and semiconductor package using the lead frame and its manufacture |
| US10/152,945 US6825062B2 (en) | 1998-11-20 | 2002-05-22 | Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant |
| US10/667,227 US7057280B2 (en) | 1998-11-20 | 2003-09-18 | Leadframe having lead locks to secure leads to encapsulant |
| US11/365,246 US7564122B2 (en) | 1998-11-20 | 2006-03-01 | Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980052924A KR100308396B1 (en) | 1998-12-03 | 1998-12-03 | Manufacturing method of semiconductor package |
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| KR100308396B1 true KR100308396B1 (en) | 2001-12-17 |
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| KR20110076604A (en) * | 2009-12-29 | 2011-07-06 | 하나 마이크론(주) | Pop package and method for manufacturing thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH06177268A (en) * | 1992-12-07 | 1994-06-24 | Fujitsu Ltd | Fabrication of semiconductor device |
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| JPH06177268A (en) * | 1992-12-07 | 1994-06-24 | Fujitsu Ltd | Fabrication of semiconductor device |
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