KR100294690B1 - Method for forming contact hole of semiconductor device - Google Patents
Method for forming contact hole of semiconductor device Download PDFInfo
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- KR100294690B1 KR100294690B1 KR1019930013213A KR930013213A KR100294690B1 KR 100294690 B1 KR100294690 B1 KR 100294690B1 KR 1019930013213 A KR1019930013213 A KR 1019930013213A KR 930013213 A KR930013213 A KR 930013213A KR 100294690 B1 KR100294690 B1 KR 100294690B1
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- South Korea
- Prior art keywords
- interlayer insulating
- insulating film
- photoresist
- contact hole
- etching
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000206 photolithography Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 14
- 238000010438 heat treatment Methods 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
제1도는 종래 반도체 장치의 콘택홀 형성방법을 나타낸 공정순서도.1 is a process flowchart showing a method for forming a contact hole in a conventional semiconductor device.
제2도는 본 발명의 반도체 장치의 콘택홀 형성방법을 나타낸 공정순서도.2 is a process flowchart showing a method for forming a contact hole in a semiconductor device of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1 : 기판 2 : 소오스/드레인영역1 substrate 2 source / drain region
3 : 게이트 21 : BPSG3: gate 21: BPSG
22.22' : 포토레지스트 23 : 콘택홀22.22 ': photoresist 23: contact hole
본 발명은 고집적 반도체 소자의 콘택홀(Comtact hole)형성 및 평탄화 방법에 관한 것으로, 특히 콘택홀 형성 전후의 평탄화를 위한 고온열처리 및 콘택 오버에치(Overetch)를 개선시킨 콘택홀 형성 및 평탄화 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming and planarizing a contact hole of a highly integrated semiconductor device. In particular, the present invention relates to a contact hole formation and planarization technique for improving high temperature heat treatment and contact overetch for planarization before and after contact hole formation. It is about.
종래의 고집적 반도체 소자의 콘택홀 형성방법을 제1도를 참조하여 설명하면, 먼저 하지구조물(예컨대, 트랜지스터 등)이 형성된 기판(1)상에 (a)와 같이 층간절연막으로 고온 열처리시의 유동성을 갖는 BPSG(Boro-Phospho-Silicate Glass)(11)를 증착한 후, (b)와 같이 고온 열처리를 행하여 BPSG(11)를 평탄화시킨 다음 포토레지스트(12)를 이용한 포토리소그래픽(Photolithography) 공정에 의해 소정영역에 콘택홀(13)을 형성한다.Referring to FIG. 1, a conventional method for forming a contact hole of a highly integrated semiconductor device is described below. First, fluidity during high temperature heat treatment with an interlayer insulating film as shown in (a) on a substrate 1 on which a base structure (e.g., a transistor) is formed. After depositing the BPSG (Boro-Phospho-Silicate Glass) 11 having a high-temperature heat treatment as shown in (b) to planarize the BPSG (11) and then photolithography (Photolithography) process using the photoresist 12 The contact hole 13 is formed in a predetermined region by the contact.
이어서 다시 고온열처리(Reflow)를 행하여 (c)와 같이 완만한 형태의 콘택홀이 되도록 한다.Subsequently, high temperature heat treatment (Reflow) is performed again to form a smooth contact hole as shown in (c).
종래 반도체 소자에 있어서, 소자와 소자의 배선재료로 많이 사용되는 알루미늄은 단차피복성이 좋지 않아 하지막의 평탄화가 필요하며 이에따라 제1도 (a)와 같이 고온열처리시 유동성을 갖는 BPSG막을 증착하고 열처리하여 평탄화를 이루게 된다.In the conventional semiconductor device, aluminum, which is widely used as a device and a wiring material of the device, has a poor step coverage and needs flattening of the underlying film. Thus, as shown in FIG. 1 (a), a BPSG film having fluidity is deposited and heat treated during high temperature heat treatment. To achieve flattening.
또한 콘택홀을 형성하고 난 후 콘택홀 부분의 금속배선시 단차피복성을 향상시키기 위해 제1도 (c)와 같이 다시한번 고온 열처리를 행하게 된다.In addition, after the contact hole is formed, the high temperature heat treatment is performed once again as shown in FIG.
이와같은 종래 방법에서는 평탄화를 위한 800-1000℃ 에서의 고온 열처리가 필요하게 되고, 그 하지층의 단차로 인해, 예컨대 트랜지스터에 있어서 소오스/드레인(2) 콘택부분과 게이트(3)콘택부분의 오버에치(Overetch)정도가 크게 달라 부분적으로 심한 오버에치가 발생하게 되어 누설(leakage)등의 문제를 초래한다.Such a conventional method requires a high temperature heat treatment at 800-1000 ° C. for planarization, and due to the step difference in the underlying layer, for example, the over-over of the source / drain 2 contact portion and the gate 3 contact portion in the transistor. The degree of etch is very different, which causes partial over etch, which leads to problems such as leakage.
본 발명은 상술한 문제를 해결하기 위한 것으로, 고온 열처리 및 콘택오버에치를 개선한 콘택홀 형성 및 평탄화방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for forming and planarizing a contact hole having improved high temperature heat treatment and contact overetch.
상기 목적을 달성하기 위해 본 발명은 소정의 하부 구조물이 형성된 반도체기판상에 층간절연막을 증착하는 제1단계와, 상기 층간절연막상에 포토레지스트를 도포하고 포토리소그래피 공정에 의해 콘택홀 영역을 패터닝하는 제2단계, 상기 포토레지스트 및 층간절연막을 소정두께만큼 에치하는 제3단계, 상기 층간절연막의 잔류분을 모두 제거하기 위해 상기 포토레지스트 및 층간절연막을 에치백하는 제4단계, 및 상기 잔류하는 포토레지스트 및 층간절연막을 오버에치하는 제5단계로 구성됨을 특징으로 한다.In order to achieve the above object, the present invention provides a first step of depositing an interlayer insulating film on a semiconductor substrate on which a predetermined lower structure is formed, applying a photoresist on the interlayer insulating film, and patterning a contact hole region by a photolithography process. A second step, a third step of etching the photoresist and the interlayer insulating film by a predetermined thickness, a fourth step of etching back the photoresist and the interlayer insulating film to remove all residues of the interlayer insulating film, and the remaining And a fifth step of overetching the photoresist and the interlayer insulating film.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도에 본 발명의 콘택홀 형성방법을 제조공정에 따라 도시하였다.2 illustrates a method for forming a contact hole according to the present invention.
먼저, 제2도 (a)와 같이 층간절연막의 하부 구조물로서 트랜지스터가 형성된 기판(1)상에 층간절연막으로서, BPSG(21)를 증착한 후, 고온 열처리를 행하지 않고 포토레지스트(22)를 사용한 포토리소그래피 공정에 의해 콘택홀 영역(23)을 정의한다.First, as the interlayer insulating film on the substrate 1 on which the transistor is formed as a lower structure of the interlayer insulating film as shown in FIG. 2A, the BPSG 21 is deposited, and then the photoresist 22 is used without performing high temperature heat treatment. The contact hole region 23 is defined by a photolithography process.
이어서 제2도 (b)와 같이 콘택홀의 크기를 결정하는 CD(Critical Dimension)관리를 위한 건식에치를 행한다.Next, as shown in FIG. 2 (b), dry etching for CD (Critical Dimension) management for determining the size of the contact hole is performed.
이때의 콘택에치량은 BPSG의 에치하고자 하는 전체두께의 10-30% 정도를 에치하며, 포토레지스트와 BPSG의 식각 선택비를 1:(5-10)로 조절하여 에치한다.At this time, the contact etch amount is about 10-30% of the total thickness of the BPSG to be etched, and the etch selectivity of the photoresist and BPSG is adjusted to 1: (5-10).
여기서, 참조부호 22는 최초의 포토레지스트 도포상태를 나타낸 것이고, 22'는 에치된 상태를 나타낸 것이다.Here, reference numeral 22 denotes an initial photoresist coating state, and 22 'denotes an etched state.
다음에 제2도 (c)와 같이 포토레지스트와 BPSG의 식각 선택비가 같도록, 즉 포토레지스트:BPSG=1:(0.5-1)로 에치조건을 조절하여 BPSG 나머지 두께를 전부 에치할 수 있도록 포토레지스트와 BPSG의 에치백을 행한다.Next, as shown in FIG. 2 (c), the etching selectivity of the photoresist and the BPSG is the same, that is, the photoresist is adjusted so that the remaining thickness of the BPSG can be etched by adjusting the etching conditions with BPSG = 1: (0.5-1). The resist and the BPSG are etched back.
이때, BPSG의 에치량은 총 에치량의 90-110%를 에치한다.At this time, the etch amount of the BPSG etch 90-110% of the total etch amount.
다음에 (d)와 같이 적절한 평탄화 및 콘택부분의 진류층을 없애기 위해 BPSG를 5-20% 오버에치 함으로써 콘택홀을 형성함과 동시에 평탄화를 이룬다.Next, as shown in (d), the BPSG is over-etched by 5-20% in order to properly planarize and eliminate the confluence layer of the contact portion, thereby forming a contact hole and planarization.
이때 소오스/드레인 영역(2)의 콘택홀과 게이트(3)상의 콘택홀에서 모두 적절한 에치가 이루어지도록 오버에치 한다.At this time, over-etching is performed so that proper etching is performed in both the contact hole of the source / drain region 2 and the contact hole on the gate 3.
상기 3단계로 행해지는 에치공정시에 에치가스로는 CHF3와 O2를 사용하며 O2유량을 조절하여 식각선택비를 조절한다.In the etch process performed in the above three steps, as the etch gas, CHF 3 and O 2 are used, and the etching selectivity is adjusted by adjusting the O 2 flow rate.
이상과 같이 본 발명에 의하면 금속배선의 단차피복성 개선을 위한 층간절연막의 고온 열처리 공정이 필요없게 되며, 소오스/드레인 부분의 콘택 및 게이트상의 콘택의 오버에치비율(Overetch rate)이 비슷하게 조절되어 과도한 오버에치에 기인한 누설을 방지할 수 있다.As described above, according to the present invention, the high temperature heat treatment process of the interlayer insulating film is not required to improve the step coverage of the metal wiring, and the overetch rate of the contact on the source / drain portion and the contact on the gate is similarly adjusted. Leakage due to excessive overetch can be prevented.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930013213A KR100294690B1 (en) | 1993-07-14 | 1993-07-14 | Method for forming contact hole of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930013213A KR100294690B1 (en) | 1993-07-14 | 1993-07-14 | Method for forming contact hole of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950004406A KR950004406A (en) | 1995-02-18 |
| KR100294690B1 true KR100294690B1 (en) | 2001-10-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930013213A KR100294690B1 (en) | 1993-07-14 | 1993-07-14 | Method for forming contact hole of semiconductor device |
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| KR (1) | KR100294690B1 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6419728A (en) * | 1987-07-15 | 1989-01-23 | Nec Corp | Manufacture of semiconductor device |
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- 1993-07-14 KR KR1019930013213A patent/KR100294690B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6419728A (en) * | 1987-07-15 | 1989-01-23 | Nec Corp | Manufacture of semiconductor device |
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| Publication number | Publication date |
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| KR950004406A (en) | 1995-02-18 |
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