KR100290231B1 - Method for forming contact of semiconductor device - Google Patents
Method for forming contact of semiconductor device Download PDFInfo
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- KR100290231B1 KR100290231B1 KR1019980036577A KR19980036577A KR100290231B1 KR 100290231 B1 KR100290231 B1 KR 100290231B1 KR 1019980036577 A KR1019980036577 A KR 1019980036577A KR 19980036577 A KR19980036577 A KR 19980036577A KR 100290231 B1 KR100290231 B1 KR 100290231B1
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- interlayer insulating
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 49
- 239000010410 layer Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims description 20
- 239000003989 dielectric material Substances 0.000 claims 4
- 239000002184 metal Substances 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 13
- 238000004140 cleaning Methods 0.000 description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- CCEKAJIANROZEO-UHFFFAOYSA-N sulfluramid Chemical group CCNS(=O)(=O)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)F CCEKAJIANROZEO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
돌출부가 없는 균일한 콘택 프로파일을 갖는 콘택홀을 형성하기에 알맞은 반도체소자의 콘택형성방법을 제공하기 위한 것으로, 이와 같은 목적을 달성하기 위한 반도체소자의 콘택형성방법은 반도체기판에 제 1 층간절연막을 증착하는 단계,The present invention provides a method for forming a contact for a semiconductor device suitable for forming a contact hole having a uniform contact profile without protrusions. A method of forming a contact for a semiconductor device for achieving the above object includes forming a first interlayer insulating film on a semiconductor substrate. Depositing,
상기 제 1 층간절연막과 식각선택비가 다른 제 2 층간절연막을 증착하는 단계, 상기 제 2 층간절연막상에 상기 제 1 층간절연막과 식각선택비가 동일한 제 3 층간절연막을 증착하는 단계, 상기 제 1, 제 3 층간절연막보다 상기 제 2 층간절연막의 식각선택성이 더 좋은 식각가스를 사용하여 상기 제 1, 제 3 층간절연막이 상기 제 2 층간절연막보다 돌출되도록 콘택홀을 형성하는 단계, 후처리공정으로 상기 콘택홀내에 돌출된 상기 제 1, 제 3 층간절연막을 식각하여 돌출부위없는 콘택 프로파일을 형성하는 것을 특징으로 한다.Depositing a second interlayer dielectric layer having an etch selectivity different from the first interlayer dielectric layer; depositing a third interlayer dielectric layer having the same etch selectivity as the first interlayer dielectric layer on the second interlayer dielectric layer; Forming a contact hole so that the first and third interlayer insulating films protrude from the second interlayer insulating film using an etching gas having better etching selectivity of the second interlayer insulating film than the third interlayer insulating film. The first and third interlayer insulating films protruding in the holes are etched to form contact profiles without protrusions.
Description
본 발명은 반도체소자에 대한 것으로, 특히 베리어 메탈층을 형성하기 위해 식각선택비가 다른 물질로 구성된 부분에 균일한 콘택프로파일을 콘택홀을 형성하기에 알맞은 반도체소자의 콘택형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for forming a contact for a semiconductor device suitable for forming a contact hole with a uniform contact profile in a portion formed of a material having a different etching selectivity to form a barrier metal layer.
첨부 도면을 참조하여 종래 반도체소자의 콘택형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method for forming a contact of a conventional semiconductor device is as follows.
도 1a 내지 도 1c는 종래 반도체소자의 콘택형성방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method for forming a contact of a conventional semiconductor device.
종래 반도체소자의 콘택형성방법은 도 1a에 도시한 바와 같이 반도체기판(1)에 게이트전극(2)을 형성한다. 이후에 게이트전극(2) 상부에는 산화막으로 형성된 제 1 층간절연막(3)을 증착하고, 제 1 층간절연막(3)상부에 질화막(4)을 증착한다.In the conventional method for forming a contact of a semiconductor device, as shown in FIG. 1A, a gate electrode 2 is formed on a semiconductor substrate 1. Thereafter, a first interlayer insulating film 3 formed of an oxide film is deposited on the gate electrode 2, and a nitride film 4 is deposited on the first interlayer insulating film 3.
그리고 질화막(4)사에 산화막으로 형성된 제 2 층간절연막(5)을 증착한다.A second interlayer insulating film 5 formed of an oxide film is deposited on the nitride film 4.
이후에 도 1b에 도시한 바와 같이 제 1 층간절연막(3)과 질화막(4)과 제 2층간절연막(5)을 식각하여서 게이트전극(2) 및 반도체기판(11)의 소정상부가 노출되도록 콘택홀(6)을 형성한다.Subsequently, as shown in FIG. 1B, the first interlayer insulating film 3, the nitride film 4, and the second interlayer insulating film 5 are etched to expose a predetermined upper portion of the gate electrode 2 and the semiconductor substrate 11. The hole 6 is formed.
다음에 도 1c에 도시한 바와 같이 후처리공정을 진행한다.Next, as shown in FIG. 1C, a post-treatment process is performed.
후처리공정에는 콘택홀을 세정하기 위한 세정공정과 차후에 베리어금속층을 형성하기 전에 행하는 전세공정이 있다. 예를 들어 세정공정에는 스탠다드 클리닝1(Standard Cleaning1:SC1)과 스탠다드 클리닝2(Standard Cleaning2:SC2) 용액을 사용하고, 전세공정에는 불산(HF)이나 BOE(Buffered Oxide Etcher)용액을 사용한다. 이와 같은 세정공정과 전세공정과 같은 후처리공정에서는 질화막보다 산화막이 더 식각되는 경향이 있다.The post-treatment step includes a cleaning step for cleaning the contact hole and a chartering step performed before the barrier metal layer is subsequently formed. For example, Standard Cleaning 1 (SC1) and Standard Cleaning 2 (SC2) solutions are used for the cleaning process, and hydrofluoric acid (HF) or BOE (Buffered Oxide Etcher) solutions are used for the charter process. In the post-treatment process such as the cleaning process and the charter process, the oxide film tends to be etched more than the nitride film.
따라서, 제 1, 제 2 층간절연막(3,5)이 질화막(4)보다 좀더 식각되어서 질화막이 돌출되는 형상이 나타난다.Accordingly, the first and second interlayer insulating films 3 and 5 are etched more than the nitride film 4 so that the nitride film protrudes.
이후에 콘택홀(6)을 따라서 베리어금속층을 증착한 후에 베리어금속층상에 금속을 증착하여 금속배선을 형성한다.(도면에는 도시되지 않았음)Subsequently, a barrier metal layer is deposited along the contact hole 6, and then metal is deposited on the barrier metal layer to form a metal wiring (not shown).
상기와 같이 종래 반도체소자의 콘택형성방법은 다음과 같은 문제가 있다.As described above, the conventional method for forming a contact of a semiconductor device has the following problems.
첫째, 콘택홀 내의 돌출된 질화막에 의해 콘택홀내에 베리어금속층을 증착하기가 어렵다.First, it is difficult to deposit the barrier metal layer in the contact hole by the protruding nitride film in the contact hole.
둘째, 돌출된 질화막에 의해서 불완전하게 베리어금속층이 증착되었을 경우에는 콘택저항이 증가하거나 분화구(volcano) 모양의 베리어금속층이 형성되는 문제가 있다.Second, when the barrier metal layer is incompletely deposited by the protruding nitride film, there is a problem in that contact resistance is increased or a barrier metal layer having a volcano shape is formed.
셋째, 상기와 같은 돌출된 질화막을 갖으며 큰 종횡비(aspect ratio)를 갖는 콘택홀에 베리어금속층을 형성하기 위해서는 별도의 새로운 장비가 요구된다.Third, separate new equipment is required to form the barrier metal layer in the contact hole having the protruding nitride film as described above and having a large aspect ratio.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 돌출부가 없는 균일한 콘택 프로파일을 갖는 콘택홀을 형성하기에 알맞은 반도체소자의 콘택형성방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for forming a semiconductor device suitable for forming a contact hole having a uniform contact profile without a protrusion.
도 1a 내지 도 1c는 종래 반도체소자의 콘택형성방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method for forming a contact in a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명 반도체소자의 콘택형성방법을 나타낸 공정단면도2A through 2C are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
11 : 반도체기판 12 : 게이트전극11 semiconductor substrate 12 gate electrode
13 : 제 1 층간절연막 14 : 질화막13 first interlayer insulating film 14 nitride film
15 : 제 2 층간절연막 16 : 콘택홀15: second interlayer insulating film 16: contact hole
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 콘택형성방법은 반도체기판에 제 1 층간절연막을 증착하는 단계, 상기 제 1 층간절연막과 식각선택비가 다른 제 2 층간절연막을 증착하는 단계, 상기 제 2 층간절연막상에 상기 제 1 층간절연막과 식각선택비가 동일한 제 3 층간절연막을 증착하는 단계, 상기 제 1, 제 3 층간절연막보다 상기 제 2 층간절연막의 식각선택성이 더 좋은 식각가스를 사용하여 상기 제 1, 제 3 층간절연막이 상기 제 2 층간절연막보다 돌출되도록 콘택홀을 형성하는 단계, 후처리공정으로 상기 콘택홀내에 돌출된 상기 제 1, 제 3 층간절연막을 식각하여 돌출부위없는 콘택 프로파일을 형성하는 것을 특징으로 한다.The method of forming a contact of a semiconductor device according to the present invention for achieving the above object comprises the steps of: depositing a first interlayer insulating film on a semiconductor substrate; depositing a second interlayer insulating film having a different etching selectivity from the first interlayer insulating film; Depositing a third interlayer dielectric layer having the same etching selectivity as the first interlayer dielectric layer on a second interlayer dielectric layer, using an etching gas having better etching selectivity of the second interlayer dielectric layer than the first and third interlayer dielectric layers; Forming a contact hole so that the first and third interlayer insulating films protrude from the second interlayer insulating film, and etching the first and third interlayer insulating films protruding into the contact holes in a post-processing step to form a contact profile without protrusions. It is characterized by forming.
첨부 도면을 참조하여 본 발명 반도체소자의 콘택형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method for forming a contact of a semiconductor device according to the present invention will be described.
도 2a 내지 도 2c는 본 발명 반도체소자의 콘택형성방법을 나타낸 공정단면도이다.2A to 2C are cross-sectional views illustrating a method for forming a contact of a semiconductor device according to the present invention.
본 발명 반도체소자의 콘택형성방법은 도 2a에 도시한 바와 같이 반도체기판(11)에 게이트전극(12)을 형성한다. 이후에 게이트전극(12) 상부에서 산화막으로 형성된 제 1 층간절연막(13)을 증착하고, 제 1 층간절연막(13)상부에 질화막(14)을 증착한다. 그리고 질화막(14)상에 산화막으로 형성된 제 2 층간절연막(15)을 증착한다.In the method for forming a contact of a semiconductor device of the present invention, as shown in FIG. 2A, a gate electrode 12 is formed on a semiconductor substrate 11. Thereafter, a first interlayer insulating film 13 formed of an oxide film is deposited on the gate electrode 12, and a nitride film 14 is deposited on the first interlayer insulating film 13. A second interlayer insulating film 15 formed of an oxide film is deposited on the nitride film 14.
다음에 도 2b에 도시한 바와 같이 CH2F2가스를 포함한 식각가스를 이용하여 제 1, 제 2 층간절연막(13,15)이 질화막(14)보다 돌출되도록 콘택홀(16)을 형성된다.Next, as shown in FIG. 2B, the contact holes 16 are formed such that the first and second interlayer insulating films 13 and 15 protrude from the nitride film 14 by using an etching gas containing a CH 2 F 2 gas.
여기서 콘택홀(16)은 반도체기판(11)이나 게이트전극(12)의 상부가 노출되도록 형성한다.The contact hole 16 is formed to expose the upper portion of the semiconductor substrate 11 or the gate electrode 12.
상기와 같이 제 1, 제 2 층간절연막(13,15)이 질화막(14)보다 돌출되는 이유는 CH2F2가스에 대한 질화막(14)의 식각비(Etch rate)가 산화막보다 2000Å이상 빠르기 때문이다.As described above, the first and second interlayer insulating films 13 and 15 protrude from the nitride film 14 because the etching rate of the nitride film 14 to the CH 2 F 2 gas is 2000 kPa or more faster than the oxide film. to be.
이때 CH2F2가스와 함께 사용되는 가스 조합으로는 Ar과 CHF3와 O2가스가 있다.At this time, the gas combination used with the CH 2 F 2 gas is Ar, CHF 3 and O 2 gas.
여기서 CH2F2가스 대신에 산화막에 비해서 질화막의 식각선택성이 더 좋은 다른 화학가스를 사용할 수 있다.Instead of the CH 2 F 2 gas, another chemical gas having better etching selectivity of the nitride film may be used as compared to the oxide film.
다음에 도 2c에 도시한 바와 같이 후처리공정을 진행한다.Next, as shown in FIG. 2C, a post-processing process is performed.
후처리공정에는 콘택홀을 세정하기 위한 세정공정과 차후에 베리어금속층을 형성하기 전에 행하는 전세공정이 있다. 예를 들어 세정공정에는 스탠다드 클리닝1(Standard Cleaning1:SC1)과 스탠다드 클리닝2(Standard Cleaning2:SC2) 용액을 사용하고, 전세공정에는 불산(HF)이나 BOE(Buffered Oxide Etcher)용액을 사용한다. 이와 같은 세정공정과 전세공정을 하면 질화막보다 산화막이 더 식각되는 경향이 있다.The post-treatment step includes a cleaning step for cleaning the contact hole and a chartering step performed before the barrier metal layer is subsequently formed. For example, Standard Cleaning 1 (SC1) and Standard Cleaning 2 (SC2) solutions are used for the cleaning process, and hydrofluoric acid (HF) or BOE (Buffered Oxide Etcher) solutions are used for the charter process. When the cleaning process and the chartering process are performed, the oxide film tends to be etched more than the nitride film.
따라서 상기 돌출되어 있는 제 1, 제 2 층간절연막(13,15)이 질화막(14)보다 더 식각되어서 돌출된 부분이 없어진 균일한 콘택프로파일이 형성된다.Accordingly, the protruding first and second interlayer insulating films 13 and 15 are etched more than the nitride film 14 to form a uniform contact profile in which the protruding portions are eliminated.
이후에 콘택홀(16)을 따라서 베리어금속층을 증착한 후에 베리어금속층상에 금속을 증착하여 배선을 형성한다.(도면에는 도시되는 않았음)Thereafter, a barrier metal layer is deposited along the contact hole 16, and then metal is deposited on the barrier metal layer to form a wiring (not shown).
그리고 콘택홀이 아닌 라인형성공정이나 격리막 형성공정에도 상기와 같은 공정을 사용할 수 있으며, 또한 산화막과 질화막처럼 서로 다른 식각선택비를 갖는 필름을 이용할 때 상기와 같은 공정을 진행할 수 있다.In addition, the above process may be used in a line forming process or an isolation layer forming process instead of a contact hole, and the above process may be performed when using films having different etching selectivities such as oxide and nitride layers.
상기와 같은 본 발명 반도체소자의 콘택형성방법은 다음과 같은 효과가 있다.The contact forming method of the semiconductor device of the present invention as described above has the following effects.
첫째, 돌출된 부분 없이 깨끗한 콘택프로파일을 얻을 수 있으므로 콘택저항이 증가하는 것을 방지할 수 있다.First, since a clean contact profile can be obtained without protruding portions, an increase in contact resistance can be prevented.
둘째, 높은 종횡비를 갖는 콘택홀에서도 쉽게 베리어금속층을 형성할 수 있다.Second, the barrier metal layer can be easily formed even in a contact hole having a high aspect ratio.
셋째, 콘택홀내에 베리어금속층을 형성하기위해서 추가적인 장비를 사용하지 않아도 된다.Third, it is not necessary to use additional equipment to form the barrier metal layer in the contact hole.
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| KR1019980036577A KR100290231B1 (en) | 1998-09-04 | 1998-09-04 | Method for forming contact of semiconductor device |
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