KR100286773B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100286773B1 KR100286773B1 KR1019980055660A KR19980055660A KR100286773B1 KR 100286773 B1 KR100286773 B1 KR 100286773B1 KR 1019980055660 A KR1019980055660 A KR 1019980055660A KR 19980055660 A KR19980055660 A KR 19980055660A KR 100286773 B1 KR100286773 B1 KR 100286773B1
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- Prior art keywords
- film
- polysilicon
- forming
- thickness
- gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 229920005591 polysilicon Polymers 0.000 claims abstract description 43
- 239000010410 layer Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 17
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 14
- 239000010937 tungsten Substances 0.000 claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000010405 reoxidation reaction Methods 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 230000008719 thickening Effects 0.000 claims 1
- 238000009279 wet oxidation reaction Methods 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 150000003657 tungsten Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 폴리실리콘막과 텅스텐막의 적층구조의 게이트에서, 재산화 공정을 배제하지 않고, 재산화공정시 텅스텐막의 산화를 효과적으로 방지할 수 있는 반도체 소자의 제조방법을 제공한다.The present invention provides a method for manufacturing a semiconductor device in the gate of a laminated structure of a polysilicon film and a tungsten film, which can effectively prevent the oxidation of the tungsten film during the reoxidation process without excluding the reoxidation process.
본 발명에 따른 반도체 소자의 제조방법은 반도체 기판 상에 게이트 산화막 및 폴리실리콘막을 순차적으로 형성하는 단계; 폴리실리콘막 및 게이트 산화막의 게이트의 형태로 패터닝하여 하부 게이트층을 형성하는 단계; 결과물 구조의 기판을 재산화하여 하부 게이트층의 측벽 및 노출된 기판에 산화막을 형성하는 단계; 하부 게이트층의 측벽에 절연막 스페이서를 형성하는 단계; 결과물 구조의 기판 상에 폴리실리콘막의 표면이 노출되도록 층간절연막을 형성하는 단계; 폴리실리콘막을 소정 두께만큼 부분식각하는 단계; 및, 부분식각된 폴리실리콘막 상에 저저항 금속막을 선택적으로 형성하여 게이트를 형성하는 단계를 포함한다. 본 실시예에서, 저저항 금속막은 텅스텐막 또는 금속 실리사이드막으로 500 내지 2,000Å의 두께로 형성하고, 폴리실리콘막은 500 내지 3,000Å의 두께로 형성하고, 폴리실리콘막의 부분식각은 건식 또는 습식식각으로 진행하여, 200 내지 1,000Å의 두께만큼 부분식각한다.A method of manufacturing a semiconductor device according to the present invention includes the steps of sequentially forming a gate oxide film and a polysilicon film on a semiconductor substrate; Patterning in the form of a gate of a polysilicon film and a gate oxide film to form a lower gate layer; Reoxidizing the substrate of the resulting structure to form an oxide film on the sidewalls of the lower gate layer and the exposed substrate; Forming insulating film spacers on sidewalls of the lower gate layer; Forming an interlayer insulating film on the substrate having the resulting structure so as to expose the surface of the polysilicon film; Partially etching the polysilicon film by a predetermined thickness; And selectively forming a low resistance metal film on the partially etched polysilicon film to form a gate. In this embodiment, the low resistance metal film is formed of a tungsten film or a metal silicide film with a thickness of 500 to 2,000 kPa, the polysilicon film is formed with a thickness of 500 to 3,000 kPa, and the partial etching of the polysilicon film is dry or wet etching. It proceeds and partially etches by the thickness of 200-1,000 micrometers.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 텅스텐막과 실리콘막의 적층구조의 게이트를 이용한 고집적 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a highly integrated semiconductor device using a gate having a laminated structure of a tungsten film and a silicon film.
일반적으로, 게이트는 모스 트랜지스터를 셀렉팅하는 전극으로서, 낮은 면저항 값을 갖는 것이 중요하다. 이에 대하여, 고집적 반도체 소자에서는 게이트 물질로서 도핑된 실리콘막 상부에 텅스텐막을 적층하여 형성하였다.In general, the gate is an electrode for selecting a MOS transistor, and it is important to have a low sheet resistance value. In contrast, in the highly integrated semiconductor device, a tungsten film was formed by laminating a silicon film doped as a gate material.
도 1은 상기한 구조의 게이트를 적용한 종래의 반도체 소자의 제조방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a conventional method of manufacturing a semiconductor device to which the gate of the above structure is applied.
도 1을 참조하면, 반도체 기판(1) 상에 게이트 산화막(2), 도핑된 폴리실리콘막(3), 배리어 금속막(4), 텅스텐막(5), 및 마스크 절연막(6)을 순차적으로 형성한다. 여기서, 배리어 금속막(4)은 티타늄 실리사이드막(5)의 티타늄이 열공정에 의해 게이트 산화막(2)으로 침투하는 것을 방지하여, 게이트 산화막의 GOI(gate oxide integrity)를 향상시키는 막으로서, TiN막으로 형성한다. 또한, 마스크 절연막(6)은 금속의 반사를 방지한다.Referring to FIG. 1, a gate oxide film 2, a doped polysilicon film 3, a barrier metal film 4, a tungsten film 5, and a mask insulating film 6 are sequentially formed on a semiconductor substrate 1. Form. Here, the barrier metal film 4 is a film that prevents titanium from the titanium silicide film 5 from penetrating into the gate oxide film 2 by a thermal process, thereby improving the gate oxide integrity (GOI) of the gate oxide film. Form into a film. In addition, the mask insulating film 6 prevents the reflection of the metal.
그런 다음, 마스크 절연막(6), 텅스텐막(5), 배리어 금속막(4), 폴리실리콘막(3), 및 게이트 산화막(2)을 패터닝하여 게이트를 형성한다. 그런 다음, 게이트 형성을 위한 식각시, 막들 표면에 발생된 데미지(demage) 및 식각 잔재물을 제거하고, 게이트 산화막(2)의 신뢰성을 회복하기 위하여, 재산화 공정을 진행하여 게이트의 측벽 및 노출된 기판 표면에 산화막(7)을 형성한다.Then, the mask insulating film 6, the tungsten film 5, the barrier metal film 4, the polysilicon film 3, and the gate oxide film 2 are patterned to form a gate. Then, during etching to form the gate, damage and etching residues generated on the surfaces of the films are removed, and in order to restore the reliability of the gate oxide film 2, a reoxidation process is performed to remove the sidewalls of the gate and exposed portions. An oxide film 7 is formed on the substrate surface.
그러나, 상기한 구조의 게이트에서는 재산화 공정시, 텅스텐막의 빠른 산화속도로 인하여 부피팽창이 야기되어 도 1에 도시된 바와 같이 게이트 패턴이 변형되는 문제가 발생된다. 이를 방지하기 위하여 재산화 공정을 배제하게 되면, 게이트 산화막의 특성저하가 야기된다.However, in the gate of the above structure, during the reoxidation process, volume expansion is caused due to the rapid oxidation rate of the tungsten film, which causes a problem that the gate pattern is deformed as shown in FIG. 1. If the reoxidation process is excluded in order to prevent this, deterioration of the characteristics of the gate oxide film is caused.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 폴리실리콘막과 텅스텐막의 적층구조의 게이트에서, 재산화 공정을 배제하지 않고, 재산화공정시 텅스텐막의 산화를 효과적으로 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned conventional problems, and in the gate of the laminated structure of the polysilicon film and the tungsten film, a semiconductor device capable of effectively preventing the oxidation of the tungsten film during the reoxidation process without excluding the reoxidation process. The purpose is to provide a method of manufacturing.
도 1은 종래의 반도체 소자의 제조방법을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]
11 : 반도체 기판 12 : 게이트 산화막11 semiconductor substrate 12 gate oxide film
13, 13a : 도핑된 폴리실리콘막13, 13a: doped polysilicon film
14 : 스페이서14: spacer
15 : 층간절연막 16 : 저저항 금속막15: interlayer insulating film 16: low resistance metal film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 반도체 기판 상에 게이트 산화막 및 폴리실리콘막을 순차적으로 형성하는 단계; 폴리실리콘막 및 게이트 산화막의 게이트의 형태로 패터닝하여 하부 게이트층을 형성하는 단계; 결과물 구조의 기판을 재산화하여 하부 게이트층의 측벽 및 노출된 기판에 산화막을 형성하는 단계; 하부 게이트층의 측벽에 절연막 스페이서를 형성하는 단계; 결과물 구조의 기판 상에 폴리실리콘막의 표면이 노출되도록 층간절연막을 형성하는 단계; 폴리실리콘막을 소정 두께만큼 부분식각하는 단계; 및, 부분식각된 폴리실리콘막 상에 저저항 금속막을 선택적으로 형성하여 게이트를 형성하는 단계를 포함한다.A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of sequentially forming a gate oxide film and a polysilicon film on a semiconductor substrate; Patterning in the form of a gate of a polysilicon film and a gate oxide film to form a lower gate layer; Reoxidizing the substrate of the resulting structure to form an oxide film on the sidewalls of the lower gate layer and the exposed substrate; Forming insulating film spacers on sidewalls of the lower gate layer; Forming an interlayer insulating film on the substrate having the resulting structure so as to expose the surface of the polysilicon film; Partially etching the polysilicon film by a predetermined thickness; And selectively forming a low resistance metal film on the partially etched polysilicon film to form a gate.
본 실시예에서, 저저항 금속막은 텅스텐막 또는 금속 실리사이드막으로 500 내지 2,000Å의 두께로 형성하고, 폴리실리콘막은 500 내지 3,000Å의 두께로 형성하고, 폴리실리콘막의 부분식각은 건식 또는 습식식각으로 진행하여, 200 내지 1,000Å의 두께만큼 부분식각한다.In this embodiment, the low resistance metal film is formed of a tungsten film or a metal silicide film with a thickness of 500 to 2,000 kPa, the polysilicon film is formed with a thickness of 500 to 3,000 kPa, and the partial etching of the polysilicon film is dry or wet etching. It proceeds and partially etches by the thickness of 200-1,000 micrometers.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(11) 상에 게이트 산화막(12) 및 도핑된 폴리실리콘막(13)을 순차적으로 형성한다. 여기서, 게이트 산화막(12)은 50 내지 100Å의 두께로 형성하고, 폴리실리콘막(13)은 500 내지 3,000Å의 두께로 형성한다. 폴리실리콘막(13) 상부에 포토리소그라피로 게이트용 마스크 패턴(미도시)을 형성하고, 상기 마스크 패턴을 이용하여 폴리실리콘막(13) 및 게이트 산화막(12)을 식각하여 하부 게이트층을 형성한다. 그런 다음, 공지된 방법으로 상기 마스크 패턴을 제거하고, 상기 하부 게이트 형성을 위한 식각시 막들 표면에 발생된 데미지 및 식각 잔재물을 제거하고, 게이트 산화막(12)의 신뢰성을 회복하기 위하여, 건식 또는 습식산화 공정으로 재산화(re-oxidation) 공정을 진행하여 하부 게이트층의 측벽 및 노출된 기판에 10 내지 300Å의 두께로 산화막(미도시)을 형성한다.Referring to FIG. 2A, a gate oxide layer 12 and a doped polysilicon layer 13 are sequentially formed on the semiconductor substrate 11. Here, the gate oxide film 12 is formed to a thickness of 50 to 100 GPa, and the polysilicon film 13 is formed to a thickness of 500 to 3,000 GPa. A photolithography gate mask pattern (not shown) is formed on the polysilicon layer 13, and the polysilicon layer 13 and the gate oxide layer 12 are etched using the mask pattern to form a lower gate layer. . Then, to remove the mask pattern by a known method, to remove damage and etching residues generated on the surface of the film during the etching for forming the lower gate, to restore the reliability of the gate oxide film 12, dry or wet An oxidation process is performed to re-oxidation to form an oxide film (not shown) on the sidewall of the lower gate layer and the exposed substrate with a thickness of 10 to 300 kPa.
도 2b를 참조하면, 기판 전면에 스페이서용 절연막을 두껍게 증착하고, 이방성 블랭킷 식각하여, 하부 게이트의 측벽에 스페이서(14)를 형성한다. 스페이서용 절연막은 예컨대 산화막, 질화막 또는 산화막과 질화막의 적층막 중 선택되는 하나의 막으로 200 내지 1,000Å의 두께로 형성한다. 그런 다음, 기판 전면에 층간절연막(15)을 증착하고 화학기계연마(Chemical Mechanical Polishing)로 전면 식각하여, 폴리실리콘막(13)의 표면을 노출시킨다.Referring to FIG. 2B, a spacer insulating film is thickly deposited on the entire surface of the substrate, and anisotropic blanket etching is performed to form the spacer 14 on the sidewall of the lower gate. The insulating film for the spacer is, for example, one film selected from an oxide film, a nitride film, or a laminated film of an oxide film and a nitride film, and is formed to have a thickness of 200 to 1,000 mW. Then, an interlayer insulating film 15 is deposited on the entire surface of the substrate and etched by chemical mechanical polishing to expose the surface of the polysilicon film 13.
그리고 나서, 도 2c에 도시된 바와 같이, 노출된 폴리실리콘막(13)을 건식 또는 습식식각으로 소정 두께, 바람직하게 200 내지 1,000Å의 두께만큼 부분식각한다. 그런 다음, 도 2d에 도시된 바와 같이, 부분식각된 폴리실리콘막(13) 상부에 상부 게이트층인 저저항 금속막(16)을 선택적으로 형성하여 게이트를 완성한다. 여기서, 저저항 금속막(16)은 텅스텐막 또는 금속 실리사이드막으로 500 내지 2,000Å의 두께로 형성한다.Then, as shown in FIG. 2C, the exposed polysilicon film 13 is partially etched by a predetermined thickness, preferably 200 to 1,000 mm 3, by dry or wet etching. Then, as shown in FIG. 2D, a low resistance metal film 16, which is an upper gate layer, is selectively formed on the partially etched polysilicon film 13 to complete the gate. Here, the low resistance metal film 16 is formed of a tungsten film or a metal silicide film with a thickness of 500 to 2,000 kPa.
한편, 도시되지는 않았지만, 저저항 금속막(16)과 폴리실리콘막(13) 사이에 이온확산을 방지하기 위한 별도의 배리어 금속막을 개재하여 형성할 수 있다. 여기서, 배리어 금속막은 TiN막 또는 WN막을 이용하여 10 내지 500Å의 두께로 형성한다.Although not shown, a low barrier metal film 16 may be formed between the low resistance metal film 16 and the polysilicon film 13 through an additional barrier metal film for preventing ion diffusion. Here, the barrier metal film is formed to a thickness of 10 to 500 kV using a TiN film or a WN film.
또한, 도시되지는 않았지만, 폴리실리콘막(13)의 부분식각 대신에, 폴리실리콘막의 식각 두께를 용이하게 조절하기 위하여, 폴리실리콘막(13)의 원하는 식각 두께만큼의 절연막을 폴리실리콘막(13) 상부에 미리 형성한 후 층간절연막(15)의 형성 후 제거하는 방법을 이용하거나, 폴리실리콘막(13)의 이중으로 형성하고, 그 의 사이에 식각정지층을 개재할 수 있다.Although not shown, instead of the partial etching of the polysilicon film 13, in order to easily adjust the etching thickness of the polysilicon film, an insulating film having a desired etching thickness of the polysilicon film 13 may be replaced with the polysilicon film 13. ) And a method of removing the interlayer insulating film 15 after formation in advance, or forming a double layer of the polysilicon film 13, and interposing an etch stop layer therebetween.
상기한 본 발명에 의하면, 폴리실리콘막만으로 이루어진 하부 게이트층을 먼저 형성하고, 재산화 공정을 진행한 후 선택적으로 상부 게이트층인 텅스텐막 또는 금속 실리사이드막과 같은 저저항 금속막을 형성하기 때문에, 저저항 금속막의 산화가 방지되므로, 게이트의 변형이 방지된다. 또한, 재산화를 용이하게 진행하기 때문에, 게이트 산화막의 특성저하가 방지된다.According to the present invention described above, since a lower gate layer consisting of only a polysilicon film is first formed, and then a reoxidation process is performed, a low resistance metal film such as a tungsten film or a metal silicide film, which is an upper gate layer, is selectively formed. Since oxidation of the resistive metal film is prevented, deformation of the gate is prevented. In addition, since the reoxidation proceeds easily, the deterioration of the characteristics of the gate oxide film is prevented.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
Claims (13)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980055660A KR100286773B1 (en) | 1998-12-17 | 1998-12-17 | Manufacturing method of semiconductor device |
| TW088119191A TW452869B (en) | 1998-12-17 | 1999-11-04 | Method of forming gate electrode in semiconductor device |
| US09/434,755 US20020001935A1 (en) | 1998-12-17 | 1999-11-05 | Method of forming gate electrode in semiconductor device |
| JP11322991A JP2000183347A (en) | 1998-12-17 | 1999-11-12 | Method for forming gate electrode of semiconductor element |
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| KR1019980055660A KR100286773B1 (en) | 1998-12-17 | 1998-12-17 | Manufacturing method of semiconductor device |
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| KR20000040108A KR20000040108A (en) | 2000-07-05 |
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| KR102171023B1 (en) | 2014-07-21 | 2020-10-29 | 삼성전자주식회사 | Method of fabricating semiconductor devices |
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