KR100275957B1 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistor Download PDFInfo
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- KR100275957B1 KR100275957B1 KR1019980040984A KR19980040984A KR100275957B1 KR 100275957 B1 KR100275957 B1 KR 100275957B1 KR 1019980040984 A KR1019980040984 A KR 1019980040984A KR 19980040984 A KR19980040984 A KR 19980040984A KR 100275957 B1 KR100275957 B1 KR 100275957B1
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- layer
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- electrode layer
- ohmic contact
- gate insulating
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000010409 thin film Substances 0.000 title abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000000059 patterning Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 99
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 125000000896 monocarboxylic acid group Chemical group 0.000 claims description 2
- 229910017604 nitric acid Inorganic materials 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 239000010408 film Substances 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
Abstract
본 발명은 박막트랜지스터의 제조방법에 관한 것으로서 기판 상에 게이트를 형성하는 공정과, 상기 기판 상에 상기 게이트를 덮도록 형성된 게이트절연막, 활성층, 오믹접촉층 및 전극층을 순차적으로 형성하는 공정과, 상기 전극층, 오믹접촉층 및 활성층을 상기 게이트와 대응하는 부분이 남게 상기 게이트절연층이 노출되도록 패터닝하는 공정과, 상기 전극층의 상기 오믹접촉층의 양측을 덮는 포토레지스트를 사용하여 상기 전극층의 상기 게이트와 대응하는 부분을 패터닝하여 소오스 및 드레인전극을 형성하면서 상기 게이트절연층 상의 식각 잔유물을 제거하는 공정을 구비한다. 따라서, 게이트절연층 상에 전극층 등의 식각 잔유물이 잔류하지 않으므로 화소전극을 통한 광의 투과를 방해하거나 인접하는 다른 박막트랜지스터와 전기적으로 단락되는 등의 불량을 방지하여 수율을 향상시킬 수 있다.The present invention relates to a method of manufacturing a thin film transistor, the process of forming a gate on a substrate, a step of sequentially forming a gate insulating film, an active layer, an ohmic contact layer and an electrode layer formed to cover the gate on the substrate, Patterning an electrode layer, an ohmic contact layer, and an active layer so that the gate insulating layer is exposed so that a portion corresponding to the gate remains; and using the photoresist covering both sides of the ohmic contact layer of the electrode layer with the gate of the electrode layer; Patterning a corresponding portion to form source and drain electrodes and removing etch residues on the gate insulating layer. Therefore, since the etch residue such as the electrode layer does not remain on the gate insulating layer, it is possible to prevent a defect such as obstructing the transmission of light through the pixel electrode or electrically shorting with another adjacent thin film transistor, thereby improving the yield.
Description
본 발명은 박막트랜지스터의 제조방법에 관한 것으로서, 특히, 소오스 및 드레인전극을 2번의 패터닝에 의해 형성 할 수 있는 박막트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor capable of forming the source and drain electrodes by two patterning.
일반적으로 박막트랜지스터는 액정표시소자(Liquid Crystal Display : LCD)의 스위칭소자나 에스램(SRAM)의 부하트랜지스터로 사용된다.In general, the thin film transistor is used as a switching element of a liquid crystal display (LCD) or a load transistor of an SRAM.
상기에서 박막트랜지스터를 스위칭소자로 사용하는 액정표시소자는 화상 신호를 각 픽셀(Pixel) 영역으로 전달하여 화상을 표시한다. 화상은 화상신호의 레벨에 따라 투과되는 광의 량을 조절하므로 박형화가 가능하여 벽걸이 TV나 PC 등에 사용될 수 있다.The liquid crystal display device using the thin film transistor as the switching device transmits an image signal to each pixel area to display an image. Since the image adjusts the amount of light transmitted according to the level of the image signal, the image can be thinned and used for a wall-mounted TV or a PC.
도 1a 내지 도 1c는 종래 기술에 따른 박막트랜지스터의 공정도이다.1A to 1C are process diagrams of a thin film transistor according to the prior art.
도 1a를 참조하면, 절연 특성을 갖는 투명기판(11) 상에 알루미늄, 구리 또는 금 등과 같은 도전성금속을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법이나, 또는, 스퍼터링(sputtering) 방법으로 증착한다. 그리고, 도전성 금속을 반응성이온에칭(Reactive Ion Etching : 이하, RIE라 칭함)을 포함하는 포토리쏘그래피(photolithography) 방법으로 패터닝하여 게이트(13)를 형성한다.Referring to FIG. 1A, a method of chemical vapor deposition (hereinafter, referred to as CVD) of a conductive metal such as aluminum, copper, or gold on a transparent substrate 11 having insulating properties, or sputtering Deposition by the method. The conductive metal is patterned by a photolithography method including reactive ion etching (hereinafter referred to as RIE) to form the gate 13.
도 1b를 참조하면, 투명기판(11) 상에 게이트(13)를 덮도록 게이트절연층(15), 활성층(17) 및 오믹접촉층(19)을 순차적으로 형성한다. 상기에서 게이트절연층(15)은 Si3N4또는 SiO2등의 절연물질을, 활성층(17)은 비정질실리콘 또는 다결정실리콘을, 오믹접촉층(19)은 N형 또는 P형의 불순물이 고농도로 도핑된 비정질실리콘 또는 다결정실리콘을 각각 CVD 방법으로 증착하므로써 형성된다.Referring to FIG. 1B, the gate insulating layer 15, the active layer 17, and the ohmic contact layer 19 are sequentially formed on the transparent substrate 11 to cover the gate 13. In the above, the gate insulating layer 15 is an insulating material such as Si 3 N 4 or SiO 2 , the active layer 17 is amorphous silicon or polycrystalline silicon, and the ohmic contact layer 19 is a high concentration of N-type or P-type impurities Are formed by depositing amorphous silicon or polycrystalline silicon doped with CVD, respectively.
오믹접촉층(19) 및 활성층(17)을 게이트(13)과 대응하는 부분이 남도록 포토리쏘그래피 방법으로 패터닝한다.The ohmic contact layer 19 and the active layer 17 are patterned by a photolithography method so that portions corresponding to the gate 13 remain.
도 1c를 참조하면, 게이트절연층(15) 및 오믹접촉층(19) 상에 Mo, W, Ta, Cr 또는 Ti 등의 고융점 금속을 CVD 방법 또는 스퍼터링 방법으로 증착하여 전극층을 형성한다. 그리고, 전극층과 오믹접촉층(19)을 활성층(17)의 게이트(13)과 대응하는 부분이 노출되도록 포토리쏘그래피 방법으로 패터닝하여 소오스 및 드레인전극(21)(22)을 형성한다. 상기에서 소오스 및 드레인전극(21)(22) 사이의 활성층(17)의 노출된 부분은 채널영역이 된다.Referring to FIG. 1C, a high melting point metal such as Mo, W, Ta, Cr, or Ti is deposited on the gate insulating layer 15 and the ohmic contact layer 19 by a CVD method or a sputtering method to form an electrode layer. The electrode layer and the ohmic contact layer 19 are patterned by photolithography such that portions corresponding to the gate 13 of the active layer 17 are exposed to form source and drain electrodes 21 and 22. The exposed portion of the active layer 17 between the source and drain electrodes 21 and 22 becomes a channel region.
그러나, 종래 기술에 따른 박막트랜지스터의 제조방법은 전극층을 패터닝하여 소오스 및 드레인전극을 형성할 때 게이트절연층 상에 전극층 등의 식각 잔유물이 잔류하여 화소전극을 통한 광의 투과를 방해할 뿐만 아니라 인접하는 다른 박막트랜지스터와 전기적으로 단락되는 불량이 발생되어 수율이 저하되는 문제점이 있었다.However, in the method of manufacturing a thin film transistor according to the related art, when forming the source and drain electrodes by patterning the electrode layer, etch residues such as the electrode layer remain on the gate insulating layer to prevent the light transmission through the pixel electrode, There is a problem in that the yield is lowered due to a defect that is electrically shorted with other thin film transistors.
따라서, 본 발명의 목적은 소오스 및 드레인전극을 형성할 때 게이트절연층 상에 전극층 등의 식각 잔유물에 의한 불량을 방지하여 수율을 향상시킬 수 있는 박막트랜지스터의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor which can improve the yield by preventing defects caused by etching residues such as electrode layers on the gate insulating layer when forming the source and drain electrodes.
상기 목적을 달성하기 위해 본 발명에 따른 박막트랜지스터의 제조방법은 기판 상에 게이트를 형성하는 공정과, 상기 기판 상에 상기 게이트를 덮도록 형성된 게이트절연막, 활성층, 오믹접촉층 및 전극층을 순차적으로 형성하는 공정과, 상기 전극층, 오믹접촉층 및 활성층을 상기 게이트와 대응하는 부분이 남게 상기 게이트절연층이 노출되도록 패터닝하는 공정과, 상기 전극층의 상기 오믹접촉층의 양측을 덮는 포토레지스트를 사용하여 상기 전극층의 상기 게이트와 대응하는 부분을 패터닝하여 소오스 및 드레인전극을 형성하면서 상기 게이트절연층 상의 식각 잔유물을 제거하는 공정을 구비한다.In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention includes forming a gate on a substrate, and sequentially forming a gate insulating film, an active layer, an ohmic contact layer, and an electrode layer formed to cover the gate on the substrate. And patterning the electrode layer, the ohmic contact layer, and the active layer to expose the gate insulating layer so that a portion corresponding to the gate remains, and using a photoresist covering both sides of the ohmic contact layer of the electrode layer. Patterning a portion corresponding to the gate of the electrode layer to form source and drain electrodes, and removing etch residues on the gate insulating layer.
도 1a 내지 도 1c는 종래 기술에 따른 박막트랜지스터의 공정도1a to 1c is a process diagram of a thin film transistor according to the prior art
도 2a 내지 도 2c는 본 발명에 따른 박막트랜지스터의 공정도2a to 2c is a process diagram of a thin film transistor according to the present invention
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 22는 본 발명에 따른 박막트랜지스터의 공정도이다.2A to 22 are process diagrams of a thin film transistor according to the present invention.
도 2a를 참조하면, 절연 특성을 갖는 투명기판(31) 상에 알루미늄, 구리 또는 금 등과 같은 도전성금속을 CVD 방법이나, 또는, 스퍼터링 방법으로 증착한다. 그리고, 도전성 금속을 RIE을 포함하는 포토리쏘그래피 방법으로 패터닝하여 게이트(33)를 형성한다.Referring to FIG. 2A, a conductive metal such as aluminum, copper, or gold is deposited on the transparent substrate 31 having insulating properties by a CVD method or a sputtering method. The conductive metal is patterned by a photolithography method including RIE to form the gate 33.
도 2b를 참조하면, 투명기판(31) 상에 게이트(33)를 덮도록 게이트절연층(35), 활성층(37), 오믹접촉층(39) 및 전극층(41)을 순차적으로 형성한다. 상기에서 게이트절연층(35)은 Si3N4또는 SiO2등의 절연물질을, 활성층(37)은 비정질실리콘 또는 다결정실리콘을, 오믹접촉층(39)은 N형 또는 P형의 불순물이 고농도로 도핑된 비정질실리콘 또는 다결정실리콘을 각각 CVD 방법으로 증착하므로써 형성된다. 또한, 전극층(41)은 Mo, W, Ta, Cr 또는 Ti 등의 고융점 금속을 CVD 방법 또는 스퍼터링 방법으로 증착하여 형성한다. 상기에서 전극층(41)을 단일층으로 형성하였으나 Mo, W, Ta, Cr 또는 Ti 등의 고융점 금속과 알루미늄 또는 알루미늄 합금의 이중층으로 형성할 수도 있다.Referring to FIG. 2B, the gate insulating layer 35, the active layer 37, the ohmic contact layer 39, and the electrode layer 41 are sequentially formed on the transparent substrate 31 to cover the gate 33. In the above, the gate insulating layer 35 is an insulating material such as Si 3 N 4 or SiO 2 , the active layer 37 is amorphous silicon or polycrystalline silicon, and the ohmic contact layer 39 is a high concentration of N-type or P-type impurities Are formed by depositing amorphous silicon or polycrystalline silicon doped with CVD, respectively. In addition, the electrode layer 41 is formed by depositing a high melting point metal such as Mo, W, Ta, Cr, or Ti by a CVD method or a sputtering method. Although the electrode layer 41 is formed as a single layer, the electrode layer 41 may be formed as a double layer of a high melting point metal such as Mo, W, Ta, Cr, or Ti and aluminum or an aluminum alloy.
전극층(41), 오믹접촉층(39) 및 활성층(37)을 게이트(33)와 대응하는 부분이 남게 게이트절연층(35)이 노출되도록 포토리쏘그래피 방법으로 순차적으로 패터닝한다.The electrode layer 41, the ohmic contact layer 39, and the active layer 37 are sequentially patterned by a photolithography method so that the gate insulating layer 35 is exposed so that portions corresponding to the gate 33 remain.
상기에서 전극층(41)과 오믹접촉층(39) 및 활성층(37)의 반도체층을 'F(fluorine)'와 'Cl(chroline)'를 포함하는 가스를 혼합한 가스, 예를 들면, SF6+HCl로 연속 식각하여 패터닝한다.In the above, the semiconductor layer of the electrode layer 41, the ohmic contact layer 39, and the active layer 37 is mixed with a gas including 'F' (fluorine) and 'Cl (chroline)', for example, SF 6. Pattern by continuous etching with + HCl.
또한, 전극층(41)와 오믹접촉층(39) 및 활성층(37)의 반도체층을 각각의 식각 방법으로 패터닝할 수도 있다. 즉, 전극층(41)을 'F'를 포함하는 가스, 예를 들면, SF6또는 CF4등의 가스, 또는, 'Cl'를 포함하는 가스, 예를 들면, HCl, Cl2또는 BCl3등의 가스를 사용하는 건식식각방법이나, 또는, 인산(H3PO4)+질산(HNO3)+초산(CH3COOH)을 혼합한 식각용액으로 습식식각하여 패터닝한다. 그리고, 오믹접촉층(39) 및 활성층(37)의 반도체층을 'Cl'를 포함하는 가스, 예를 들면, HCl, Cl2또는 BCl3등의 가스를 사용하는 건식식각방법으로 패터닝한다.In addition, the semiconductor layers of the electrode layer 41, the ohmic contact layer 39, and the active layer 37 may be patterned by respective etching methods. That is, the electrode layer 41 is a gas containing 'F', for example, a gas such as SF 6 or CF 4 , or a gas containing 'Cl', for example, HCl, Cl 2, or BCl 3 . Dry etching method using gas or wet etching with an etching solution containing phosphoric acid (H 3 PO 4 ) + nitric acid (HNO 3 ) + acetic acid (CH 3 COOH) is patterned. The ohmic contact layer 39 and the semiconductor layer of the active layer 37 are patterned by a dry etching method using a gas containing 'Cl', for example, a gas such as HCl, Cl 2, or BCl 3 .
도 2c를 참조하면, 전극층(41)을 오믹접촉층(39)의 양측에만 잔류하도록 게이트(33)와 대응하는 부분을 포토리쏘그래피 방법으로 패터닝하여 소오스 및 드레인전극(43)(44)을 형성한다. 상기에서 마스크로 사용되는 포토레지스트(도시되지 않음)를 게이트절연층(35)이 노출되도록 전극층(41) 상의 소오스 및 드레인전극(43)(44)이 형성될 부분에만 형성한다. 그러므로, 전극층(41)을 패터닝하여 소오스 및 드레인전극(43)(44)을 형성할 때 게이트절연층(35) 상에 잔류될 수도 있는 전극층(41)의 식각 잔유물 등을 한 번 더 제거할 수 있다.Referring to FIG. 2C, the source and drain electrodes 43 and 44 are formed by patterning a portion corresponding to the gate 33 by photolithography so that the electrode layer 41 remains only on both sides of the ohmic contact layer 39. do. The photoresist (not shown) used as a mask is formed only at a portion where the source and drain electrodes 43 and 44 on the electrode layer 41 are to be exposed so as to expose the gate insulating layer 35. Therefore, when the electrode layer 41 is patterned to form the source and drain electrodes 43 and 44, the etching residues of the electrode layer 41, which may remain on the gate insulating layer 35, may be removed once more. have.
상기에서 전극층(41)을 패터닝하여 소오스 및 드레인전극(43)(44)을 형성할 때 오믹접촉층(39)도 패터닝하여 활성층(37)을 노출시킨다. 소오스 및 드레인전극(43)(44)을 형성하기 위한 전극층(41)과 오믹접촉층(39)의 패터닝은 도 2b 공정에 사용한 패터닝 방법과 동일하게 진행한다.When the electrode layer 41 is patterned to form the source and drain electrodes 43 and 44, the ohmic contact layer 39 is also patterned to expose the active layer 37. The patterning of the electrode layer 41 and the ohmic contact layer 39 for forming the source and drain electrodes 43 and 44 proceeds in the same manner as the patterning method used in the FIG. 2B process.
상기에서 소오스 및 드레인전극(43)(44) 사이의 활성층(37)의 노출된 부분은 채널영역이 된다.The exposed portion of the active layer 37 between the source and drain electrodes 43 and 44 becomes a channel region.
상술한 바와 같이 본 발명은 전극층, 오믹접촉층 및 활성층을 게이트와 대응하는 부분이 남도록 패터닝할 때 노출되는 게이트절연층 상에 잔류되는 전극층 등의 식각 잔유물을 소오스 및 드레인전극을 형성하기 위해 전극층을 패터닝할 때 한 번 더 제거한다.As described above, the present invention provides an electrode layer for forming source and drain electrodes of an etch residue such as an electrode layer remaining on the gate insulating layer exposed when the electrode layer, the ohmic contact layer, and the active layer are patterned such that the portion corresponding to the gate remains. Remove it once more when patterning.
따라서, 본 발명은 게이트절연층 상에 전극층 등의 식각 잔유물이 잔류하지 않으므로 화소전극을 통한 광의 투과를 방해하거나 인접하는 다른 박막트랜지스터와 전기적으로 단락되는 등의 불량을 방지하여 수율을 향상시킬 수 있는 잇점이 있다.Therefore, since the etch residues such as the electrode layer do not remain on the gate insulating layer, the present invention can improve the yield by preventing defects such as obstructing light transmission through the pixel electrode or electrically shorting with another adjacent thin film transistor. There is an advantage.
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