KR100274353B1 - Method of manufacturing a capacitor in a semiconductor device - Google Patents

Method of manufacturing a capacitor in a semiconductor device Download PDF

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KR100274353B1
KR100274353B1 KR1019970079259A KR19970079259A KR100274353B1 KR 100274353 B1 KR100274353 B1 KR 100274353B1 KR 1019970079259 A KR1019970079259 A KR 1019970079259A KR 19970079259 A KR19970079259 A KR 19970079259A KR 100274353 B1 KR100274353 B1 KR 100274353B1
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gas
semiconductor device
capacitor
manufacturing
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KR19990059062A (en
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이태혁
박철환
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: A manufacturing method of capacitor of semiconductor device is provided to reduce leakage current of a dielectric layer, and to increase insulating breakage voltage characteristic by improving the structure of the dielectric layer for the capacitor. CONSTITUTION: A lower electrode(1) is formed on a substrate. The lower electrode(1) is made of a doped polysilicon to reduce resistance. An oxide layer(2A) covers on the lower electrode(1), and a nitride layer(2B) is made on the oxide layer(2A). The oxide layer(2A) is built through a surface oxide step, a vaporizing step, and a rapid tempering step. The nitride layer(2B) is constructed by the vaporizing process, and a plasma treatment or the rapid tempering step. An ON(Oxide/Nitride) structure of dielectric layer(2) is composed of the oxide layer(2A) and the nitride layer(2B). An upper electrode(3) is produced using the doped polysilicon to decrease resistance.

Description

반도체 소자의 캐패시터 제조 방법{Method of manufacturing a capacitor in a semiconductor device}Method of manufacturing a capacitor in a semiconductor device

본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 유효 산화막 두께( effective oxide thickness) 제어가 용이하며, 누설 전류 감소 및 절연 파괴 전압 특성이 향상된 캐패시터용 유전체막을 제조하여 캐패시터에 적용하므로, 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. The method provides a method of manufacturing a dielectric film for a capacitor, which facilitates effective oxide thickness control, reduces leakage current, and improves dielectric breakdown voltage characteristics. The present invention relates to a method for manufacturing a capacitor of a semiconductor device capable of improving.

일반적으로, 반도체 소자의 집적도 증가에 따른 셀의 크기 감소로 캐패시터의 크기 또한 감소하게 되어 충분한 정전용량 확보가 어려워지고 있는 실정이다. 이를 해결하기 위해 통상적으로 사용되는 산화막/질화막/산화막(SiO2/Si3N4/SiOXNy)의 ONO 구조 또는 질화막/산화막(Si3N4/SiO2)의 NO 구조인 캐패시터의 유전체막 대신에 Ta2O5, BST, PZT 등의 고유전율 물질 개발이 진행중이나 소자의 제조 공정에 적용하기에는 미흡한 상태이다. 반도체 소자의 집적도를 증가시키기 위한 또 다른 해결책으로 준안정 폴리실리콘(metastable polysilicon; MPS)을 이용하여 전하저장용 하부 전극의 유효 표면적을 증가시키면서 NO 구조의 유전체막을 적용하는 방법이 있으나, NO 구조의 유전체막 두께를 얇게 할 경우 준안정 폴리실리콘층의 거친 표면 형상에 의한 국부적 전계(local field)로 인해 NO 구조의 유전체막의 누설 전류가 증가하고, 절연 파괴 전압이 낮아져 소자의 수명이 짧아지는 문제점이 있다.In general, as the size of the cell decreases due to the increase in the degree of integration of semiconductor devices, the size of the capacitor also decreases, making it difficult to secure sufficient capacitance. In order to solve this problem, a dielectric of a capacitor which is an ONO structure of an oxide film / nitride film / oxide film (SiO 2 / Si 3 N 4 / SiO X N y ) or a NO structure of nitride film / oxide film (Si 3 N 4 / SiO 2 ) is used. The development of high dielectric constant materials such as Ta 2 O 5 , BST, and PZT instead of the film is in progress, but it is insufficient to be applied to the manufacturing process of the device. Another solution to increase the density of semiconductor devices is to use a metastable polysilicon (MPS) to increase the effective surface area of the lower electrode for charge storage while applying a dielectric film of NO structure. When the thickness of the dielectric film is reduced, the local field due to the rough surface shape of the metastable polysilicon layer increases the leakage current of the dielectric film of the NO structure, and the dielectric breakdown voltage is lowered, thereby shortening the lifetime of the device. have.

또한, 반도체 소자의 집적도 증가에 따른 충분한 정전용량을 확보하기 위한 방법으로 유전체막의 두께를 낮추는 방법이 있는데, 유효 산화막 두께를 약 48Å 정도로 낮출 경우, ONO 구조로는 유전체막의 두께를 낮추는데 한계가 있어 NO 구조를 사용하고 있다. NO 구조는 실제적으로 하부 전극 표면에 자연 산화막(native oxide film)이 약 5Å 정도 존재하여 ONO 구조로 볼 수 있지만 자연 산화막의 두께가 매우 얇고 균일하지 못해 홀 전류(hole current)의 장벽(barrier)으로서의 역할은 수행하지 못하고 있기 때문에 통상적으로 NO 구조라 칭하고 있다. NO 구조의 유전체막은, 도 2에 도시된 바와 같이, 상부 전극에 포지티브 바이어스(positive bias)가 인가된 경우 상부 전극 쪽의 산화막(SiOXNy)이 홀 전류의 장벽 역할을 하여 상부 전극에서 산화막(SiOXNy)으로 진행하는 홀 전류를 막아 누설 전류를 낮춘다. 또한, NO 구조의 유전체막은, 도 3에 도시된 바와 같이, 상부 전극에 네가티브 바이어스(negative bias)가 인가된 경우 하부 전극에서 자연 산화막과 질화막(Si3N4)을 흘러온 홀 전류를 산화막(SiOXNy)이 막아 누설 전류를 낮추게 된다. 그러나, 유효 산화막 두께가 40Å 정도로 더욱 얇아지면 질화막(Si3N4)의 산화 저항성이 급격히 떨어져 질화막(Si3N4)상에 산화막(SiOXNy)을 형성할 때 질화막(Si3N4)이 산화되거나 심하게는 전하저장전극까지 산화되어 캐패시터 불량의 원인이 될 뿐만 아니라, 산화막(SiOXNy)을 치밀하면서 두껍게 형성할 수 없어 터널링 전류가 증가하여 누설 전류 또한 급격히 증가하고 절연 파괴 전압 역시 급격하게 감소되어 소자의 수율을 치명적으로 낮추고, 초고집적화된 차세대 반도체 소자 개발의 걸림돌이 되고 있다.In addition, there is a method of reducing the thickness of the dielectric film as a method for securing sufficient capacitance as the integration degree of the semiconductor device increases. When the effective oxide film thickness is reduced to about 48 kW, the ONO structure has a limitation in reducing the thickness of the dielectric film. I am using a structure. The NO structure can be seen as an ONO structure with a native oxide film on the surface of the lower electrode, which is about 5Å, but the thickness of the natural oxide film is very thin and uneven, which is a barrier to hole current. It is usually called NO structure because it does not play a role. As shown in FIG. 2, when the positive bias is applied to the upper electrode, an oxide film (SiO X N y ) on the upper electrode side acts as a barrier for the hole current, and as shown in FIG. The leakage current is lowered by preventing the hole current going to (SiO X N y ). In addition, as shown in FIG. 3, when the negative electrode is applied to the upper electrode, the dielectric film of the NO structure is configured to convert the hole current flowing through the natural oxide film and the nitride film Si 3 N 4 from the lower electrode into the oxide film (SiO). X N y ) prevents leakage current. However, the effective oxide thickness is more thinner about 40Å nitride oxidation resistance (Si 3 N 4) drops significantly nitride film (Si 3 N 4) oxide film on the nitride film to form a (SiO X N y) (Si 3 N 4) This oxide or severely oxidizes to the charge storage electrode, causing not only the capacitor defect, but also the oxide film (SiO X N y ) cannot be formed thick and dense, so the tunneling current increases and the leakage current rapidly increases and the dielectric breakdown voltage also increases. It has been rapidly reduced to reduce the yield of devices critically, and becomes an obstacle to the development of ultra-high density next generation semiconductor devices.

따라서, 본 발명은 반도체 소자의 캐패시터용 유전체막의 구조를 개선함에 의해 유전체막의 유효 산화막 두께 제어를 용이하게 하면서 유전체막의 누설 전류 감소 및 절연 파괴 전압 특성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조 방법을 제공함에 그 목적이 있다.Accordingly, the present invention provides a method of manufacturing a capacitor of a semiconductor device which can improve the effective oxide film thickness control of the dielectric film by improving the structure of the capacitor dielectric film of the semiconductor device and improve the leakage current and dielectric breakdown voltage characteristics of the dielectric film. Has its purpose.

이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판 상에 하부 전극을 형성하는 단계; 상기 하부 전극 상에 산화막과 질화막이 순차적으로 적층된 ON 구조의 유전체막을 형성하는 단계; 및 상기 유전체막 상에 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: forming a lower electrode on a substrate on which various elements for forming a semiconductor device are formed; Forming a dielectric film having an ON structure in which an oxide film and a nitride film are sequentially stacked on the lower electrode; And forming an upper electrode on the dielectric film.

도 1은 본 발명의 일 실시 예에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 단면도.1 is a cross-sectional view for describing a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

도 2는 종래 질화막/산화막(NO) 구조의 유전체막을 갖는 캐패시터에 포지티브 바이어스가 인가된 경우의 에너지 밴드 다이어그램.FIG. 2 is an energy band diagram when a positive bias is applied to a capacitor having a dielectric film of a conventional nitride / oxide film (NO) structure. FIG.

도 3은 종래 질화막/산화막(NO) 구조의 유전체막을 갖는 캐패시터에 네가티브 바이어스가 인가된 경우의 에너지 밴드 다이어그램.3 is an energy band diagram when a negative bias is applied to a capacitor having a dielectric film having a conventional nitride / oxide film (NO) structure.

도 4는 본 발명의 산화막/질화막(ON) 구조의 유전체막을 갖는 캐패시터에 포지티브 바이어스가 인가된 경우의 에너지 밴드 다이어그램.Fig. 4 is an energy band diagram when a positive bias is applied to a capacitor having a dielectric film of an oxide / nitride film (ON) structure of the present invention.

도 5는 본 발명의 산화막/질화막(ON) 구조의 유전체막을 갖는 캐패시터에 네가티브 바이어스가 인가된 경우의 에너지 밴드 다이어그램.5 is an energy band diagram when a negative bias is applied to a capacitor having a dielectric film of an oxide / nitride film (ON) structure of the present invention.

〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1: 하부 전극 2A: 산화막1: lower electrode 2A: oxide film

2B: 질화막 2: 유전체막2B: nitride film 2: dielectric film

3: 상부 전극3: upper electrode

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 일 실시 예에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for describing a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present disclosure.

먼저, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판 상에 하부 전극(1)을 형성한다. 하부 전극(1)은 저항을 낮추기 위해 도프트 폴리실리콘(doped polysilicon)으로 형성된다. 이후, 하부 전극(1)상에 10 내지 30Å의 두께로 산화막(2A)을 형성하고, 산화막(2A)상에 15 내지 45Å의 두께로 질화막(2B)을 형성하며, 이로 인하여 산화막(2A)과 질화막(2B)으로 된 ON 구조의 유전체막(2)이 형성된다. 다음으로, 유전체막(2)상에 상부 전극(3)이 형성된다. 상부 전극(3)은 저항을 낮추기 위해 도프트 폴리실리콘으로 형성되며, 질화막(2A) 형성 후에 시간 지연 없이 형성한다.First, the lower electrode 1 is formed on a substrate having a structure in which various elements for forming a semiconductor element are formed. The lower electrode 1 is formed of doped polysilicon to lower the resistance. Subsequently, an oxide film 2A is formed on the lower electrode 1 with a thickness of 10 to 30 GPa, and a nitride film 2B is formed on the oxide film 2A to a thickness of 15 to 45 GPa, whereby the oxide film 2A is formed. The dielectric film 2 having the ON structure made of the nitride film 2B is formed. Next, the upper electrode 3 is formed on the dielectric film 2. The upper electrode 3 is formed of doped polysilicon to lower the resistance, and is formed without time delay after the nitride film 2A is formed.

여기에서, 유전체막(2) 중의 산화막(2A)은 하부 전극(1)을 산화시켜 SiO2막 또는 SiOXNy막으로 형성되거나, 저압 또는 플라즈마 증가 화학적 기상 증착(LPCVD 또는 PECVD)법으로 SiO2막 또는 SiOXNy막을 증착 하여 형성되거나, 하부 전극(1)을 급속 열 공정으로 처리하여 SiO2막 또는SiOXNy막으로 형성된다.Here, the oxide film 2A in the dielectric film 2 is formed as an SiO 2 film or SiO X N y film by oxidizing the lower electrode 1, or SiO by low pressure or plasma enhanced chemical vapor deposition (LPCVD or PECVD) method. It is formed by depositing 2 films or SiO x N y films or by forming the SiO 2 film or SiO x N y films by treating the lower electrode 1 by a rapid thermal process.

산화막(2A) 형성을 위한 표면 산화 공정은 O2, NO, N2O 및 H2O 가스중 적어도 어느 하나를 사용하여 600 내지 900℃의 온도와 상압 또는 0.1 내지 1Torr의 저압에서 실시된다. 상압 조건일 경우 O2, NO, N2O 및 H2O 가스를 Ar 및 N2등의 불활성 가스로 희석하여 표면 산화 공정을 실시한다.The surface oxidation process for forming the oxide film 2A is performed at a temperature of 600 to 900 ° C. and an atmospheric pressure or a low pressure of 0.1 to 1 Torr using at least one of O 2 , NO, N 2 O, and H 2 O gases. Under normal pressure conditions, O 2 , NO, N 2 O and H 2 O gases are diluted with an inert gas such as Ar and N 2 to perform a surface oxidation process.

산화막(2A) 형성을 위한 증착 공정은 실리콘 소오스 가스, 산화 소오스 가스 및 질화 소오스 가스를 사용하여 400 내지 900℃의 온도와 0.1 내지 10Torr의 압력에서 실시된다. 실리콘 소오스 가스로는 SiH4, SiH2Cl2, Si2H6가스를 사용하고, 산화 소오스 가스로는 O2, NO, N2O 가스를 사용하며, 질화 소오스 가스로는 NO, N2O, N2가스를 사용한다.The deposition process for forming the oxide film 2A is performed at a temperature of 400 to 900 ° C. and a pressure of 0.1 to 10 Torr using a silicon source gas, an oxide source gas, and a nitride source gas. Silicon-source gas, SiH 4, SiH 2 Cl 2, Si 2 H 6 Use gas and source gas, and use of O 2, NO, N 2 O gas oxidation, nitridation source gas, NO, N 2 O, N 2 Use gas.

산화막(2A) 형성을 위한 급속 열 공정은 O2, NO 및 N2O 가스중 적어도 어느 하나를 사용하여 600 내지 1000℃의 온도와 상압 또는 0.1 내지 1Torr의 저압에서 10 내지 60초 동안 실시된다. 이때 승온 속도는 30 내지 100℃/초로 한다. 상압 조건일 경우 O2, NO 및 N2O 가스를 Ar 및 N2등의 불활성 가스로 희석하여 급속 열처리 공정을 실시한다.The rapid thermal process for forming the oxide film 2A is performed for 10 to 60 seconds at a temperature of 600 to 1000 ° C. and an atmospheric pressure or a low pressure of 0.1 to 1 Torr using at least one of O 2 , NO and N 2 O gases. At this time, the temperature increase rate is 30 to 100 ° C / sec. Under normal pressure conditions, O 2 , NO, and N 2 O gases are diluted with an inert gas such as Ar and N 2 to perform a rapid heat treatment process.

질화막(2B) 형성을 위한 증착 공정은 실리콘 소오스 가스 및 질화 소오스 가스를 사용하여 550 내지 750℃의 온도와 0.1 내지 1Torr의 압력에서 저압 화학적 기상 증착법으로 실시되거나, 350 내지 650℃의 온도와 0.1 내지 10Torr의 압력에서 플라즈마 증가 화학 기상 증착법으로 실시된다. 실리콘 소오스 가스로는 SiH4, SiH2Cl2, Si2H6가스를 사용하고, 질화 소오스 가스로는 NH4, NO, N2O, N2가스를 사용한다.The deposition process for forming the nitride film 2B is performed by low pressure chemical vapor deposition at a temperature of 550 to 750 ° C and a pressure of 0.1 to 1 Torr using a silicon source gas and a nitride source gas, or a temperature of 350 to 650 ° C and 0.1 to It is carried out by plasma enhanced chemical vapor deposition at a pressure of 10 Torr. SiH 4 , SiH 2 Cl 2 , and Si 2 H 6 gases are used as the silicon source gas, and NH 4 , NO, N 2 O, and N 2 gases are used as the nitride source gas.

상기의 공정으로 질화막(2B)을 형성한 후에 질화막(2B)의 표면을 치밀화하기 위해 NO, N2O 및 N2가스중 적어도 어느 하나를 사용하여 플라즈마 후처리하거나, Ar 및 N2등의 불활성 가스를 사용하여 급속 열 공정 후처리를 할 수 있다.After the formation of the nitride film 2B by the above process, in order to densify the surface of the nitride film 2B, plasma post-treatment is performed using at least one of NO, N 2 O and N 2 gases, or inert such as Ar and N 2 . The gas can be used for rapid thermal process post-treatment.

상술한 바와 같이, 본 발명은 산화막(SiO2또는 SiOXNy)을 먼저 형성한 후에 질화막(Si3N4)을 형성하므로, 질화막(Si3N4)이 산화되는 문제가 해결되어 홀 전류의 장벽인 산화막(SiO2또는 SiOXNy)층의 두께 증가 및 치밀화를 실현할 수 있고, 질화막(Si3N4)의 두께를 감소시킬 수 있어, 유효 산화막 두께의 감소, 누설 전류의 감소, 절연 파괴 전압의 증가, TDDB 특성 향상 등을 얻을 수 있다. 따라서, 신뢰성 있는 캐패시터를 형성할 수 있어 소자의 전기적 특성, 수명 및 수율 등을 개선할 수 있고, Ta2O5, BST, PZT 등의 고유전율 물질 개발 필요 없이 유효 산화막 두께를 40Å 이하로 낮출 수 있어 차세대 반도체 소자의 개발을 실현할 수 있고, 경제적인 측면에서도 유리하다.As described above, since the present invention forms an oxide film (SiO 2 or SiO X N y ) first and then forms a nitride film (Si 3 N 4 ), the problem of oxidizing the nitride film (Si 3 N 4 ) is solved and the hall current Increasing and densifying the thickness of the oxide film (SiO 2 or SiO X N y ) layer, which is a barrier, can reduce the thickness of the nitride film (Si 3 N 4 ), thereby reducing the effective oxide film thickness, reducing the leakage current, Increasing the dielectric breakdown voltage and improving the TDDB characteristics can be obtained. Therefore, it is possible to form a reliable capacitor to improve the electrical characteristics, lifetime and yield of the device, and to reduce the effective oxide film thickness to 40 kΩ or less without the need to develop high dielectric constant materials such as Ta 2 O 5 , BST, PZT Therefore, it is possible to realize the development of the next-generation semiconductor device, which is advantageous in terms of economy.

Claims (15)

반도체 소자를 형성하기 위한 여러 요소가 형성된 기판 상에 하부 전극을 형성하는 단계;Forming a lower electrode on a substrate on which various elements for forming a semiconductor device are formed; 상기 하부 전극 상에 산화막과 질화막이 순차적으로 적층된 ON 구조의 유전체막을 형성하는 단계; 및Forming a dielectric film having an ON structure in which an oxide film and a nitride film are sequentially stacked on the lower electrode; And 상기 유전체막 상에 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.And forming an upper electrode on the dielectric film. 제 1 항에 있어서,The method of claim 1, 상기 하부 전극 및 상기 상부 전극은 도프트 폴리실리콘으로 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The lower electrode and the upper electrode is a capacitor manufacturing method of the semiconductor device, characterized in that formed of doped polysilicon. 제 1 항에 있어서,The method of claim 1, 상기 산화막은 표면 산화 공정, 증착 공정 및 급속 열공정 중 어느 하나를 적용하여 10 내지 30Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The oxide film is a capacitor manufacturing method of a semiconductor device, characterized in that formed by a thickness of 10 to 30Å by applying any one of a surface oxidation process, a deposition process and a rapid thermal process. 제 3 항에 있어서,The method of claim 3, wherein 상기 표면 산화 공정은 O2, NO, N2O 및 H2O 가스 중 적어도 어느 하나를 사용하여 600 내지 900℃의 온도와 0.1 내지 1Torr의 저압에서 실시하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The surface oxidation process is carried out at a temperature of 600 to 900 ℃ and a low pressure of 0.1 to 1 Torr using at least one of O 2 , NO, N 2 O and H 2 O gas method of manufacturing a capacitor of a semiconductor device. . 제 3 항에 있어서,The method of claim 3, wherein 상기 표면 산화 공정은 O2, NO, N2O 및 H2O 가스 중 적어도 어느 하나와 불활성 가스를 사용하여 600 내지 900℃의 온도와 상압으로 실시하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The surface oxidation process is a capacitor manufacturing method of a semiconductor device, characterized in that carried out at at least one of O 2 , NO, N 2 O and H 2 O gas and an inert gas at a temperature of 600 to 900 ℃. 제 3 항에 있어서,The method of claim 3, wherein 상기 증착 공정은 실리콘 소오스 가스, 산화 소오스 가스 및 질화 소오스 가스를 사용하여 400 내지 900℃의 온도와 0.1 내지 10Torr의 압력에서 저압 화학적 기상 증착법 및 플라즈마 증가 화학적 기상 증착법 중 어느 하나의 방법으로 실시하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The deposition process may be performed using any one of low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition at a temperature of 400 to 900 ° C. and a pressure of 0.1 to 10 Torr using a silicon source gas, an oxide source gas, and a nitride source gas. A method for manufacturing a capacitor of a semiconductor device. 제 6 항에 있어서,The method of claim 6, 상기 실리콘 소오스 가스로는 SiH4, SiH2Cl2, Si2H6가스를 사용하고, 상기 산화 소오스 가스로는 O2, NO, N2O 가스를 사용하며, 상기 질화 소오스 가스로는 NO, N2O, N2가스를 사용하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The silicon source gas is SiH 4, SiH 2 Cl 2, Si 2 H 6 Use gas and the oxidation source gas, and using O 2, NO, N 2 O gas, the nitriding source gas, NO, N 2 O And N 2 gas. 제 3 항에 있어서,The method of claim 3, wherein 상기 급속 열처리 공정은 O2, NO 및 N2O 가스 중 적어도 어느 하나를 사용하여 600 내지 1000℃의 온도와 0.1 내지 1Torr의 저압에서 10 내지 60초 동안 실시하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The rapid heat treatment process using the at least one of O 2 , NO and N 2 O gas capacitor manufacturing of the semiconductor device, characterized in that performed for 10 to 60 seconds at a temperature of 600 to 1000 ℃ and low pressure of 0.1 to 1 Torr Way. 제 3 항에 있어서,The method of claim 3, wherein 상기 급속 열처리 공정은 O2, NO 및 N2O 가스중 적어도 어느 하나와 불활성 가스를 사용하여 600 내지 1000℃의 온도와 상압에서 10 내지 60초 동안 실시하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The rapid heat treatment process is a capacitor manufacturing method of a semiconductor device, characterized in that for at least one of O 2 , NO and N 2 O gas and an inert gas for 10 to 60 seconds at a temperature of 600 to 1000 ℃ and atmospheric pressure. . 제 8 항 또는 제 9 항에 있어서,The method according to claim 8 or 9, 상기 급속 열처리 공정은 30 내지 100℃/초의 승온 속도 조건으로 실시하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The rapid heat treatment process is a capacitor manufacturing method of a semiconductor device, characterized in that carried out under conditions of temperature increase rate of 30 to 100 ℃ / sec. 제 1 항에 있어서,The method of claim 1, 상기 질화막은 실리콘 소오스 가스 및 질화 소오스 가스를 사용하여 550 내지 750℃의 온도와 0.1 내지 1Torr의 압력에서 저압 화학적 기상 증착법으로 실시하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The nitride film is a method of manufacturing a capacitor of a semiconductor device, characterized in that the silicon source gas and the nitride source gas using a low pressure chemical vapor deposition method at a temperature of 550 to 750 ℃ and a pressure of 0.1 to 1 Torr. 제 1 항에 있어서,The method of claim 1, 상기 질화막은 실리콘 소오스 가스 및 질화 소오스 가스를 사용하여 350 내지 650℃의 온도와 0.1 내지 10Torr의 압력에서 플라즈마 증가 화학 기상 증착법으로 실시하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The nitride film is a method of manufacturing a capacitor of a semiconductor device, characterized in that the silicon source gas and the nitride source gas using a plasma enhanced chemical vapor deposition method at a temperature of 350 to 650 ℃ and a pressure of 0.1 to 10 Torr. 제 11 항 또는 제 12 항에 있어서,The method according to claim 11 or 12, 상기 실리콘 소오스 가스로는 SiH4, SiH2Cl2, Si2H6가스를 사용하고, 상기 질화 소오스 가스로는 NH4, NO, N2O, N2가스를 사용하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.SiH 4 , SiH 2 Cl 2 , Si 2 H 6 gas are used as the silicon source gas, and NH 4 , NO, N 2 O, and N 2 gas are used as the nitride source gas. Manufacturing method. 제 1 항에 있어서,The method of claim 1, 상기 질화막을 형성한 후에 상기 질화막의 표면을 치밀화하기 위해 NO, N2O 및 N2가스중 적어도 어느 하나를 사용하여 플라즈마 후처리하는 것을 포함하는 반도체 소자의 캐패시터 제조 방법.And plasma post-treatment using at least one of NO, N 2 O, and N 2 gases to densify the surface of the nitride film after forming the nitride film. 제 1 항에 있어서,The method of claim 1, 상기 질화막을 형성한 후에 상기 질화막의 표면을 치밀화하기 위해 불활성 가스를 사용하여 급속 열 공정 후처리하는 것을 포함하는 반도체 소자의 캐패시터 제조 방법.And a rapid thermal process post-treatment using an inert gas to densify the surface of the nitride film after forming the nitride film.
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