KR100273271B1 - Fabricating method of silicide - Google Patents
Fabricating method of silicide Download PDFInfo
- Publication number
- KR100273271B1 KR100273271B1 KR1019980001138A KR19980001138A KR100273271B1 KR 100273271 B1 KR100273271 B1 KR 100273271B1 KR 1019980001138 A KR1019980001138 A KR 1019980001138A KR 19980001138 A KR19980001138 A KR 19980001138A KR 100273271 B1 KR100273271 B1 KR 100273271B1
- Authority
- KR
- South Korea
- Prior art keywords
- silicide
- layer
- metal layer
- heat treatment
- semiconductor substrate
- Prior art date
Links
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 52
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 23
- -1 nitrogen ions Chemical class 0.000 claims abstract description 23
- 238000010438 heat treatment Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 239000002245 particle Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000002513 implantation Methods 0.000 abstract description 2
- 235000012054 meals Nutrition 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 229910008479 TiSi2 Inorganic materials 0.000 description 4
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910018999 CoSi2 Inorganic materials 0.000 description 2
- 238000005054 agglomeration Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
Description
본 발명은 실리사이드 제조방법에 관한 것으로, 특히 후속 고온 열처리에서 열적 안정성을 갖는 실리사이드를 원하는 두께로 제조하기에 적당하도록 한 실리사이드 제조방법에 관한 것이다.The present invention relates to a method for preparing silicides, and more particularly to a method for preparing silicides which is suitable for producing silicides having thermal stability in a subsequent high temperature heat treatment to a desired thickness.
반도체소자의 디자인 룰(design rule)이 엄격해지고, 감소하면서 접합의 면저항 및 금속과 반도체의 접촉저항에 따른 기생저항이 소자의 안정적인 동작에 큰 영향을 미치고 있다. 이러한 기생저항을 감소시키기 위한 기술로 살리사이드(self-aligned silicide) 공정에 대한 연구가 활발히 진행되어 왔다. 살리사이드 공정이란 실리콘과 금속의 반응성과 산화막과 금속의 비반응성을 이용한 자기정렬방식을 통해 실리사이드를 제조하는 공정법을 지칭하며, 내열성의 금속 실리사이드중에서 Ti 및 Co-실리사이드는 비저항이 낮고, 열적 안정성이 다른 실리사이드에 비해 뛰어나므로, 살리사이드공정에 가장 널리 이용되고 있다. 이와같은 종래 실리사이드 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.As the design rules of semiconductor devices become stricter and decreasing, parasitic resistances due to the sheet resistance of the junction and the contact resistance of the metal and the semiconductor have a great influence on the stable operation of the device. As a technique for reducing such parasitic resistance, research on a salicide (self-aligned silicide) process has been actively conducted. The salicide process refers to a process for preparing silicide through a self-aligning method using silicon and metal reactivity and oxide film and metal non-reactivity.Ti and Co-silicide has low specific resistance and thermal stability among heat resistant metal silicides. Since it is superior to other silicides, it is most widely used in the salicide process. This conventional silicide manufacturing method will be described in detail below with reference to the accompanying drawings.
도1a 내지 도1d는 종래의 실리사이드 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 반도체기판(1)의 상부에 폴리실리콘으로 이루어진 게이트(2)를 형성하고, 그 게이트(2)의 측면에 측벽(3)을 형성하여 엘디디구조(lightly doped drain:LDD)의 저농도 및 고농도 소스/드레인영역(4)을 형성하는 단계(도1a)와; 그 반도체기판(1)의 상부 전면에 금속층(5)을 증착하는 단계(도1b)와; 그 금속층(5)이 증착된 반도체기판(1)을 1차 열처리하여 게이트(2) 및 고농도 소스/드레인영역(4)의 상부에 실리사이드층(6)을 형성하는 단계(도1c)와; 습식식각방법을 통해 잔여 금속층(5)을 제거한 후, 2차 열처리를 수행하는 단계(도1d)로 이루어진다. 이하, 상기한 바와같은 일반적인 실리사이드 제조방법을 좀더 상세히 설명한다.1A to 1D are cross-sectional views showing a conventional silicide manufacturing method. As shown therein, a gate 2 made of polysilicon is formed on an upper portion of a semiconductor substrate 1, and a side surface of the gate 2 is formed. Forming sidewalls 3 to form low and high concentration source / drain regions 4 of lightly doped drain (LDD) (FIG. 1A); Depositing a metal layer 5 on the entire upper surface of the semiconductor substrate 1 (Fig. 1B); First heat treating the semiconductor substrate 1 on which the metal layer 5 is deposited to form a silicide layer 6 on the gate 2 and the high concentration source / drain region 4 (FIG. 1C); After the residual metal layer 5 is removed through a wet etching method, a second heat treatment is performed (FIG. 1D). Hereinafter, a general silicide manufacturing method as described above will be described in more detail.
먼저, 도1a에 도시한 바와같이 반도체기판(1)의 상부에 폴리실리콘으로 이루어진 게이트(2)를 형성하고, 그 게이트(2)의 측면에 측벽(3)을 형성하여 엘디디구조의 저농도 및 고농도 소스/드레인영역(4)을 형성한다. 이때, 엘디디구조를 형성하는 공정은 게이트(2)가 형성된 반도체기판(1)에 저농도의 불순물이온을 주입한 후, 그 게이트(2)의 측면에 측벽(3)을 형성하고, 그 측벽(3)이 형성된 반도체기판(1)에 고농도의 불순물이온을 주입하여 저농도 및 고농도 소스/드레인영역을 형성하는 공정으로, 열전자효과를 감소시켜 반도체소자의 신뢰성을 향상시키기 위해 통상적으로 행해지고 있다.First, as shown in FIG. 1A, a gate 2 made of polysilicon is formed on the semiconductor substrate 1, and sidewalls 3 are formed on the side surface of the gate 2 so as to provide a low concentration of the LED structure. High concentration source / drain regions 4 are formed. At this time, in the process of forming the LED structure, a low concentration of impurity ions are injected into the semiconductor substrate 1 on which the gate 2 is formed, and then a sidewall 3 is formed on the side surface of the gate 2, and the sidewall ( A process of forming a low concentration and a high concentration source / drain region by injecting a high concentration of impurity ions into the semiconductor substrate 1 on which 3) is formed is conventionally performed to reduce the thermoelectronic effect and improve the reliability of the semiconductor device.
그리고, 도1b에 도시한 바와같이 반도체기판(1)의 상부 전면에 금속층(5)을 증착한다. 이때, 금속층(5)으로는 다른 금속에 비해 열처리 후 상대적으로 저항이 낮은 Co,Ti 등을 증착한다.Then, as shown in FIG. 1B, the metal layer 5 is deposited on the entire upper surface of the semiconductor substrate 1. In this case, as the metal layer 5, Co, Ti, etc. having a relatively low resistance after heat treatment are deposited as compared to other metals.
그리고, 도1c에 도시한 바와같이 금속층(5)이 증착된 반도체기판(1)을 1차 열처리하여 게이트(2) 및 고농도 소스/드레인영역(4)의 상부에 실리사이드층(6)을 형성한다. 이때, 1차 열처리는 금속층(5)이 Ti인 경우는 600℃∼750℃, 금속층(5)이 Co인 경우는 450℃∼550℃로 수행한다.As shown in FIG. 1C, the semiconductor substrate 1 on which the metal layer 5 is deposited is first heat treated to form a silicide layer 6 on the gate 2 and the high concentration source / drain region 4. . At this time, the primary heat treatment is performed at 600 ° C to 750 ° C when the metal layer 5 is Ti, and at 450 ° C to 550 ° C when the metal layer 5 is Co.
그리고, 도1d에 도시한 바와같이 습식식각방법을 통해 잔여 금속층(5)을 제거한 후, 2차 열처리를 수행한다. 이때, 2차 열처리는 형성된 실리사이드층(6)이 C49 TiSi2인 경우는 800℃∼900℃로 열처리하여 저항이 낮은 물질인 C54 TiSi2로 상변이 시키며, CoSi인 경우는 600℃∼750℃로 열처리하여 저항이 낮은 물질인 CoSi2로 상변이 시킨다.Then, as shown in FIG. 1D, the residual metal layer 5 is removed through a wet etching method, and then secondary heat treatment is performed. In this case, the secondary heat treatment is a heat treatment at 800 ℃ to 900 ℃ when the silicide layer 6 is formed of C49 TiSi2 phase change to C54 TiSi2, a material of low resistance, in the case of CoSi heat treatment at 600 ℃ to 750 ℃ Phase shift to CoSi2, a low-resistance material.
그러나, 상기한 바와같은 종래의 실리사이드 제조방법은 형성된 실리사이드가 후속공정에서 열에너지를 얻으면 결정경계(grain boundary)가 감소되고, 이에 따라 결정경계의 과잉에너지가 줄어들어 실리사이드 전체의 에너지가 줄어들게 되므로, 후속 열공정에 의해 실리사이드의 덩어리(agglomeration)가 형성되고, 그 덩어리들로 인해 실리사이드의 저항이 급격히 증가되는 문제점이 있었다.However, in the conventional silicide manufacturing method as described above, when the formed silicide obtains thermal energy in a subsequent process, the grain boundary is reduced, and thus the excess energy of the crystal boundary is reduced, thereby reducing the energy of the silicide as a whole. Agglomeration of the silicide is formed by the process, and the agglomeration causes a problem in that the silicide resistance is rapidly increased.
본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 고온에서 열적안정성을 갖으며, 원하는 두께의 실리사이드를 제조할 수 있는 실리사이드 제조방법을 제공하는 데 있다.The present invention was devised to solve the above problems, and an object of the present invention is to provide a silicide manufacturing method which has thermal stability at high temperature and can produce silicide having a desired thickness.
도1은 종래의 실리사이드 제조방법을 보인 수순단면도.Figure 1 is a flow sectional view showing a conventional silicide manufacturing method.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
도3은 도2에 있어서, 실리사이드층의 상세단면도.3 is a detailed cross-sectional view of the silicide layer in FIG.
도4는 본 발명을 적용한 실리사이드층의 열적안정성을 보인 그래프도.Figure 4 is a graph showing the thermal stability of the silicide layer to which the present invention is applied.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:반도체기판 2:게이트1: semiconductor substrate 2: gate
3:측벽 4:소스/드레인영역3: side wall 4: source / drain area
5:금속층 6:실리사이드층5: metal layer 6: silicide layer
상기한 바와같은 본 발명의 목적은 게이트 및 소스/드레인영역이 형성된 반도체기판 상에 질소이온을 소정깊이로 주입하는 공정과; 상기 질소이온이 주입된 반도체기판의 상부전면에 금속층을 증착하고, 1차 열처리를 통해 금속층과 실리콘을 선택적으로 반응시켜 실리사이드층을 형성하는 공정과; 상기 1차 열처리에서 미반응된 금속층을 제거한 다음 2차 열처리를 통해 상기 실리사이드층을 상변이시켜 저항값을 최소화하는 공정을 구비하여 이루어짐으로써 달성되는 것으로, 본 발명에 의한 실리사이드 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.An object of the present invention as described above is a step of implanting nitrogen ions to a predetermined depth on a semiconductor substrate on which gate and source / drain regions are formed; Depositing a metal layer on an upper surface of the semiconductor substrate into which the nitrogen ions are implanted, and selectively reacting the metal layer with silicon through a first heat treatment to form a silicide layer; It is achieved by removing the unreacted metal layer in the first heat treatment and then performing a phase change of the silicide layer through the second heat treatment to minimize the resistance value. When described in detail with reference to as follows.
도2a 내지 도2e는 본 발명의 일 실시예를 보인 수순단면도로서, 이에 도시한 바와같이 반도체기판(1)의 상부에 게이트(2)를 형성하고, 그 게이트(2)의 측면에 측벽(3)을 형성하여 엘디디구조의 저농도 및 고농도 소스/드레인영역(4)을 형성하는 단계(도2a)와; 그 게이트(2) 및 소스/드레인영역(4)에 소정깊이로 질소이온을 주입하는 단계(도2b)와; 질소이온이 주입된 반도체기판(1)의 상부 전면에 금속층(5)을 증착하는 단계(도2c)와; 그 금속층(5)이 증착된 반도체기판(1)을 1차 열처리하여 게이트(2) 및 고농도 소스/드레인영역(4)의 상부에 실리사이드층(6)을 형성하는 단계(도2d)와; 습식식각방법을 통해 잔여 금속층(5)을 제거한 후, 2차 열처리를 수행하는 단계(도2e)로 이루어진다. 이하, 상기한 바와같은 본 발명의 일 실시예를 좀더 상세히 설명한다.2A through 2E are cross-sectional views showing an embodiment of the present invention. As shown therein, a gate 2 is formed on an upper portion of a semiconductor substrate 1, and sidewalls 3 are formed on a side surface of the gate 2. Forming a low density and high concentration source / drain region 4 of the LED structure (FIG. 2A); Injecting nitrogen ions to a predetermined depth into the gate 2 and the source / drain region 4 (FIG. 2B); Depositing a metal layer 5 on the upper front surface of the semiconductor substrate 1 into which nitrogen ions are implanted (FIG. 2C); First heat treating the semiconductor substrate 1 on which the metal layer 5 is deposited to form a silicide layer 6 on the gate 2 and the high concentration source / drain region 4 (FIG. 2D); After the residual metal layer 5 is removed through a wet etching method, a second heat treatment is performed (FIG. 2E). Hereinafter, an embodiment of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와같이 반도체기판(1)의 상부에 게이트(2)를 형성하고, 그 게이트(2)의 측면에 측벽(3)을 형성하여 엘디디구조의 저농도 및 고농도 소스/드레인영역(4)을 형성한다. 이때, 엘디디구조를 형성하는 공정은 종래와 동일하게 수행된다.First, as shown in FIG. 2A, the gate 2 is formed on the upper surface of the semiconductor substrate 1, and the sidewalls 3 are formed on the side surface of the gate 2 to form a low concentration and a high concentration source / drain of the LED structure. The region 4 is formed. At this time, the process of forming the LED structure is performed as in the prior art.
그리고, 도2b에 도시한 바와같이 게이트(2) 및 소스/드레인영역(4)에 소정깊이로 질소이온을 주입한다. 이때, 질소이온은 30keV∼100keV의 에너지로 1015∼1016개/㎠를 주입한다.As shown in FIG. 2B, nitrogen ions are implanted into the gate 2 and the source / drain region 4 at a predetermined depth. At this time, the nitrogen ions are injected 1015-1016 pieces / cm 2 with energy of 30keV ~ 100keV.
그리고, 도2c에 도시한 바와같이 질소이온이 주입된 반도체기판(1)의 상부 전면에 금속층(5)을 증착한다. 이때, 금속층(5)은 Ti 또는 Co를 증착한다.As shown in FIG. 2C, the metal layer 5 is deposited on the entire upper surface of the semiconductor substrate 1 into which nitrogen ions are implanted. At this time, the metal layer 5 deposits Ti or Co.
그리고, 도2d에 도시한 바와같이 금속층(5)이 증착된 반도체기판(1)을 1차 열처리하여 게이트(2) 및 고농도 소스/드레인영역(4)의 상부에 실리사이드층(6)을 형성한다. 이때, 1차 열처리의 온도조건은 종래와 동일하며, 게이트(2) 및 고농도 소스/드레인영역(4)에 주입된 질소이온은 금속층(5)이 Ti일 경우는 Ti와 반응하여 도3에 도시한 바와같이 TiN이 실리사이드층(6)의 결정경계에 주로 분포함으로써, 후속 열공정에 의해 실리사이드의 덩어리가 형성되는 것을 방지하며, 금속층(5)이 Co일 경우는 CoN은 존재하지 않지만, 질소이온이 CoSi2의 결정경계에 주로 분포하여 상기와 동일하게 실리사이드의 덩어리가 형성되는 것을 방지한다. 한편, 질소이온이 금속과 반응함으로써, 실리사이드층(6)의 형성을 억제하여 질소이온의 주입깊이에 따라 실리사이드층(6)의 두께를 조절할 수 있다.As shown in FIG. 2D, the semiconductor substrate 1 on which the metal layer 5 is deposited is first heat-treated to form the silicide layer 6 on the gate 2 and the high concentration source / drain region 4. . At this time, the temperature condition of the first heat treatment is the same as in the prior art, nitrogen ions implanted in the gate 2 and the high concentration source / drain region 4 reacts with Ti when the metal layer 5 is Ti, as shown in FIG. As described above, TiN is mainly distributed in the crystal boundary of the silicide layer 6, thereby preventing formation of silicides by subsequent thermal processes, and when the metal layer 5 is Co, CoN does not exist but nitrogen ions. It is mainly distributed in the crystal boundary of CoSi2 to prevent the formation of silicide agglomerates in the same manner as above. On the other hand, by the reaction of the nitrogen ions with the metal, the formation of the silicide layer 6 can be suppressed and the thickness of the silicide layer 6 can be adjusted according to the depth of implantation of the nitrogen ions.
그리고, 도2e에 도시한 바와같이 습식식각방법을 통해 잔여 금속층(5)을 제거한 후, 2차 열처리를 수행한다. 이때, 2차 열처리도 종래와 동일한 온도조건으로 수행하여 보다 저항이 낮은 물질로 실리사이드층(6)을 상변이 시킨다.As shown in FIG. 2E, after the residual metal layer 5 is removed through a wet etching method, secondary heat treatment is performed. At this time, the secondary heat treatment is also performed under the same temperature conditions as before, so that the silicide layer 6 is phase-transformed with a material having a lower resistance.
한편, 도4는 이와같은 질소이온을 통한 실리사이드층(6)의 열적안정성을 보인 그래프도로서, 1차 열처리를 N2 분위기와 NH3 분위기에서 각각 진행한 TiSi2의 저항변화를 나타내며, NH3 분위기에서 열처리하여 TiSi2에 질소이온의 주입이 많은 것의 열적 특성이 보다 안정되어 있음을 알수 있다.On the other hand, Figure 4 is a graph showing the thermal stability of the silicide layer 6 through such nitrogen ions, showing the change in the resistance of TiSi2 proceeded to the first heat treatment in N2 atmosphere and NH3 atmosphere, respectively, by heat treatment in NH3 atmosphere It can be seen that the thermal properties of many nitrogen ions injected into TiSi2 are more stable.
상기한 바와같은 본 발명에 의한 실리사이드 제조방법은 게이트 및 고농도 소스/드레인영역에 주입된 질소이온이 금속과 반응하여 실리사이드층의 결정경계에 주로 분포하거나, 또는 질소이온 자체가 실리사이드의 결정경계에 주로 분포하여 후속 열공정에 의해 실리사이드의 덩어리가 형성되지 않도록 하여 저항의 증가를 방지함으로써, 실리사이드층의 열적안정성을 도모할 수 있는 효과와; 질소이온이 금속과 반응함으로써, 실리사이드층의 형성을 억제하여 질소이온의 주입깊이에 따라 실리사이드층의 두께를 조절할 수 있는 효과가 있다.In the silicide manufacturing method according to the present invention as described above, the nitrogen ion injected into the gate and the high concentration source / drain region reacts with the metal and is mainly distributed in the crystal boundary of the silicide layer, or the nitrogen ion itself is mainly used in the crystal boundary of the silicide. An effect of achieving thermal stability of the silicide layer by distributing it to prevent formation of agglomerates of silicide by a subsequent thermal process and preventing an increase in resistance; By the reaction of the nitrogen ions with the metal, the formation of the silicide layer is suppressed, and thus the thickness of the silicide layer can be adjusted according to the depth of injection of the nitrogen ions.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980001138A KR100273271B1 (en) | 1998-01-16 | 1998-01-16 | Fabricating method of silicide |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980001138A KR100273271B1 (en) | 1998-01-16 | 1998-01-16 | Fabricating method of silicide |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990065713A KR19990065713A (en) | 1999-08-05 |
| KR100273271B1 true KR100273271B1 (en) | 2001-02-01 |
Family
ID=40749331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980001138A KR100273271B1 (en) | 1998-01-16 | 1998-01-16 | Fabricating method of silicide |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100273271B1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100433054B1 (en) * | 2001-12-22 | 2004-05-27 | 동부전자 주식회사 | Method For Manufacturing Semiconductor Devices |
| KR101004811B1 (en) * | 2003-07-25 | 2011-01-04 | 매그나칩 반도체 유한회사 | Method for manufacturing Transistor |
| US8987102B2 (en) * | 2011-07-27 | 2015-03-24 | Applied Materials, Inc. | Methods of forming a metal silicide region in an integrated circuit |
| EP4199110A4 (en) | 2021-01-14 | 2024-04-10 | Changxin Memory Tech Inc | Manufacturing method for semiconductor structure, and two semiconductor structures |
| CN112864240B (en) * | 2021-01-14 | 2022-05-31 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and two semiconductor structures |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09223677A (en) * | 1996-02-14 | 1997-08-26 | Sony Corp | Manufacturing method of semiconductor device |
-
1998
- 1998-01-16 KR KR1019980001138A patent/KR100273271B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09223677A (en) * | 1996-02-14 | 1997-08-26 | Sony Corp | Manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990065713A (en) | 1999-08-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100218894B1 (en) | Method of manufacturing semiconductor device | |
| KR0135163B1 (en) | Manufacturing method of mos transistor with shallow | |
| US6451693B1 (en) | Double silicide formation in polysicon gate without silicide in source/drain extensions | |
| KR100440840B1 (en) | Method of manufacturing semiconductor device and semiconductor device | |
| US6004871A (en) | Implant enhancement of titanium silicidation | |
| US6630721B1 (en) | Polysilicon sidewall with silicide formation to produce high performance MOSFETS | |
| US6451679B1 (en) | Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology | |
| US6514859B1 (en) | Method of salicide formation with a double gate silicide | |
| US6200840B1 (en) | Method for producing PMOS devices | |
| US6156615A (en) | Method for decreasing the contact resistance of silicide contacts by retrograde implantation of source/drain regions | |
| KR100273271B1 (en) | Fabricating method of silicide | |
| US6150248A (en) | Method for fabricating semiconductor device | |
| US5998286A (en) | Method to grow self-aligned silicon on a poly-gate, source and drain region | |
| US6559018B1 (en) | Silicon implant in a salicided cobalt layer to reduce cobalt-silicon agglomeration | |
| KR20060126972A (en) | Semiconductor device with silicided source/drains | |
| JP3129867B2 (en) | Method for manufacturing semiconductor device | |
| KR100313089B1 (en) | Method for manufacturing semiconductor device | |
| KR100588686B1 (en) | Method for manufacturing a silicide layer of semiconductor device | |
| KR100572209B1 (en) | Method for fabricating silicide layer of semiconductor device | |
| US6777300B2 (en) | Method to improve silicide formation on polysilicon | |
| KR100255008B1 (en) | Manufacture method of semiconductor apparatus | |
| KR100486649B1 (en) | Method for forming salicide of a semiconductor device | |
| JP3639745B2 (en) | Manufacturing method of semiconductor device | |
| KR100491419B1 (en) | Method for manufacturing a semiconductor device | |
| KR100903279B1 (en) | Method for manufacturing a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100825 Year of fee payment: 11 |
|
| LAPS | Lapse due to unpaid annual fee |