KR100272270B1 - Method for forming metal interconnection layer in semiconductor device - Google Patents

Method for forming metal interconnection layer in semiconductor device Download PDF

Info

Publication number
KR100272270B1
KR100272270B1 KR1019970030368A KR19970030368A KR100272270B1 KR 100272270 B1 KR100272270 B1 KR 100272270B1 KR 1019970030368 A KR1019970030368 A KR 1019970030368A KR 19970030368 A KR19970030368 A KR 19970030368A KR 100272270 B1 KR100272270 B1 KR 100272270B1
Authority
KR
South Korea
Prior art keywords
contact hole
mask pattern
layer
ion implantation
forming
Prior art date
Application number
KR1019970030368A
Other languages
Korean (ko)
Other versions
KR19990006146A (en
Inventor
조경수
심규철
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR1019970030368A priority Critical patent/KR100272270B1/en
Publication of KR19990006146A publication Critical patent/KR19990006146A/en
Application granted granted Critical
Publication of KR100272270B1 publication Critical patent/KR100272270B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a metal interconnection of a semiconductor device is provided to improve a burying characteristic and to prevent a surface roughness phenomenon, by implanting impurity ions into a lower interconnection layer inside a contact hole to form a seed layer, and by growing an aluminum metal layer. CONSTITUTION: An interlayer dielectric(3) is formed on a semiconductor substrate(1) having a conductive region. A mask pattern is formed on the interlayer dielectric to expose a predetermined portion. The interlayer dielectric is etched to expose a predetermined portion of the conductive region as the shape of the mask pattern and to form a contact hole. Impurity ions are implanted into the upper portion of the mask pattern and into the exposed conductive region inside the contact hole to form an ion implantation layer. The mask pattern is removed while the ion implantation layer formed on the mask pattern is removed together. A buried metal layer composed of aluminium is formed only inside the contact hole by using the ion implantation layer inside the contact hole as a medium.

Description

반도체 소자의 금속 배선 형성방법Metal wiring formation method of semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 보다 구체적으로는, 상층배선과 하층 배선을 연결하는 콘택 금속막의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a method for forming a contact metal film connecting upper wirings and lower wirings.

반도체 소자가 미세화되고 고집적화됨에 따라, 폴리실리콘의 게이트 전극이나 소오스 및 드레인 확산 영역을 금속 배선과 접촉시켜 주기 위한 콘택홀의 폭이 점점 작아 지고, 또한 확산 영역의 PN 접합의 깊이도 점점 얇아지게 됨으로써, 배선의 접촉저항이 증대되며, 다층의 금속 배선 공정이 요구된다.As semiconductor devices become finer and more highly integrated, the width of the contact hole for contacting the gate electrode or the source and drain diffusion regions of polysilicon with the metal wiring becomes smaller and the depth of the PN junction of the diffusion regions becomes thinner. Contact resistance of the wiring is increased, and a multilayer metal wiring process is required.

여기서, 종래의 상층 배선(접합 영역)과 하층 배선을 연결하기 위한 콘택 방법은, 하층 배선이 형성된 기판상에 절연막을 증착하고, 하층 배선의 소정 부분이 노출되도록 절연막을 식각하여, 콘택홀을 형성한다. 종래의 콘택홀은 현재의 고집적 추세에 부응하여 매우 미세한 사이즈로 형성되어, 콘택홀 내부를 매립하기 위한 매립 금속층이 소정의 방식으로 형성된다. 그후, 이 매립된 금속충과 접촉되도록 상부 배선이 형성된다.Here, in the conventional contact method for connecting the upper layer wiring (junction region) and the lower layer wiring, an insulating film is deposited on the substrate on which the lower layer wiring is formed, and the insulating film is etched so that a predetermined portion of the lower layer wiring is exposed to form a contact hole. do. Conventional contact holes are formed in a very fine size in response to the current high integration trend, so that a buried metal layer for filling the inside of the contact holes is formed in a predetermined manner. Thereafter, the upper wiring is formed to be in contact with the buried metal worm.

이때, 매립 금속층을 형성하는 방법으로는, 매립 특성이 우수한 화학기상 증착 방식의 텅스텐 플러그, 고온 스퍼터링 방식에 의한 알루미늄 증착법 또는 화학 기상 증착 방식에 의한 알루미늄 증착법이 있다.At this time, the method of forming the buried metal layer includes a tungsten plug of a chemical vapor deposition method having excellent buried characteristics, an aluminum deposition method by a high temperature sputtering method or an aluminum deposition method by a chemical vapor deposition method.

그러나, 상술한 매립 금속층 형성방법은 다음과 같은 문제점을 지닌다.However, the above-described buried metal layer forming method has the following problems.

먼저, 텅스텐 플러그 방법은, 매립 특성은 우수한 반면, 텅스텐의 자체 저항이 크므로, 배선 저항이 증가되고, 금속 신뢰성이 저하되는 문제점이 있다.First, the tungsten plug method has a problem in that the buried property is excellent, while the tungsten self resistance is large, so that the wiring resistance is increased and the metal reliability is lowered.

또한, 상기 고온 스퍼터링 방식에 의한 알루미늄 증착법은 전도성은 우수하나, 매립 특성이 좋지않아, 재현성이 저하되는 문제점이 발생된다.In addition, the aluminum deposition method by the high temperature sputtering method is excellent in conductivity, but the buried property is not good, there is a problem that the reproducibility is lowered.

또한, 화학 기상 증착 방식에 의한 알루미늄 증착법은, 증착후 표면이 거칠게 증착되어, 추가적으로 화학적 기계적 연마 공정을 진행하여야 하는 번거러움 또한 상존하였다.In addition, the aluminum vapor deposition method by the chemical vapor deposition method also has a rough surface after the deposition, the cumbersome to further proceed with the chemical mechanical polishing process also existed.

따라서, 본 발명은, 하층 배선 또는 접합 영역과 상층 배선을 연결하는 콘택 금속을 전도 특성 및 매립 특성을 동시에 만족할 수 있도록하여 금속 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device which can improve the metal reliability by making the contact metal connecting the lower wiring or the junction region and the upper wiring at the same time satisfying the conductive and buried characteristics. It is done.

또한, 본 발명의 다른 목적은 추가적인 연마 공정없이 표면이 평탄한 금속 배선 형성방법을 제공하는 것이다.Another object of the present invention is to provide a method for forming metal wiring with a flat surface without an additional polishing process.

제1(a)도 내지 제1(c)도는 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 공정 단면도.1 (a) to 1 (c) are cross-sectional views for explaining a method for forming a metal wiring of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 반도체 기판 2 : 하층 배선1: semiconductor substrate 2: lower layer wiring

3 : 층간 절연막 4 : 콘택용 마스크 패턴3: interlayer insulation film 4: mask pattern for contact

5 : 알루미늄막 100 : 콘택홀5: aluminum film 100: contact hole

200-1,200-2 : 이온 주입층200-1,200-2: ion implantation layer

상기한 본 발명의 목적을 달성하기 위하여, 본 발명은 전도 영역을 구비한 반도체 기판상에 층간 절연막을 형성하는 단계; 상기 층간 절연막 상부에 소정 부분이 노출되도록 마스크 패턴을 형성하는 단계; 상기 마스크 패턴의 형태로 전도 영역의 소정 부분이 노출되도록 층간 절연막을 식각하여, 콘택홀을 형성하는 단계; 상기 마스크 패턴 상부 및 상기 콘택홀내의 노출된 전도영역으로 불순물을 이온주입하여 이온주입층을 형성하는 단계; 상기 마스크 패턴을 제거하여 그의 상부에 형성된 이온주입층도 함께 제거하는 단계; 상기 콘택홀내의 이온주입층을 매개로 상기 콘택홀내에만 알루미늄으로된 매립 금속막을 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성방법을 제공하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate having a conductive region; Forming a mask pattern on the interlayer insulating layer to expose a predetermined portion; Etching the interlayer insulating film to expose a predetermined portion of the conductive region in the form of the mask pattern to form a contact hole; Forming an ion implantation layer by implanting impurities into the exposed conductive region in the upper portion of the mask pattern and the contact hole; Removing the mask pattern to remove the ion implantation layer formed thereon; And forming a buried metal film made of aluminum only in the contact hole through the ion implantation layer in the contact hole.

본 발명에 의하면, 콘택홀 매립 금속층 형성단계 이전에, 콘택홀 저면에 시드층을 형성한 후, 알루미늄 금속막을 매립하므로서, 콘택홀 내의 매립 특성을 향상시키게 되고, 표면 거칠음 현상이 방지된다.According to the present invention, before the contact hole filling metal layer forming step, the seed layer is formed on the bottom of the contact hole and then the aluminum metal film is embedded, thereby improving the embedding characteristics in the contact hole and preventing surface roughness.

아울러, 전도 특성이 우수한 알루미늄 금속막을 매립 금속막으로 이용하여, 금속 배선이 전도 특성이 개선된다.In addition, by using an aluminum metal film having excellent conductivity as a buried metal film, the metal wiring has improved conductivity.

[실시예]EXAMPLE

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도면 제1(a)도 내지 제1(c)도는 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 공정 단면도이다.1 (a) to 1 (c) are sectional views for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

먼저, 제1(a)도에 도시된 바와 같이, 하층 배선(2)을 포함하는 반도체 기판(1) 상부에 층간 절연막(3)이 공지의 증착 방식에 의하여 형성된다. 여기서, 상기 하층 배선은 트랜지스터의 접합 영역이 될 수 있으며, 또는 접합 영역과 연결되는 제1금속 배선이 될 수 있다. 이 층간 절연막(3) 상부에는 콘택용 마스크 패턴(4)이 공지의 포토리소그라피 공정에 의하여 형성된다.First, as shown in FIG. 1 (a), an interlayer insulating film 3 is formed on the semiconductor substrate 1 including the lower wiring 2 by a known deposition method. Here, the lower layer wiring can be a junction region of the transistor or can be a first metal wiring connected to the junction region. A contact mask pattern 4 is formed on the interlayer insulating film 3 by a known photolithography process.

이어, 제1(b)도에 도시된 바와같이, 콘택용 마스크 패턴(4)을 이용하여, 층간 절연막(3)은 하층 배선(2)의 표면이 노출되도록 에칭하여 콘택홀(100)이 형성된다. 이어, 콘택홀(100) 내부 및 마스크 패턴(4) 상부에는 소정의 불순물들이 이온 주입된다. 이때, 불순물들로는 F, P, BF2, As, Ge, Si, Pb, Ar 중 선택되는 하나 또는 두개의 불순물이 이용된다. 상기 불순물을 결과물상에 이온 주입하는 것은, 알루미늄이 용이하게 성장될 수 있도록 시드층(seed layer)을 형성하여 주기 위함이고, 본 발명에서는 예를들어, F 이온을 이온 주입하였다. 여기서, 미설명 부호 200-1, 200-2는 상기 불순물이 이온 주입된 이온주입 층을 나타낸다.Subsequently, as shown in FIG. 1 (b), using the contact mask pattern 4, the interlayer insulating film 3 is etched to expose the surface of the lower layer wiring 2 to form the contact hole 100. do. Subsequently, predetermined impurities are implanted into the contact hole 100 and the mask pattern 4. In this case, one or two impurities selected from F, P, BF 2, As, Ge, Si, Pb, and Ar may be used as impurities. The ion implantation of the impurity onto the resultant is to form a seed layer so that aluminum can be easily grown, and in the present invention, for example, ion implanted with F ions. Here, reference numerals 200-1 and 200-2 denote ion implantation layers in which the impurities are ion implanted.

여기서, 상기와 같이 시드층을 형성하게 되면 다음과 같은 반응에 의하여 알루미늄이 용이하게 성장된다.Here, when the seed layer is formed as described above, aluminum is easily grown by the following reaction.

즉, 알루미늄 소오스로서 예를들어 DMAH(dimethylaluminumhydride : A1H(CH3)2)가 이용되면, 하기의 반응식에 의하여 알루미늄만이 성장되어진다.That is, when, for example, DMAH (dimethylaluminum hydride: A1H (CH 3 ) 2 ) is used as the aluminum source, only aluminum is grown by the following reaction formula.

AlH(CH3)2) +F →1 Al(CH3)2+ HF ↑AlH (CH 3 ) 2 ) + F → 1 Al (CH 3 ) 2 + HF ↑

→ Al + 3H2↑+ 2CF4↑→ Al + 3H 2 ↑ + 2CF 4 ↑

→ Al→ Al

그후, 제1(c)에 도시된 바와 같이, 마스크 패턴(4)은 공지의 제거 방식으로 제거되어 콘택홀(100)내에만 이온주입층(200-1)이 존재하게 된다. 이어서, 콘택홀(100)내의 이온주입층(200-1)을 시드층으로 하여 알루미늄을 성장시키면, 콘택홀(100)내에 알루미늄층(5)이 선택 성장된다. 이때, 알루미늄막은 상기의 반응식에 의하여 성장되며, 약 200 내지 400℃의 온도와, 10-3내지 10 Torr의 압력하에서 형성된다. 여기서, 알루미늄 소오스로는 TIBA(triisobutylaluminum), 또는 DMAH가 이용된다. 이와같이, 콘택홀(100)내의 하부배선층에 시드층을 형성하여, 알루미늄막(5)이 콘택홀(100)내에만 고르게 성장된다. 따라서, 매립 불량으로 인한 금속 신뢰성 저하가 개선된다. 아울러, 콘택홀내의 하부 배선층에 이온주입된 불순물 이온주입층을 시드층으로 하여 알루미늄막이 성장되므로, 성장후 알루미늄막(5) 표면에 댕글링 본드들이 존재하지 않아, 표면 거칠음 현상이 방지된다. 따라서, 추가적인 연마 공정이 배제되고, 알루미늄막의 자체 저항이 매우 낮으므로, 전도 특성이 우수하게 된다.Thereafter, as shown in the first (c), the mask pattern 4 is removed by a known removal method so that the ion implantation layer 200-1 exists only in the contact hole 100. Subsequently, when aluminum is grown using the ion implantation layer 200-1 in the contact hole 100 as a seed layer, the aluminum layer 5 is selectively grown in the contact hole 100. At this time, the aluminum film is grown by the reaction scheme, and is formed at a temperature of about 200 to 400 ° C. and a pressure of 10 −3 to 10 Torr. Here, triisobutylaluminum (TIBA) or DMAH is used as the aluminum source. In this way, the seed layer is formed in the lower wiring layer in the contact hole 100 so that the aluminum film 5 is evenly grown only in the contact hole 100. Therefore, the reduction in metal reliability due to the poor filling is improved. In addition, since the aluminum film is grown using an impurity ion implantation layer ion-implanted into the lower wiring layer in the contact hole as a seed layer, dangling bonds do not exist on the surface of the aluminum film 5 after growth, thereby preventing surface roughness. Therefore, the additional polishing step is excluded, and the self-resistance of the aluminum film is very low, so that the conductive properties are excellent.

그후, 결과물은 약 200 내지 500℃에서 5 내지 10분 동안 금속 특성 향상을 위한 어닐링 공정이 실시될 수 있다.Thereafter, the resultant may be subjected to an annealing process for improving metal properties at about 200 to 500 ° C. for 5 to 10 minutes.

이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 콘택홀 매립 금속층에서 형성단계 이전에, 콘택홀내의 하부 배선층에 불순물을 이온주입하여 시드층을 형성한 후, 알루미늄 금속막을 성장시킴으로써, 콘택홀 내의 매립 특성을 향상시키게 되고, 표면 거칠음 현상이 방지된다.As described in detail above, according to the present invention, before forming the contact hole buried metal layer, an ion is implanted into the lower interconnection layer in the contact hole to form a seed layer, and then an aluminum metal film is grown to thereby form the inside of the contact hole. The buried property is improved, and surface roughness is prevented.

아울러, 전도 특성이 우수한 알루미늄 금속막을 매립 금속막으로 이용하여, 금속 배선이 전도 특성이 개선된다.In addition, by using an aluminum metal film having excellent conductivity as a buried metal film, the metal wiring has improved conductivity.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (2)

전도 영역을 구비한 반도체 기판상에 층간 절연막을 형성하는 단계; 상기 층간 절연막 상부에 소정 부분이 노출되도록 마스크 패턴을 형성하는 단계; 상기 마스크 패턴의 형태로 전도 영역의 소정 부분이 노출되도록 층간절연막을 식각하여, 콘택홀을 형성하는 단계; 상기 마스크 패턴 상부 및 상기 콘택홀내의 노출된 전도영역으로 불순물을 이온주입하여 이온주입층을 형성하는 단계; 상기 마스크 패턴을 제거하여 그의 상부에 형성된 이온주입층도 함께 제거하는 단계; 상기 콘택홀내의 이온주입층을 매개로 상기 콘택홀내에만 알루미늄으로된 매립 금속막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.Forming an interlayer insulating film on the semiconductor substrate having the conductive region; Forming a mask pattern on the interlayer insulating layer to expose a predetermined portion; Etching the interlayer insulating layer to expose a predetermined portion of the conductive region in the form of the mask pattern to form a contact hole; Forming an ion implantation layer by implanting impurities into the exposed conductive region in the upper portion of the mask pattern and the contact hole; Removing the mask pattern to remove the ion implantation layer formed thereon; And forming a buried metal film made of aluminum only in the contact hole through the ion implantation layer in the contact hole. 제1항에 있어서, 상기 불순물은 F, P, BF2, As, Ge, Si, Pb, Ar 중 선택되는 하나 또는 두개의 불순물로 이온 주입하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method of claim 1, wherein the impurities are implanted with one or two impurities selected from F, P, BF 2, As, Ge, Si, Pb, and Ar.
KR1019970030368A 1997-06-30 1997-06-30 Method for forming metal interconnection layer in semiconductor device KR100272270B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970030368A KR100272270B1 (en) 1997-06-30 1997-06-30 Method for forming metal interconnection layer in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970030368A KR100272270B1 (en) 1997-06-30 1997-06-30 Method for forming metal interconnection layer in semiconductor device

Publications (2)

Publication Number Publication Date
KR19990006146A KR19990006146A (en) 1999-01-25
KR100272270B1 true KR100272270B1 (en) 2000-12-01

Family

ID=19513056

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970030368A KR100272270B1 (en) 1997-06-30 1997-06-30 Method for forming metal interconnection layer in semiconductor device

Country Status (1)

Country Link
KR (1) KR100272270B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499630B1 (en) 2002-10-08 2005-07-05 주식회사 하이닉스반도체 Fabricating method of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05259110A (en) * 1992-03-12 1993-10-08 Sony Corp Formation method of metal plug in semiconductor device
KR960015793A (en) * 1994-10-11 1996-05-22 문정환 Manufacturing method of wiring metal thin film

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05259110A (en) * 1992-03-12 1993-10-08 Sony Corp Formation method of metal plug in semiconductor device
KR960015793A (en) * 1994-10-11 1996-05-22 문정환 Manufacturing method of wiring metal thin film

Also Published As

Publication number Publication date
KR19990006146A (en) 1999-01-25

Similar Documents

Publication Publication Date Title
US5607879A (en) Method for forming buried plug contacts on semiconductor integrated circuits
US5656556A (en) Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures
US4818723A (en) Silicide contact plug formation technique
US6933228B2 (en) Method of manufacturing of contact plug in a contact hole on a silicon substrate
JPS61503064A (en) Semiconductor integrated circuit gettered with phosphorus
KR20010016923A (en) Method for forming contact structure of semiconductor device
KR100375230B1 (en) Method for forming an interconnection of semiconductor device having a smooth surface
US5071789A (en) Method for forming a metal electrical connector to a surface of a semiconductor device adjacent a sidewall of insulation material with metal creep-up extending up that sidewall, and related device
KR100715389B1 (en) Boron-doped titanium nitride layer for high aspect ratio semiconductor devices
US6852579B2 (en) Method of manufacturing a semiconductor integrated circuit device
KR20000026588A (en) Semiconductor device having contact holes and method for manufacturing the same
US6746952B2 (en) Diffusion barrier layer for semiconductor wafer fabrication
US20030068882A1 (en) Method of manufacturing a contact plug for a semiconductor device
US5849625A (en) Planar field oxide isolation process for semiconductor integrated circuit devices using liquid phase deposition
US5700726A (en) Multi-layered tungsten depositions for contact hole filling
US5457070A (en) Method of forming a step compensated semiconductor device
US6054385A (en) Elevated local interconnect and contact structure
KR0171050B1 (en) Method of forming a wiring pattern for a semiconductor device
JP2892421B2 (en) Method for manufacturing semiconductor device
US7402487B2 (en) Process for fabricating a semiconductor device having deep trench structures
KR100272270B1 (en) Method for forming metal interconnection layer in semiconductor device
KR100415519B1 (en) Method of manufacturing a semiconductor device
KR19980056170A (en) Metal wiring formation method of semiconductor device
KR100376258B1 (en) Method for forming a plug of a semiconductor device
KR100340860B1 (en) Method for fabricating contact plug of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120720

Year of fee payment: 13

FPAY Annual fee payment

Payment date: 20130821

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee