KR100271493B1 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistor Download PDFInfo
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- KR100271493B1 KR100271493B1 KR1019980020046A KR19980020046A KR100271493B1 KR 100271493 B1 KR100271493 B1 KR 100271493B1 KR 1019980020046 A KR1019980020046 A KR 1019980020046A KR 19980020046 A KR19980020046 A KR 19980020046A KR 100271493 B1 KR100271493 B1 KR 100271493B1
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- amorphous silicon
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- 239000010409 thin film Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract 6
- 239000010408 film Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 238000005224 laser annealing Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 5
- 238000001816 cooling Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 238000010583 slow cooling Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
본 발명은 박막트랜지스터의 제조방법에 관한 것으로, 특히 활성층을 비정질 실리콘을 형성하고 비정질 실리콘을 레이저 어닐링 시켜 재결정화된 다결정 실리콘을 사용한 박막트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor using polycrystalline silicon recrystallized by forming amorphous silicon and laser annealing the amorphous silicon.
도 2는 종래의 박막 트랜지스터의 단면구조도로, 종래의 박막트랜지스터는 기판(1), 기판(1)의 상부에 박막 장비를 사용하여 산화막을 침적시켜 형성된 버퍼(Buffer)층(2), 버퍼층(2) 상부에 고농도로 도핑된 드레인영역(3a)과 소스영역(3b) 및 비도핑된 채널영역(Ⅰ)들이 형성되는 활성층(3), 활성층(3) 상부에 실리콘 산화막을 전면 침적하여 형성된 게이트 절연막(4) 및 게이트 절연막(4) 상부에 다결정 실리콘 또는 금속막을 전면에 침적한 후 사진식각공정에 의해 형성된 게이트 전극(5)으로 구성된다.FIG. 2 is a cross-sectional structure of a conventional thin film transistor, in which a conventional thin film transistor includes a substrate 1 and a buffer layer 2 and a buffer layer formed by depositing an oxide film on the substrate 1 using thin film equipment. 2) An active layer 3 having a heavily doped drain region 3a, a source region 3b, and an undoped channel region I formed thereon, and a gate formed by completely depositing a silicon oxide film on the active layer 3. And a gate electrode 5 formed by depositing a polycrystalline silicon or metal film on the entire surface of the insulating film 4 and the gate insulating film 4 by a photolithography process.
채널영역 및 드레인과 소스영역이 형성되는 활성층(3)은 비정질 실리콘(Amorphous Silicon) 또는 다결정 실리콘(Polycrystalline Silicon)으로 형성할 수 있다.The active layer 3 in which the channel region and the drain and the source region are formed may be formed of amorphous silicon or polycrystalline silicon.
다결정 실리콘은 비정질 실리콘에 비해 캐리어(Carrier)의 이동도가 크므로 다결정 실리콘을 이용한 박막트랜지스터(Thin film Transistor; TFT)는 스위칭(Switching) 특성이 뛰어나고 이로 인해 비정질 실리콘을 이용한 박막트랜지스터에 비해 보다 작은 면적으로 형성할 수 있다. 이는 액티브 매트릭스 액정표시장치에서 화소의 온/오프를 제어하는 박막트랜지스터를 작게 형성함으로써 액정표시장치의 개구율을 향상시킬 수 있다.Since polycrystalline silicon has a greater mobility of carriers than amorphous silicon, thin film transistors (TFTs) using polycrystalline silicon have excellent switching characteristics and thus are smaller than thin film transistors using amorphous silicon. It can form with area. This can improve the aperture ratio of the liquid crystal display by forming a thin film transistor that controls on / off of pixels in the active matrix liquid crystal display.
활성층을 다결정 실리콘으로 형성시키기 위하여 활성층을 직접 다결정 실리콘으로 증착하는 방법과 활성층을 비정질 실리콘으로 형성하고 비정질 실리콘을 재결정화 시켜 형성되는 다결정 실리콘으로 증착하는 방법이 있으나 비정질 실리콘을 레이저 어닐링(Laser Annealing)하여 다결정 실리콘으로 재결정화 시키는 방법은 비정질 실리콘의 표면을 레이저 빔에 의하여 약 1000℃ 이상의 고온으로 가열하여 녹이지만 기판(1)은 손상되지 않으므로 기판은 가격이 저렴한 저온용 유리를 사용할 수 있다.In order to form an active layer into polycrystalline silicon, there is a method of directly depositing an active layer into polycrystalline silicon and a method of forming an active layer into amorphous silicon and then depositing into polycrystalline silicon formed by recrystallizing amorphous silicon, but laser annealing of laser silicon is performed. In the method of recrystallization into polycrystalline silicon, the surface of amorphous silicon is heated and melted by a laser beam at a high temperature of about 1000 ° C. or more, but since the substrate 1 is not damaged, a low-temperature glass having low cost may be used.
활성층을 비정질 실리콘을 형성하고 비정질 실리콘을 레이저 어닐링하여 다결정 실리콘을 이용한 종래의 박막트랜지스터의 제조방법은 다음과 같다.A method of manufacturing a conventional thin film transistor using polycrystalline silicon by forming amorphous silicon and laser annealing the amorphous silicon is as follows.
유리기판(1)의 상부에 박막 장비를 사용하여 산화막을 침적시켜 버퍼층(2)을 형성하고, 버퍼층(2) 상부 전면에 비정질 실리콘으로 이루어진 활성층(3)을 증착하고, 활성층(3)을 패터닝한 후 활성층(3)을 다결정 실리콘으로 재결정화 시키기 위해 패터닝된 활성층(3)을 레이저 어닐링 한다. 패터닝된 활성층(3) 상부 및 버퍼층(2) 상부에 게이트 절연막(4)을 형성하고 게이트 절연막(4) 상부의 소정 위치에 다결정 실리콘 또는 금속으로 형성된 게이트 전극(5)을 형성한다. 게이트 전극(5) 형성 후 게이트 전극(5)을 마스크로 사용하여 고농도의 불순물을 이온주입(Ion Implantation)하여 게이트 전극(5) 하부의 활성층(3)은 비도핑되어 채널영역(Ⅰ)이 형성되고, 채널영역(Ⅰ)의 좌우측에는 이온주입된 고농도의 불순물에 의해 드레인영역(3a) 및 소스영역(3b)이 형성된다.An oxide film is deposited on the upper portion of the glass substrate 1 to form a buffer layer 2, the active layer 3 made of amorphous silicon is deposited on the entire upper surface of the buffer layer 2, and the active layer 3 is patterned. The patterned active layer 3 is then laser annealed to recrystallize the active layer 3 into polycrystalline silicon. The gate insulating film 4 is formed on the patterned active layer 3 and the buffer layer 2, and the gate electrode 5 formed of polycrystalline silicon or metal is formed at a predetermined position on the gate insulating film 4. After the gate electrode 5 is formed, a high concentration of impurities are implanted using the gate electrode 5 as a mask to undo the active layer 3 under the gate electrode 5 to form a channel region I. On the left and right sides of the channel region I, the drain region 3a and the source region 3b are formed by the high concentration of impurities implanted with ions.
게이트 전극(5)이 다결정 실리콘으로 형성된 경우 게이트 전극(5)을 마스크로 사용함으로써 고농도로 불순물의 이온주입시 드레인영역(3a) 및 소스영역(3b)은 게이트 전극(5)에 의해 자동적으로 그 위치가 자기정합(Self-Align)되며, 게이트 전극(5)이 금속으로 형성된 경우 게이트 전극(5)을 사진식각공정에 의해 패터닝하기 위한 감광막 패턴을 마스크로 고농도의 불순물을 이온주입 하여 활성층(3)에 드레인영역(3a) 및 소스영역(3b)을 형성한다.When the gate electrode 5 is formed of polycrystalline silicon, the drain region 3a and the source region 3b are automatically formed by the gate electrode 5 when ion implantation of impurities at high concentration is performed by using the gate electrode 5 as a mask. When the self-aligned position is formed and the gate electrode 5 is formed of metal, the active layer 3 is ion-implanted with a high concentration of impurities using a photosensitive film pattern for patterning the gate electrode 5 by a photolithography process. ), The drain region 3a and the source region 3b are formed.
상기의 비정질 실리콘을 레이저 어닐링하여 다결정 실리콘을 이용한 종래의 박막트랜지스터 제조방법은 비정질 실리콘으로 형성된 활성층에 직접 레이저 빔을 조사하는 레이저 어닐링하여 비정질 실리콘을 다결정 실리콘으로 재결정화 시키나 재결정화 과정에서 결정립이 성장할수록 활성층의 표면이 거칠어져 활성층의 표면은 균일하지 못하고, 결정의 크기가 부위별로 상이하므로 활성층 상부의 게이트 절연막과의 밀착성(Adhesion)이 좋지 못하고, 전하의 이동도도 균일하지 못한 문제점을 가지고 있다.The conventional thin film transistor manufacturing method using the polycrystalline silicon by laser annealing the amorphous silicon is a laser annealing by irradiating a laser beam directly to the active layer formed of amorphous silicon to recrystallize the amorphous silicon into polycrystalline silicon, but crystal grains grow in the recrystallization process As the surface of the active layer becomes rougher, the surface of the active layer is not uniform, and the size of crystals is different for each part, so that the adhesion to the gate insulating film on the upper part of the active layer is poor and the mobility of charge is not uniform. .
본 발명의 목적은 비정질 실리콘 상부에 캐핑층을 형성하고 사진식각공정으로 캐핑층을 수직으로 식각하고 활성층은 경사지게 식각하고 캐핑층 상부에 레이저 빔을 조사함으로써 경사식각된 활성층의 양측면에서 빠른 냉각속도에 의해 핵이 우선적으로 생성되고 캐핑층으로 덮여진 활성층은 느린 냉각속도로 인해 결정성장만 발생되어 생성된 핵이 활성층의 채널영역 중앙쪽으로 조대하고 균일한 그레인으로 성장되어 전하의 이동도를 향상시킬 수 있고, 활성층의 표면은 균일하게 되어 게이트 절연막과의 밀착성을 향상시킬 수 있는 박막트랜지스터 제조방법을 제공하는 데 있다.An object of the present invention is to form a capping layer on the amorphous silicon, and to etch the capping layer vertically by a photolithography process, the active layer is inclined etched and irradiated with a laser beam on the capping layer to increase the fast cooling speed at both sides of the inclined etched active layer The nucleus is first generated and the active layer covered with the capping layer generates only crystal growth due to the slow cooling rate, so that the generated nucleus is grown into coarse and uniform grain toward the center of the channel region of the active layer, thereby improving charge mobility. In addition, the surface of the active layer is uniform to provide a thin film transistor manufacturing method that can improve the adhesion with the gate insulating film.
상기의 목적을 달성하기 위하여 본 발명의 박막트랜지스터 제조방법은 기판에 버퍼층 및 비정질 실리콘층을 순차적으로 형성하는 단계, 비정질 실리콘 상부에 캐핑층을 증착하는 단계, 캐핑층 상부에 감광막 패턴을 형성하여 감광막 패턴을 마스크로 캐핑층은 수직으로 식각하고 비정질 실리콘은 경사지게 식각하여 활성층을 형성하는 단계, 감광막 패턴을 제거하고 비정질 실리콘으로 형성된 활성층을 다결정 실리콘으로 재결정화 시키는 단계, 캐핑층을 제거하고 버퍼층 및 활성층 상부에 게이트 절연막을 형성하고 게이트 절연막 상부의 소정 위치에 게이트 전극을 형성하는 단계 및 게이트 전극 형성 후 고농도의 불순물을 이온주입하여 게이트 전극 하부의 활성층에 비도핑된 채널영역을 형성시키고 채널영역의 좌우측에 이온주입된 고농도의 불순물에 의해 드레인영역 및 소스영역을 형성시키는 단계를 구비한 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention includes sequentially forming a buffer layer and an amorphous silicon layer on a substrate, depositing a capping layer on the amorphous silicon, and forming a photoresist pattern on the capping layer. Using a pattern as a mask, the capping layer is vertically etched and the amorphous silicon is etched obliquely to form an active layer, the photoresist pattern is removed, and the active layer formed of amorphous silicon is recrystallized with polycrystalline silicon, the capping layer is removed, and the buffer layer and the active layer are removed. Forming a gate insulating film on the upper portion of the gate insulating film, forming a gate electrode at a predetermined position on the gate insulating film, and implanting a high concentration of impurities after forming the gate electrode to form an undoped channel region in the active layer below the gate electrode, High concentration of ion-implanted fire Characterized in that it includes the step of forming the drain region and the source region by the water.
캐핑층은 열전도도가 낮은 재질인 실리콘 산화막 및 산화아연들 중 어느 한 재질로 이루어진 것을 특징으로 한다.The capping layer is made of any one of silicon oxide film and zinc oxide, which is a material having low thermal conductivity.
도 1a 내지 도 1f는 본 발명에 따른 박막트랜지스터의 제조방법을 도시한1A to 1F illustrate a method of manufacturing a thin film transistor according to the present invention.
공정순서도,Process Flowchart,
도 2는 종래의 박막트랜지스터의 단면구조도이다.2 is a cross-sectional structure diagram of a conventional thin film transistor.
이하, 첨부된 도면을 참조하여 본 발명의 박막트랜지스터의 제조방법을 상세히 설명하고자 한다.Hereinafter, a method of manufacturing a thin film transistor of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1g는 본 발명에 따른 박막트랜지스터의 제조방법을 도시한 공정단면도이다.1A to 1G are cross-sectional views illustrating a method of manufacturing a thin film transistor according to the present invention.
도1의 본 발명의 박막트랜지스터의 제조방법은 기판(11)에 버퍼층(12) 및 비정질 실리콘층(13)을 순차적으로 형성하는 단계, 비정질 실리콘(13) 상부에 캐핑층(14)을 증착하는 단계, 캐핑층(14) 상부에 감광막 패턴(PR)을 형성하여 감광막 패턴(PR)을 마스크로 캐핑층(14)은 수직으로 식각하고 비정질 실리콘(13)은 경사지게 식각하여 활성층(13a)을 형성하는 단계, 감광막 패턴(PR)을 제거하고 비정질 실리콘으로 형성된 활성층(13a)을 다결정 실리콘으로 재결정화 시키기 위하여 활성층(13a) 및 패터닝된 캐핑층(14a) 상부에 레이저 빔을 조사하는 단계, 패터닝된 캐핑층(14a)을 제거하고 버퍼층(12) 및 활성층(13a) 상부에 게이트 절연막(15)을 형성하고 게이트 절연막(15) 상부의 소정 위치에 게이트 전극(16)을 형성하는 단계 및 게이트 전극(16) 형성 후 고농도의 불순물을 이온주입하여 게이트 전극(16) 하부의 활성층(13a)에 비도핑된 채널영역(Ⅰ)을 형성시키고 채널영역(Ⅰ)의 좌우측에 이온주입된 고농도의 불순물에 의해 드레인영역 및 소스영역(13b)을 형성시키는 단계로 구성된다.In the method of manufacturing the thin film transistor of FIG. 1, the buffer layer 12 and the amorphous silicon layer 13 are sequentially formed on the substrate 11, and the capping layer 14 is deposited on the amorphous silicon 13. Step, the photoresist pattern PR is formed on the capping layer 14, and the capping layer 14 is vertically etched and the amorphous silicon 13 is etched obliquely using the photoresist pattern PR as a mask to form the active layer 13a. Irradiating a laser beam over the active layer 13a and the patterned capping layer 14a to remove the photoresist pattern PR and recrystallize the active layer 13a formed of amorphous silicon into polycrystalline silicon. Removing the capping layer 14a, forming the gate insulating layer 15 on the buffer layer 12 and the active layer 13a, and forming the gate electrode 16 at a predetermined position on the gate insulating layer 15 and the gate electrode ( 16) After formation, high concentration of impurities Implantation to form a undoped channel region (I) in the active layer (13a) below the gate electrode (16) and drain and source regions (13b) by the high concentration of impurities implanted into the left and right sides of the channel region (I) Forming step.
캐핑층(14) 및 비정질 실리콘(13)은 건식식각으로 식각하며, 캐핑층(14)은 열전도도가 낮은 재질인 실리콘 산화막(SiO2) 및 산화아연(ZnO)들 중 어느 한 재질로 이루어진다.The capping layer 14 and the amorphous silicon 13 are etched by dry etching, and the capping layer 14 is made of any one of silicon oxide film (SiO 2 ) and zinc oxide (ZnO), which are materials having low thermal conductivity.
본 발명의 박막트랜지스터의 제조방법을 첨부된 도 1a 내지 도 1f를 참조하여 설명하면 다음과 같다.A method of manufacturing the thin film transistor of the present invention will be described with reference to FIGS. 1A to 1F.
도 1a에 도시된 바와 같이 기판(11)에 500Å 내지 3000Å 정도의 두께로 열전도도가 낮은 물질인 실리콘 산화막(SiO2) 등을 증착하여 버퍼층(12)을 형성하고, 버퍼층(12) 상부에 플라즈마 화학 기상 증착(Plasma Enhanced Chemical Vapor Deposition:PECVD)으로 500Å 내지 1000Å 정도의 두께의 비정질 실리콘층(13)을 형성한다. 도 1b와 같이 비정질 실리콘(13) 상부에 열전도도가 낮은 재질인 실리콘 산화막(SiO2) 및 산화아연(ZnO) 등을 사용하여 500Å 내지 3000Å 정도의 두께로 캐핑층(14)을 증착한다. 도 1c와 같이 사진식각공정을 사용하여 활성영역을 패터닝하기 위하여 캐핑층(14) 상부에 감광막 패턴(PR)을 형성한다. 도 1d에 도시된 바와 같이 감광막 패턴(PR)을 식각 마스크로 하여 캐핑층(14)은 수직으로 식각하여 패터닝된 캐핑층(14a)을 형성하고, 비정질 실리콘(13)은 경사지게 식각하여 활성층(13a)을 형성한다. 즉, 활성층(13a)은 양 끝단부가 경사지며, 경사진 양 끝단부는 패터닝된 캐핑층(14a)으로 덮이지 않는다. 도 1e에 도시된 바와 같이 감광막 패턴(PR)을 제거하고 비정질 실리콘으로 형성된 활성층(13a)을 다결정 실리콘으로 재결정화 시키기 위하여 활성층(13a) 및 패터닝된 캐핑층(14a) 상부에 레이저 빔을 조사하여 레이저 어닐링을 한다. 레이저 어닐링시 활성층(13a)의 경사진 양 끝단부는 캐핑층(14a) 외부로 노출되어 있으므로 냉각속도가 빠르고, 캐핑층(14a)으로 덮여져 있는 활성층(13a)은 열전도도가 낮은 캐핑층(14a)에 의하여 냉각속도는 느리다. 냉각속도가 빠른 활성층(13a)의 경사진 양 끝단부는 핵(13b) 생성이 빨리 이루어지고, 냉각속도가 느린 캐핑층(14a)으로 덮여져 있는 활성층(13a)은 결정성장만 이루어지므로 활성층(13a)의 경사진 양 끝단부에서 생성된 핵(13b)들에 의해 활성층(13a)의 가운데 부분으로 그레인(Grain)이 성장되어 활성층(13a)에는 조대한 두 개의 그레인(13c)이 생성되어 전하의 이동도를 향상시킬 수 있다. 또한 캐핑층(14a)으로 덮여져 있는 활성층(13a)은 비정질 실리콘으로부터 다결정 실리콘으로 결정화가 이루어졌을 때 다결정 실리콘의 표면 상태는 매우 균일해지므로 활성층(13a)과 후공정에 생성되는 게이트 절연막(15)과의 밀착성이 좋아진다.As shown in FIG. 1A, a silicon oxide film (SiO 2 ) or the like having a low thermal conductivity is deposited on the substrate 11 to form a buffer layer 12, and a plasma is formed on the buffer layer 12. Plasma Enhanced Chemical Vapor Deposition (PECVD) forms an amorphous silicon layer 13 having a thickness of about 500 kV to 1000 kPa. As shown in FIG. 1B, the capping layer 14 is deposited on the amorphous silicon 13 using a silicon oxide film (SiO 2 ), zinc oxide (ZnO), or the like having a low thermal conductivity. A photoresist pattern PR is formed on the capping layer 14 to pattern the active region using a photolithography process as shown in FIG. 1C. As shown in FIG. 1D, the capping layer 14 is vertically etched using the photoresist pattern PR as an etch mask to form a patterned capping layer 14a, and the amorphous silicon 13 is etched obliquely to form an active layer 13a. ). In other words, both ends of the active layer 13a are inclined, and both of the inclined ends are not covered with the patterned capping layer 14a. As shown in FIG. 1E, a laser beam is irradiated on the active layer 13a and the patterned capping layer 14a to remove the photoresist pattern PR and recrystallize the active layer 13a formed of amorphous silicon into polycrystalline silicon. Laser annealing is performed. Since the inclined ends of the active layer 13a are exposed outside the capping layer 14a during laser annealing, the cooling rate is high, and the active layer 13a covered with the capping layer 14a has a low thermal conductivity capping layer 14a. Cooling rate is slow. Since the inclined ends of the active layer 13a having a high cooling rate are rapidly formed in the nucleus 13b, the active layer 13a covered with the capping layer 14a having a slow cooling rate only undergoes crystal growth, so the active layer 13a Grain grows in the center portion of the active layer 13a by the nuclei 13b generated at both ends of the inclined ends of the crest. Thus, two coarse grains 13c are formed in the active layer 13a. Mobility can be improved. In addition, when the active layer 13a covered by the capping layer 14a is crystallized from amorphous silicon to polycrystalline silicon, the surface state of the polycrystalline silicon becomes very uniform, so that the gate insulating film 15 generated in the active layer 13a and the subsequent process is performed. ) Good adhesion with).
도 1f에 도시된 바와 같이 패터닝된 캐핑층(14a)을 제거하고 버퍼층(12) 및 활성층(13a) 상부에 게이트 절연막(15)을 형성하고, 게이트 절연막(15) 상부의 소정 위치에 게이트 전극(16)을 형성한다. 게이트 전극(16)은 다결정 실리콘 또는 금속으로 형성할 수 있다. 게이트 전극(16) 형성 후 고농도의 불순물을 이온주입하여 게이트 전극(16) 하부의 활성층(13a)에는 비도핑된 채널영역(Ⅰ)이 형성되고, 채널영역(Ⅰ)의 좌우측에는 이온주입된 고농도의 불순물에 의해 드레인영역 및 소스영역(13d)이 형성된다.As shown in FIG. 1F, the patterned capping layer 14a is removed, and the gate insulating layer 15 is formed on the buffer layer 12 and the active layer 13a, and the gate electrode is disposed at a predetermined position on the gate insulating layer 15. 16). The gate electrode 16 may be formed of polycrystalline silicon or metal. After the gate electrode 16 is formed, a high concentration of impurities are ion implanted to form an undoped channel region I in the active layer 13a below the gate electrode 16, and a high concentration of ion implantation in left and right sides of the channel region I. The drain region and the source region 13d are formed by impurities.
본 발명은 경사식각된 활성층의 양측면에서 핵이 생성되고 캐핑층으로 덮여진 활성층은 결정성장만 발생되어 생성된 핵에 의해 활성층의 채널영역 중앙쪽으로 조대하고 균일한 그레인이 성장되어 전하의 이동도를 향상시킬 수 있고, 활성층의 표면은 균일하게 되어 게이트 절연막과의 밀착성을 향상시킬 수 있다.In the present invention, nuclei are generated on both sides of the inclined etched active layer, and the active layer covered with the capping layer generates only crystal growth, whereby coarse and uniform grains are grown toward the center of the channel region of the active layer by the generated nucleus to increase the mobility of charge. The surface of the active layer can be made uniform, and the adhesion to the gate insulating film can be improved.
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| KR100847846B1 (en) * | 2007-08-01 | 2008-07-23 | 실리콘 디스플레이 (주) | Manufacturing method of thin film transistor by local-doppong and apparatus by the same |
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