KR100264079B1 - Manufacturing method of a semiconductor device - Google Patents

Manufacturing method of a semiconductor device Download PDF

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KR100264079B1
KR100264079B1 KR1019970030211A KR19970030211A KR100264079B1 KR 100264079 B1 KR100264079 B1 KR 100264079B1 KR 1019970030211 A KR1019970030211 A KR 1019970030211A KR 19970030211 A KR19970030211 A KR 19970030211A KR 100264079 B1 KR100264079 B1 KR 100264079B1
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semiconductor substrate
oxide film
forming
film
blocking layer
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KR1019970030211A
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Korean (ko)
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KR19990005989A (en
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김태우
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A method for manufacturing semiconductor devices is provided to prevent etching of a bird's beak at an end of a device separation film when a spacer oxide film is formed by a subsequent process. CONSTITUTION: A method for manufacturing semiconductor devices forms a device isolation film(2) in a semiconductor substrate(1) by device isolation process to define an active region. A blocking layer(8) is formed on the entire surface and a photoresist pattern is then formed on the device isolation film(2) as a blocking mask. Then, the blocking layer on the active region is etched to expose the semiconductor substrate(1). A gate oxide film(10) is formed in the exposed semiconductor substrate(1) by oxidization process. A polysilicon layer is deposited on the entire surface and the polysilicon layer is dry-etched by means of an etching process using a gate mask, thus forming gates(3,4) on the semiconductor substrate(1) and the device isolation film(2). Low concentration impurities are injected into the semiconductor substrate(1) with the energy of 30-40KeV to form a low concentration region. An oxide film is formed on the entire surface and the oxide film is then dry-etched by blanket etch process to form a spacer oxide film(6) at the sidewalls of the gates(3,4). High concentration impurities are injected with the energy of 30-40KeV to form a source/drain junction(7) via thermal process.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 DRAM에서 가장 문제시되는 리프레쉬(Refresh) 및 트랜지스터의(Transistor)의 소오스/드레인 접합 특성을 개선시켜 소자의 신뢰성을 향상시키고, 수율을 증가시키는 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the semiconductor device fabrication method improves the source / drain junction characteristics of refresh and transistor, which are the most problematic problems in DRAM, to improve device reliability and increase yield. It is about a method.

반도체 소자의 트랜지스터 형성 공정은 반도체 기판(1)에 소자분리(Isolation)공정으로 소자분리막(2)을 형성한 후, 웰(Well)을 형성한다(도시안됨). 그리고, 게이트 산화막(도시안됨)을 형성하고, 그 상부에 게이트인 폴리실리콘층을 증착한 다음 게이트 마스크를 이용하여 폴리실리콘층을 건식 식각하여 게이트 전극(3, 4)을 형성한다. 그리고, 상기 식각공정에서 발생되는 손상(Damage)을 보상해 주기 위하여 산화(Oxidation) 공정을 실시한 후, 저농도 불순물(LDD Implant)을 반도체 기판(1)의 표면으로 이온 주입하여 저농도 영역(5)을 형성한다. (제1(a)도 참조).In the process of forming a transistor of a semiconductor device, a device isolation film 2 is formed on a semiconductor substrate 1 by an isolation process, and then a well is formed (not shown). A gate oxide layer (not shown) is formed, a polysilicon layer as a gate is deposited on the gate oxide, and the polysilicon layer is dry-etched using a gate mask to form gate electrodes 3 and 4. After performing an oxidation process to compensate for the damage generated in the etching process, a low concentration impurity (LDD Implant) is ion-implanted onto the surface of the semiconductor substrate 1 to form a low concentration region 5. Form. (See also first (a).)

상기 공정후 게이트 전극(3, 4)의 측벽에 스페이서 산화막(6)을 형성하기 위하여 산화막을 증착한 후, 건식 식각 공정을 진행한다. 이때 소자분리막(2)의 단부인 필드 영역과 액티브 영역의 사이에 위치하는 스페이서 산화막(6)을 형성하기 위한 건식 식각 공정에서 상기 소자분리막(2)의 버즈 빅 부분이 식각되어 요홈 또는 손상(15)이 형성된다. (제1(b)도 참조).After the process, the oxide film is deposited to form the spacer oxide film 6 on the sidewalls of the gate electrodes 3 and 4, followed by a dry etching process. At this time, in the dry etching process for forming the spacer oxide film 6 positioned between the field region, which is an end of the device isolation film 2, and the active region, the buzz big portion of the device isolation film 2 is etched to cause grooves or damage (15). ) Is formed. (See also first (b).)

이후 고농도 불순물을 이온 주입하고, 열공정에 의해 반도체 기판(1)으로 고농도 불순물을 확산시켜 소오스/드레인 접합(7)을 형성하게 되는데 상기 소자분리막(2)의 단부에서 발생된 요홈 또는 손상 부분으로 고농도 불순물이 주입되면서 반도체 기판에 디스로케이션(Dislocation)이 발생되고, 또한, 이부분에서 소오스/드레인 접합(7)의 하부 경계면에서 하측으로 돌출부(20)가 형성되어 누설전류의 원인이 되며, 돌출된 접합의 형성으로 이부분에서 큰 전계에 의해 접합 항복 전압이 낮아진다. (제1(c)도 참조)Thereafter, a high concentration of impurities are ion-implanted, and a high concentration of impurities are diffused into the semiconductor substrate 1 by a thermal process to form a source / drain junction 7, which is a recess or damage portion generated at the end of the device isolation film 2. Dislocation occurs in the semiconductor substrate as a high concentration of impurities are injected, and a protrusion 20 is formed at the lower side of the lower interface of the source / drain junction 7 at this portion, which causes leakage current. As a result of the formation of the junction, the junction breakdown voltage is lowered by the large electric field in this region. (See also first (c).)

그결과 DRAM에서 가장 중요한 리프레쉬(Refresh) 특성을 저하 시키고, 소자의 특성을 저하시키게 된다.As a result, the most important refresh characteristics in DRAMs are degraded and device characteristics are degraded.

본 발명에서는 앞에서 언급한 종래의 문제점을 해결하기 위하여 실리콘기판에 소자분리막을 형성하고, 반도체 기판의 표면에 블로킹 층(Blocking Layer)을 증착한 후, 액티브 영역의 블로킹 층을 제거함으로서 소자분리막 단부에도 블로킹 층을 남겨두어서 후속 공정으로 스페이서 산화막을 형성할 때 소자분리막 단부에서 버즈 빅이 식각되는 현상을 방지하는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.In the present invention, in order to solve the above-mentioned problems, a device isolation film is formed on a silicon substrate, a blocking layer is deposited on the surface of the semiconductor substrate, and then the blocking layer of the active region is removed. An object of the present invention is to provide a method of manufacturing a semiconductor device that prevents a phenomenon in which a buzz big is etched at the end of a device isolation layer when the spacer oxide layer is formed in a subsequent process by leaving a blocking layer.

제1(a)도 내지 제1(c)도는 종래 기술에 의해 반도체 소자를 형성하는 공정단계를 도시한 단면도이다.1 (a) to 1 (c) are cross-sectional views showing the process steps for forming a semiconductor device according to the prior art.

제2(a)도 내지 제2(c)도는 본 발명에 의해 반도체 소자를 형성하는 공정단계를 도시한 단면도이다.2 (a) to 2 (c) are cross-sectional views showing the process steps for forming a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호 설명* Explanation of symbols on the main parts of the drawings

1 : 반도체 기판 2 : 소자분리막1 semiconductor substrate 2 device isolation film

3, 4 : 게이트 전극 5 : 저농도 영역3, 4: gate electrode 5: low concentration region

6 : 스페이서 산화막 7 : 소오스/드레인 접합6 spacer oxide film 7 source / drain junction

8 : 블로킹 층 10 : 게이트 산화막8: blocking layer 10: gate oxide film

상기 목적을 달성하기 위한 본 발명은 반도체 소자 제조 방법에 있어서, 상기 반도체 기판에 소자분리막을 형성하는 단계와, 상기 소자분리막과 소자분리막의 버즈 빅 상부면에 블로킹 층을 형성하는 단계와, 상기 반도체 기판의 표면에 게이트 산화막을 형성하는 단계와, 상기 반도체 기판 상부와 소자분리막 상부에 게이트 전극을 형성하는 단계와, 저농도 불순물을 상기 반도체 기판으로 이온 주입하여 저농도 영역을 형성하는 단계와, 상기 게이트 전극의 측벽에 스페이서 산화막을 형성하되 스페이서 산화막이 상기 블로킹 층에 의해 버즈 빅 부분이 손상되지 않도록 하는 하는 단계와, 고농도 불순물을 반도체 기판으로 이온주입하여 소오스/드레인 접합을 형성하는 단계를 포함한다.According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: forming an isolation layer on the semiconductor substrate, forming a blocking layer on a buzz big upper surface of the isolation layer and the isolation layer; Forming a gate oxide film on the surface of the substrate, forming a gate electrode on the semiconductor substrate and an isolation layer, ion implanting low concentration impurities into the semiconductor substrate to form a low concentration region, and the gate electrode Forming a spacer oxide film on sidewalls of the spacer oxide to prevent the spacer oxide film from being damaged by the blocking layer, and ion implanting a high concentration of impurities into the semiconductor substrate to form a source / drain junction.

상기한 본 발명에 의하면 고농도 불순물 이온주입후 열공정을 거칠 때 접합영역의 저면에서 돌출되는 영역을 방지하여 누설 전류를 감소시키고, 리프레쉬 특성을 개선하고, 접합의 항복전압을 증가 시킬 수 있다.According to the present invention described above, when the thermal process is performed after the implantation of high concentration impurity ions, a region protruding from the bottom of the junction region can be prevented to reduce leakage current, improve refresh characteristics, and increase breakdown voltage of the junction.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제2(a)도는 반도체 소자의 트랜지스터 형성 공정은 반도체기판(1)에 소자분리(Isolation) 공정으로 소자분리막(2)을 형성하여 활성영역을 정의한 후, 웰(Well)을 형성한다(도시안됨). 그리고, 블로킹 층(8)을 전면에 걸쳐 형성한 다음, 블로킹 마스크(9)로 감광막 패턴을 상기 소자분리막(2)의 상부에 형성한 후 액티브영역 상부에 있는 블로킹 층(8)을 식각하여 반도체기판(1)을 노출시킨 단면도로서, 상기 남아 있는 블로킹 층(8)이 상기 소자분리막(2)의 버즈 빅 부분까지 오버랩 됨을 도시하며, 상기 블로킹 층(8)은 질화막, 산화질화막(Oxynitride), TEOS(Tetra Ethyl Ortho Silicate) 산화막 중의 하나를 이용할 수 있으며 20∼200Å의 두께로 증착한다. 그리고, 상기 블로킹 마스크(9)는 소자분리 마스크 보다 액티브 영역으로 0.25∼0.3㎛ 연장된다.In the process of forming a transistor of the semiconductor device of FIG. 2 (a), the isolation layer 2 is formed on the semiconductor substrate 1 by an isolation process to define an active region, and then a well is formed (not shown). ). After forming the blocking layer 8 over the entire surface, the photoresist pattern is formed on the device isolation layer 2 using the blocking mask 9, and then the blocking layer 8 on the active region is etched. A cross-sectional view of the substrate 1 exposed, showing that the remaining blocking layer 8 overlaps the buzz big portion of the device isolation film 2, and the blocking layer 8 includes a nitride film, an oxynitride film, One of TEOS (Tetra Ethyl Ortho Silicate) oxide films may be used and is deposited to a thickness of 20 to 200 Å. The blocking mask 9 extends 0.25 to 0.3 탆 into the active region than the device isolation mask.

제2(b)도는 상기 블로킹 마스크(9)를 제거한 다음, 산화 공정으로 노출된 반도체 기판(1)에 게이트 산화막(10)을 형성하고, 전체적으로 폴리실리콘층을 증착한 다음, 게이트 마스크를 이용한 식각 공정으로 상기 폴리실리콘층을 건식 식각하여 반도체 기판(1)과 소자분리막(2)의 상부에 각각 게이트 전극(3, 4)을 형성한 다음, 상기 식각 공정시 발생되는 손상을 보상해 주기 위하여 산화공정을 실시하고 난 후, 저농도 불순물을 반도체기판(1)으로 30∼40KeV의 에너지로 이온 주입하여 저농도 영역(5)을 형성한 도면이다.In FIG. 2 (b), after the blocking mask 9 is removed, the gate oxide film 10 is formed on the semiconductor substrate 1 exposed by the oxidation process, the polysilicon layer is entirely deposited, and then the etching is performed using the gate mask. In the process, the polysilicon layer is dry-etched to form gate electrodes 3 and 4 on the semiconductor substrate 1 and the device isolation layer 2, respectively, and then oxidized to compensate for the damage generated during the etching process. After the step is performed, the low concentration region 5 is formed by ion implanting low concentration impurities into the semiconductor substrate 1 at an energy of 30 to 40 KeV.

제2(c)도는 전체적으로 산화막을 증착한 다음, 전면(Blanket) 식각 공정으로 상기 산화막을 건식 식각하여 게이트 전극(3, 4)의 측벽에 스페이서 산화막(6)을 형성하고, 고농도 불순물을 30∼40 KeV의 에너지로 이온 주입하고, 열공정을 거쳐서 소오스/드레인 접합(7)을 형성한 단면도이다.In FIG. 2 (c), the oxide film is entirely deposited, and then the oxide film is dry-etched by a blanket etching process to form a spacer oxide film 6 on the sidewalls of the gate electrodes 3 and 4, and to form a high concentration impurity 30 to 30. It is sectional drawing in which the source / drain junction 7 was formed by ion implantation with the energy of 40 KeV, and the thermal process.

여기서, 본 발명은 블로킹 층(8)이 소자분리막(2)의 버즈 빅 부분까지 오버랩 되어 있음으로서 게이트 전극(3, 4)의 측벽에 스페이서 산화막(6)을 형성하기 위한 식각 공정에서 소자분리막(2)의 버즈 빅 부분이 손상되는 것을 방지 할 수가 있으므로 이온주입에 의해 접합영역을 형성하게 되면 접합영역의 저면이 완만한 것을 알 수가 있다.Here, in the etching process for forming the spacer oxide film 6 on the sidewalls of the gate electrodes 3 and 4 because the blocking layer 8 overlaps the buzz big portion of the device isolation film 2, the device isolation film ( Since the buzz big part of 2) can be prevented from being damaged, when the junction region is formed by ion implantation, the bottom surface of the junction region is smooth.

상기한 본 발명은 소자분리막의 버즈 빅 까지 블로킹층을 남긴 상태에서 식각공정 및 이온 주입 공정을 실시함으로써 접합영역의 저면이 완만한 굴곡을 가짐으로써 접합 누설 전류가 발생되는 것이 억제되고, 누설 전류를 줄임으로써 리프레쉬 특성을 개선시키고, 접합에서 돌출부 형성이 방지되어 접합의 항복 전압을 증가시켜 소자의 수율 및 신뢰성을 향상시킨다.According to the present invention, by performing the etching process and the ion implantation process in the state of leaving the blocking layer to the buzz big of the device isolation film, the bottom surface of the junction region has a gentle bend, thereby preventing the occurrence of the junction leakage current, Reduction improves the refresh characteristics and prevents the formation of protrusions in the junction, thereby increasing the breakdown voltage of the junction to improve device yield and reliability.

Claims (5)

반도체 소자 제조 방법에 있어서, 상기 반도체기판에 소자분리막을 형성하여 활성영역을 정의하는 단계와, 상기 소자분리막의 버즈 빅 상부면에 블로킹 층을 형성하되, 상기 활성영역과 일정 폭만큼 중첩되게 형성하는 단계와, 상기 반도체기판의 표면에 게이트 산화막을 형성하는 단계와, 상기 반도체기판 상부에 게이트 전극을 형성하는 단계와, 저농도 불순물을 상기 반도체기판으로 이온 주입하여 저농도 영역을 형성하는 단계와, 상기 게이트 전극의 측벽에 스페이서 산화막을 형성하되 스페이서 산화막이 상기 블로킹 층에 의해 버즈 빅 부분이 손상되지 않도록 하는 단계와, 고농도 불순물을 반도체기판으로 이온 주입하여 소오스/드레인 접합영역을 형성하는 단계를 포함하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, comprising: forming an isolation layer on the semiconductor substrate to define an active region, and forming a blocking layer on a buzz big upper surface of the isolation layer, and overlapping the active region by a predetermined width Forming a gate oxide film on the surface of the semiconductor substrate, forming a gate electrode on the semiconductor substrate, ion implanting low concentration impurities into the semiconductor substrate, and forming a low concentration region; Forming a spacer oxide film on a sidewall of the electrode, wherein the spacer oxide film is not damaged by the blocking layer, and ion implanting a high concentration of impurities into the semiconductor substrate to form a source / drain junction region; Method of manufacturing the device. 제1항에 있어서, 상기 블로킹 층은 질화막 또는 산화 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the blocking layer is formed of a nitride film or an oxynitride film. 제1항에 있어서, 블로킹 층의 두께를 50∼200Å으로 하는 것을 특징으로 하는 반도체 소자의 제조방법.The method for manufacturing a semiconductor device according to claim 1, wherein the blocking layer has a thickness of 50 to 200 kPa. 제1항에 있어서, 블로킹 층을 형성할 때 이용되는 마스크는 소자분리 마스크 보다 0.25∼0.30㎛정도 큰 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the mask used when forming the blocking layer is about 0.25 to 0.30 μm larger than the device isolation mask. 제1항에 있어서, 상기 저농도 이온 주입 또는 고농도 이온 주입 에너지는 30∼40 KeV로 하는 것을 특징으로 하는 반도체 소자 제조방법.The method according to claim 1, wherein the low concentration ion implantation or high concentration ion implantation energy is 30 to 40 KeV.
KR1019970030211A 1997-06-30 1997-06-30 Manufacturing method of a semiconductor device KR100264079B1 (en)

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