KR100259166B1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR100259166B1
KR100259166B1 KR1019970059226A KR19970059226A KR100259166B1 KR 100259166 B1 KR100259166 B1 KR 100259166B1 KR 1019970059226 A KR1019970059226 A KR 1019970059226A KR 19970059226 A KR19970059226 A KR 19970059226A KR 100259166 B1 KR100259166 B1 KR 100259166B1
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film
tungsten silicide
amorphous silicon
polysilicon
polysilicon film
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KR1019970059226A
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KR19990039217A (en
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박상훈
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: A manufacturing method of semiconductor device is provided to prevent fluoro atoms within a tungsten silicide from being diffused into a gate insulating film to enhance the reliability of gate electrodes and gate insulating film. CONSTITUTION: A polysilicon film(3) having impurities doped is formed on a semiconductor substrate(1), and the resultant is baked to grow a natural oxide on a surface of the polysilicon film. An HMDS(hexamethyldisilazane: (CH3)3Si-NH-Si(CH3)3) is coated on the baked polysilicon film. An amorphous silicon film(4) is formed by using the bondage of the natural oxide and (CH3)3Si as a growth seed, wherein (CH3) is presented in the interface between the amorphous silicon film and polysilicon film. A tungsten silicide film(5) is formed on the amorphous silicon film(4), wherein the (CH3) prevents atoms within the tungsten silicide film(5) from being diffused.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 구체적으로는, 텅스텐 실리사이드-폴리실리콘 구조의 게이트 전극 형성에 있어서, 텅스텐 실리사이드내의 불소 원자의 확산을 방지하기 위한 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for preventing diffusion of fluorine atoms in tungsten silicide in forming a gate electrode of a tungsten silicide-polysilicon structure.

최근 많은 반도체 소자에서 실리사이드층막이 많이 이용되는 것은 주지의 사실이다. 이러한 실리사이드막은 폴리실리콘막을 대체용으로 이용되며, 그중 텅스텐 실리사이드는 낮은 저항성, 열적 안정성, 다양한 화학액에 대한 높은 저항성을 갖는다.It is well known that the silicide layer film is widely used in many semiconductor devices in recent years. The silicide film is used as a substitute for the polysilicon film, and tungsten silicide has low resistance, thermal stability, and high resistance to various chemical liquids.

종래의 게이트는 게이트 절연막 상부에 폴리실리콘막, 텅스텐 실리사이드막이 적층된 폴리사이드 구조로 형성된다. 여기서, 텅스텐 실리사이드막은 하층의 폴리실리콘막의 배선 저항을 감소시킨다.The conventional gate is formed of a polyside structure in which a polysilicon film and a tungsten silicide film are stacked on a gate insulating film. Here, the tungsten silicide film reduces the wiring resistance of the underlying polysilicon film.

그러나, 상기와 같은 텅스텐 실리사이드-폴리사이드 게이트를 형성하게 되면, 다음과 같은 문제점이 발생된다.However, when the tungsten silicide-polyside gate is formed as described above, the following problems occur.

상기한 텅스텐 실리사이드-폴리사이드 게이트는, 게이트 형성후, 고온의 열공정을 거치게 된다. 이과정에서, 텅스텐 실리사이드막으로부터 불소 원자(F:텅스텐 실리사이드를 형성하는 반응원이 WF6임에 따라, 텅스텐 실리사이드막내에 F이 잔존됨)가 확산되어, 폴리실리콘막을 통과하여, 게이트 산화막으로 도달하게 된다. 이때, 게이트 산화막에 도달된 불소 원자(F)는 게이트 절연막(SiO2)내의 산소 원자 (O)와 치환되어, Si-O 결합을 파괴시킨다. 더불어, 불소 원자(F)와 치환된 산소 원자(O)는 반도체 기판과 게이트 절연막의 계면 또는 게이트 절연막과 폴리실리콘막과의 계면으로 확산되어, 실리콘 기판 및 폴리실리콘막을 일부 산화시키게 된다. 이로 인하여, 게이트 산화막의 두께가 증가되어, 즉, 게이트 절연막의 GOI(gate oxide integration)특성의 저하를 유발하게 되어, 반도체 소자의 신뢰성과 제조 수율에 치명적인 악영향을 미치게 된다.The tungsten silicide-polyside gate is subjected to a high temperature thermal process after the gate is formed. In this process, a fluorine atom (F is remaining in the tungsten silicide film as the reaction source forming F: tungsten silicide is WF 6 ) diffuses from the tungsten silicide film, passes through the polysilicon film, and reaches the gate oxide film. Done. At this time, the fluorine atom (F) that reaches the gate oxide film is replaced with the oxygen atom (O) in the gate insulating film (SiO 2 ) to break the Si-O bond. In addition, the fluorine atom F and the substituted oxygen atom O diffuse to the interface between the semiconductor substrate and the gate insulating film or the interface between the gate insulating film and the polysilicon film to partially oxidize the silicon substrate and the polysilicon film. As a result, the thickness of the gate oxide film is increased, that is, the gate oxide integration (GOI) property of the gate insulating film is deteriorated, which has a fatal adverse effect on the reliability and manufacturing yield of the semiconductor device.

이러한 종래 문제점을 해결하기 위하여, 종래의 개선된 방법으로, 미국 특허 5,364,803호(method of preventing fluorine-induced gate oxide degradation in WSixpolycide structure)에 개재된 바와 같이, 실리콘 기판 상부에 게이트 산화막, 폴리실리콘막, 불소 원자 확산 방지용 TiN막 및 텅스텐 실리사이드를 연속적으로 증착하고, 공지의 사진 식각 방법으로 원하는 폴리사이드 게이트를 형성한다. 그러나, 불소 원자 확산 방지용 TiN막은 원주(column)형 결정인 구조적인 특성 때문에 결정립계를 통하여 일부 불소 원자가 확산된다.In order to solve this conventional problem, as a conventional improved method, as described in US Patent 5,364,803 (method of preventing fluorine-induced gate oxide degradation in WSi x polycide structure), the gate oxide film, polysilicon on the silicon substrate A film, a TiN film for preventing fluorine atom diffusion, and tungsten silicide are successively deposited, and a desired polyside gate is formed by a known photolithography method. However, in the TiN film for preventing fluorine atom diffusion, some fluorine atoms are diffused through grain boundaries because of the structural characteristics of columnar crystals.

또한, 종래의 개선된 다른 방법으로, 미국 특허 5,441,904(Method for forming a two-layered polysilicon gate electrode in semiconductor device using grain boundaries)에 개재된 바와 같이, 실리콘 기판상에 게이트 산화막을 형성하고, 불소 확산을 방지하기 위하여, 결정립계가 상이한 두층의 폴리실리콘을 적층한 다음, 그 상부에 텅스텐 실리사이드막을 증착하는 기술이 제안되었다. 이 방법 또한, 폴리실리콘막의 결정립계의 차이로 불소 원자의 확산을 줄이기는 하였으나, 완전히 차단하지는 못하는 단점이 있다.In addition, another improved method of the prior art is to form a gate oxide film on a silicon substrate, as described in US Patent 5,441,904 (Method for forming a two-layered polysilicon gate electrode in semiconductor device using grain boundaries), In order to prevent this, a technique of stacking two layers of polysilicon having different grain boundaries and then depositing a tungsten silicide film thereon has been proposed. This method also reduces the diffusion of fluorine atoms due to differences in the grain boundaries of the polysilicon film, but does not completely block it.

또한, 종래의 또 다른 방법으로, 미국 특허 5,604,152호(CVD process for depositon of amorphous silicon)는 비정질 실리콘막을 SiH4의 분해에 의한 동종 반응으로 증착하는 방법이 제안된다. 즉, 상온에서 SiH4를 증착 장비내에 공급하고, 550℃로 가열된 오토클래브(autoclave) 장치에서 SiH4를 SiH2+H2로 분해시킨다. 이어, 550℃의 수평 저압 기상 증착 챔버에서 SiH2를 Si+H2로 분해시키어, 비정질 실리콘막을 형성한다. 이와같은 방법을 사용하기 위하여는, 기존의 장치에 오토 클래브 장치를 추가로 설치하여야 하는 불편함이 있으며, 오토 클래브 장치가 매우 사소한 고장을 일으킨 경우에도 증착된 비정질 실리콘막의 저항과 두께에 대한 균일도가 나빠지는 문제점이 있었다.In addition, as another conventional method, US Patent No. 5,604,152 (CVD process for depositon of amorphous silicon) is proposed to deposit an amorphous silicon film by homogeneous reaction by decomposition of SiH 4 . That is, the supply of SiH 4 at room temperature in a deposition equipment, and decomposing SiH 4 in the autoclave probe (autoclave) the device is heated to 550 ℃ as SiH 2 + H 2. Next, sikieo decomposition from the horizontal low-pressure vapor deposition chamber of 550 ℃ the SiH 2 to the Si + H 2, thereby forming an amorphous silicon film. In order to use this method, it is inconvenient to additionally install an autoclave device in an existing device, and even if the autoclave device causes a very slight failure, There was a problem that the uniformity worsened.

따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 텅스텐 실리사이드를 이용한 폴리사이드 구조의 게이트 구조에서, 텅스텐 실리사이드내의 불소 원자가 게이트 절연막으로 확산이 차단되어, 게이트 전극 및 게이트 절연막의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention is to solve the above-mentioned problems, in the gate structure of the polyside structure using tungsten silicide, the diffusion of fluorine atoms in the tungsten silicide is blocked by the gate insulating film, improving the reliability of the gate electrode and the gate insulating film It is an object of the present invention to provide a method for manufacturing a semiconductor device.

도 1a 내지 도 1e는 본 발명에 따른 텅스텐 실리사이드-폴리실리콘 게이트 구조에서 불소 원자 확산 방지방법을 설명하기 위한 도면.1A to 1E are views for explaining a method for preventing fluorine atom diffusion in a tungsten silicide-polysilicon gate structure according to the present invention.

(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

1 : 반도체 기판 2 : 게이트 절연막1 semiconductor substrate 2 gate insulating film

3 : 폴리실리콘막 4 : 비정질 실리콘막3: polysilicon film 4: amorphous silicon film

5 : 텅스텐 실리사이드막 6 : 난반사 방지막5: tungsten silicide film 6: antireflection film

10 : 게이트 전극10: gate electrode

상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 게이트 절연막이 형성된 반도체 기판 상부에 불순물이 도핑된 폴리실리콘막(Si+H2)을 형성하는 단계; 상기 폴리실리콘막이 형성된 결과물을 베이킹하는 단계로서, 상기 폴리실리콘막의 표면에는 공기중의 산소와 반응되어, 자연 산화막이 성장되어 있다.; 상기 베이킹 처리된 폴리실리콘막상에 HMDS(hexamethyldisilazane : (CH3)3Si-NH-Si(CH3)3)를 도포하는 단계로서, 상기 HMDS의 NH는 폴리실리콘막내부의 수소(H2)와 반응되어 기화되고, (CH3)3Si는 자연 산화막과 결합된다.; 상기 자연 산화막과 (CH3)3Si의 결합물을 성장 시드로 하여, 비정질 실리콘막을 형성하는 단계로서, 상기 비정질 실리콘막과 폴리실리콘막의 계면에는 (CH3)3Si의 메틸기(CH3)가 존재한다.; 상기 비정질 실리콘막 상에 텅스텐 실리사이드막을 형성하는 단계를 포함하며, 상기 메틸기(CH3)가 상기 텅스텐 실리사이드막 내의 원자가 확산되는 것을 포획하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention comprises the steps of forming a polysilicon film (Si + H 2 ) doped with impurities on the semiconductor substrate on which the gate insulating film is formed; Baking the resultant product in which the polysilicon film is formed, on which a natural oxide film is grown on the surface of the polysilicon film by reacting with oxygen in the air; Applying HMDS (hexamethyldisilazane: (CH 3 ) 3 Si-NH-Si (CH 3 ) 3 ) on the baked polysilicon film, wherein NH of the HMDS reacts with hydrogen (H 2 ) in the polysilicon film And vaporize, and (CH 3 ) 3 Si is combined with the native oxide film; Forming an amorphous silicon film by using the combination of the natural oxide film and (CH 3 ) 3 Si as a growth seed, wherein the methyl group (CH 3 ) of (CH 3 ) 3 Si is formed at the interface between the amorphous silicon film and the polysilicon film. exist.; And forming a tungsten silicide film on the amorphous silicon film, wherein the methyl group (CH 3 ) captures the diffusion of atoms in the tungsten silicide film.

본 발명에 의하면, 텅스텐 실리사이드막과 폴리실리콘막 사이에 불소 원자를 포획할 수 있는 메틸기(CH3)를 포함하는 비정질 실리콘을 형성하여, 불소 원자의 확산을 방지하게 된다.According to the present invention, amorphous silicon containing a methyl group (CH 3 ) capable of trapping fluorine atoms is formed between the tungsten silicide film and the polysilicon film to prevent diffusion of the fluorine atoms.

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도면 도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 게이트 전극 형성시 불소 원자의 확산을 방지방법을 설명하기 위한 단면도이다.1A to 1E are cross-sectional views illustrating a method of preventing diffusion of fluorine atoms when forming a gate electrode of a semiconductor device according to the present invention.

먼저, 도 1a를 참조하여, 반도체 기판(1) 상부에 게이트 절연막(2)을 공지의 방법으로 형성한다. 이어서, 게이트 절연막(2) 상부에 불순물이 도핑된 폴리실리콘막(3)을 SiH4의 열분해(pyrolysis: SiH4→SiH2+ H2, SiH2→Si(고체) + H2)에 의한 저압 화학 기상 증착법으로 형성한다. 즉, 표면에 흡착된 SiH4는 중간 화합물인 SiH2및 H2로 분해되고, 다시 SiH2는 고체인 Si와 H2로 분해되어, 폴리실리콘막(3)이 형성된다.First, referring to FIG. 1A, a gate insulating film 2 is formed on a semiconductor substrate 1 by a known method. Then, a gate insulating film (2) thermal decomposition of the upper doped polysilicon layer (3) impurity to SiH 4 (pyrolysis: SiH 4 → SiH 2 + H 2, SiH 2 → Si ( solid) + H 2) low pressure by It is formed by chemical vapor deposition. That is, the SiH 4 adsorbed on the surface is decomposed to an intermediate compound of SiH 2 and H 2, is again SiH 2 is broken down into solid Si and H 2, a polysilicon film 3 is formed.

그 다음으로, 도 1b에 도시된 바와 같이, 폴리실리콘막(3)이 형성된 반도체 기판 결과물(시편)은 진공 탈수 베이킹 공정(vacuum dehydration baking process)이 진행된다. 여기서, 진공 탈수 베이킹 공정을 실시하는 것은 다음과 같다. 불순물이 도핑된 폴리실리콘막(3)에 표면에는 도핑후 부산물인 P2O5가 발생된다. 따라서, 폴리실리콘막(3)의 전도 특성을 개선하기 위하여는 이를 선택적으로 제거하여야 하므로, 습식 식각 공정을 실시하여 주어야 한다. 그러나, 일반적으로 IBM의 로버트 루소(Robert Lussow)가 발표한 바와 같이, P2O5와 같은 산화막 계열의 물질들은 습식 식각을 진행한 후 표면에 물 분자를 포함하게 되어, 이후 공정에 지장을 주게 된다. 따라서, 상기한 물분자를 제거하여, 안정한 실라놀(silanol) 상태를 구축하기 위하여는, 100℃ 이상의 가열을 병행하는 진공 탈수 베이킹 공정을 실시하여야 한다.Subsequently, as shown in FIG. 1B, the semiconductor substrate product (test piece) on which the polysilicon film 3 is formed is subjected to a vacuum dehydration baking process. Here, performing a vacuum dehydration baking process is as follows. On the surface of the polysilicon film 3 doped with impurities, a by-product P 2 O 5 is generated after the doping. Therefore, in order to improve the conductive properties of the polysilicon film 3, it must be selectively removed, and a wet etching process must be performed. In general, however, as IBM's Robert Lussow has published, oxide-based materials such as P 2 O 5 contain water molecules on the surface after wet etching, which can interfere with subsequent processes. do. Therefore, in order to remove the above water molecules and form a stable silanol state, a vacuum dehydration baking process with heating at 100 ° C. or higher must be performed.

그후, 상기와 같은 공정이 진행된 폴리실리콘막(3) 표면에는 공기중의 산소와 폴리실리콘내의 실리콘 원자가 반응하여, 약 5 내지 20Å 정도의 자연 산화막(도시되지 않음)이 성장된다. 이어서, 폴리실리콘막(3) 표면에 HMDS(hexa- methyldisilazane: (CH3)3Si-NH-Si(CH3)3)를 도포한다. 그러면, 폴리실리콘막(Si+H2:3)내의 H2와 HMDS의 NH가 결합되어, NH3를 이루어, HMDS에서 분리(기화)된다. 그리고, NH3를 제외한 HMDS 분자 즉, (CH3)3Si-기가 폴리실리콘막(3) 상의 자연 산화막(Si-O)과 반응하여, HMDS의 단층(monolayer)을 형성한다. 즉, 4가의 실리콘 원자는, 4개의 결합손중 3개는 산소 원자와 결합되고, 나머지 1개는 Si(CH3)3과 결합된다. 도면에서 R은 Si(CH3)3을 나타낸다.Thereafter, oxygen in the air and silicon atoms in the polysilicon react with the surface of the polysilicon film 3 subjected to the above-described process, and a natural oxide film (not shown) of about 5 to 20 kPa is grown. Subsequently, HMDS (hexamethyldisilazane: (CH 3 ) 3 Si-NH-Si (CH 3 ) 3 ) is coated on the surface of the polysilicon film 3. Then, the polysilicon film: NH is the combination of HMDS and H 2 in the (Si + H 2 3), made of the NH 3, are separated (evaporated) from the HMDS. Then, HMDS molecules other than NH 3, that is, (CH 3 ) 3 Si-groups react with the native oxide film (Si-O) on the polysilicon film 3 to form a monolayer of HMDS. That is, in the tetravalent silicon atom, three of the four bonds are bonded to an oxygen atom, and the other one is bonded to Si (CH 3 ) 3 . In the figures, R represents Si (CH 3 ) 3 .

그리고나서, 도 1c에 도시된 바와 같이, 상기 HMDS의 단층을 성장 시드(seed)로 하고, SiH4또는 SiCl2H2가스를 이용하여, 약 400 내지 550℃, 약 200 내지 400mTorr의 조건에서 약 50 내지 500Å의 두께를 갖는 비정질 실리콘막(4)을 형성한다. 이때, 상기와 같은 공정 중, HMDS 성분중의 하나인 메틸기(CH3)가 비정질 실리콘막(4)과 폴리실리콘막(3)의 계면에 잔류하게 되는데, 이 메틸기는, 비정질 실리콘막(4)과 함께 이후에 형성될 텅스텐 실리사이드로 부터 확산된 불소 원자를 차단하는 역할을 한다. 즉, 상기 메틸기가 이후에 형성되는 텅스텐 실리사이드로부터 확산되는 불소를 포획하는 것이다. 이를 보다 자세히 설명하면, 비정질 실리콘막(4)과 폴리실리콘막(3)의 계면에 잔류하는 메틸기는 텅스텐 실리사이드막 형성시 발생되는 불소 원자를 포획하여, CH2F,CHF2의 화합물을 형성하게 된다. 이때, CH2F, CHF2와 같은 탄소 화합물은 실리콘과 동일한 4가의 원자이므로, 비정질 실리콘막(4)과 폴리실리콘막(3) 사이에서 전기적인 문제를 일으키지 않는다. 한편, 비정질 실리콘층(4)은 텅스텐 실리사이드와 폴리실리콘막(3) 사이의 접착 특성을 개선하고, 비정질 실리콘층(4)과 폴리실리콘막(3)의 계면이 상이하므로, 불소 원자의 확산이 한층 더 저지하는 역할을 한다.Then, as shown in Figure 1c, the monolayer of the HMDS as a growth seed, using SiH 4 or SiCl 2 H 2 gas, about 400 to 550 ℃, about 200 to 400 mTorr at about An amorphous silicon film 4 having a thickness of 50 to 500 GPa is formed. At this time, in the above process, methyl group (CH 3 ), which is one of the HMDS components, remains at the interface between the amorphous silicon film 4 and the polysilicon film 3, and the methyl group is the amorphous silicon film 4. Together with the fluorine atom diffused from the tungsten silicide to be formed later. That is, the methyl group traps fluorine diffused from the tungsten silicide formed later. In more detail, the methyl group remaining at the interface between the amorphous silicon film 4 and the polysilicon film 3 traps fluorine atoms generated when the tungsten silicide film is formed, thereby forming a compound of CH 2 F, CHF 2 . do. At this time, carbon compounds such as CH 2 F and CHF 2 are the same tetravalent atoms as silicon, and thus do not cause electrical problems between the amorphous silicon film 4 and the polysilicon film 3. On the other hand, the amorphous silicon layer 4 improves the adhesion property between the tungsten silicide and the polysilicon film 3, and the interface between the amorphous silicon layer 4 and the polysilicon film 3 is different, whereby diffusion of fluorine atoms is prevented. It plays a further role in deterrence.

그 다음으로, 도 1d에 도시된 바와 같이, 비정질 실리콘막(4) 상부에 텅스텐 실리사이드막(5)을 하부 비정질 실리콘막 및 폴리실리콘막의 두께를 고려하여, 약 1200 내지 2000Å 두께로 형성한다. 이러한 두께의 텅스텐 실리사이드막(5)을 형성하기 위하여는, 약 390 내지 440℃의 온도와 0.5 내지 1.0 Torr의 압력에서 약 400 SCCM의 SiH4과 약 4.5 SCCM의 WF6의 공정 조건으로 진행한다. 이어서, 텅스텐 실리사이드막(5) 상부에는 이후에 진행될 사진 식각 공정시, 난반사를 방지하기 위하여, 난반사 방지용 산화 질화막(6)을 형성한다. 이 산화 질화막(6)은 350 내지 450℃의 온도와, 1 내지 2 Torr의 압력에서, 200 SCCM의 SiH4과, 1200 SCCM의 N2O와, 2000 SCCM의 NH3와, 3000 SCCM의 N2가스에 의하여 형성된다.Next, as shown in FIG. 1D, a tungsten silicide film 5 is formed on the amorphous silicon film 4 to a thickness of about 1200 to 2000 micrometers in consideration of the thicknesses of the lower amorphous silicon film and the polysilicon film. In order to form the tungsten silicide film 5 having such a thickness, it proceeds to the processing conditions of SiH 4 of about 400 SCCM and WF 6 of about 4.5 SCCM at a temperature of about 390 to 440 ° C. and a pressure of 0.5 to 1.0 Torr. Subsequently, an oxynitride film 6 for preventing diffuse reflection is formed on the tungsten silicide layer 5 in order to prevent diffuse reflection during the subsequent photolithography process. The oxynitride film 6 has a temperature of 350 to 450 ° C., a pressure of 1 to 2 Torr, SiH 4 of 200 SCCM, N 2 O of 1200 SCCM, NH 3 of 2000 SCCM, and N 2 of 3000 SCCM. Formed by gas.

그 후, 도 1e에 나타낸 바와 같이, 상기 산화 질화막(6)과, 텅스텐 실리사이드막(5), 비정질 실리콘막(4), 폴리실리콘막(3) 및 게이트 산화막(2)을 소정 부분 식각하여, 게이트 전극(10)을 형성한다.Thereafter, as shown in FIG. 1E, the oxynitride film 6, the tungsten silicide film 5, the amorphous silicon film 4, the polysilicon film 3, and the gate oxide film 2 are etched by a predetermined portion. The gate electrode 10 is formed.

이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 텅스텐 실리사이드막과 폴리실리콘막 사이에 텅스텐 실리사이드를 형성하는 공정시 발생, 확산되는 불소 원자를 포획할 수 있는 메틸기(CH3)를 포함하는 비정질 실리콘을 형성하여, 불소 원자의 확산을 방지하게 된다.As described in detail above, according to the present invention, amorphous silicon including a methyl group (CH 3 ) that can capture a fluorine atom that is generated and diffused during the process of forming tungsten silicide between the tungsten silicide film and the polysilicon film is formed. To prevent the diffusion of fluorine atoms.

따라서, 게이트 전극 및 게이트 절연막의 신뢰성이 개선된다.Thus, the reliability of the gate electrode and the gate insulating film is improved.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (8)

게이트 절연막이 형성된 반도체 기판 상부에 불순물이 도핑된 폴리실리콘막(Si+H2)을 형성하는 단계;Forming a polysilicon film (Si + H 2 ) doped with impurities on the semiconductor substrate on which the gate insulating film is formed; 상기 폴리실리콘막이 형성된 결과물을 베이킹하는 단계로서, 상기 폴리실리콘막의 표면에는 공기중의 산소와 반응되어, 자연 산화막이 성장되어 있다.;Baking the resultant product in which the polysilicon film is formed, on which a natural oxide film is grown on the surface of the polysilicon film by reaction with oxygen in air; 상기 베이킹 처리된 폴리실리콘막상에 HMDS(hexamethyldisilazane : (CH3)3Si-NH-Si(CH3)3)를 도포하는 단계로서, 상기 HMDS의 NH는 폴리실리콘막내부의 수소(H2)와 반응되어 기화되고, (CH3)3Si는 자연 산화막과 결합된다. ;Applying HMDS (hexamethyldisilazane: (CH 3 ) 3 Si-NH-Si (CH 3 ) 3 ) on the baked polysilicon film, wherein NH of the HMDS reacts with hydrogen (H 2 ) in the polysilicon film And vaporize, and (CH 3 ) 3 Si is combined with the native oxide film. ; 상기 자연 산화막과 (CH3)3Si의 결합물을 성장 시드로 하여, 비정질 실리콘막을 형성하는 단계로서, 상기 비정질 실리콘막과 폴리실리콘막의 계면에는 상기 (CH3)3Si의 메틸기(CH3)가 존재한다.;A step of forming an amorphous silicon film using a combination of the natural oxide film and (CH 3 ) 3 Si as a growth seed, wherein the (CH 3 ) 3 Si methyl group (CH 3 ) is formed at the interface between the amorphous silicon film and the polysilicon film. Is present; 상기 비정질 실리콘막 상에 텅스텐 실리사이드막을 형성하는 단계를 포함하며, 상기 메틸기(CH3)가 상기 텅스텐 실리사이드막 내의 원자가 확산되는 것을 포획하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming a tungsten silicide film on the amorphous silicon film, wherein the methyl group (CH 3 ) captures diffusion of atoms in the tungsten silicide film. 제 1 항에 있어서, 상기 폴리실리콘막은 SiH4의 열분해에 의하여 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the polysilicon film is formed by thermal decomposition of SiH 4 . 제 1 항에 있어서, 상기 비정질 실리콘막은 400 내지 550℃의 온도와 200 내지 400 mTorr의 조건에서 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the amorphous silicon film is formed at a temperature of 400 to 550 ° C. and a condition of 200 to 400 mTorr. 제 1 항 또는 제 3 항에 있어서, 상기 비정질 실리콘막은 SiH4또는 SiCl2H2가스의 반응으로 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the amorphous silicon film is formed by reaction of SiH 4 or SiCl 2 H 2 gas. 제 4 항에 있어서, 상기 비정질 실리콘막의 두께는 50 내지 500Å 인 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 4, wherein the amorphous silicon film has a thickness of 50 to 500 GPa. 제 1 항에 있어서, 상기 텅스텐 실리사이드막은, 390 내지 440℃의 온도와 0.5 내지 1.0 Torr의 압력에서, 약 400 SCCM의 SiH4가스와 약 4.5 SCCM의 WF6가스의 반응으로 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the tungsten silicide film is formed by the reaction of SiH 4 gas of about 400 SCCM and WF 6 gas of about 4.5 SCCM at a temperature of 390 to 440 ° C and a pressure of 0.5 to 1.0 Torr. Method of manufacturing a semiconductor device. 제 6 항에 있어서, 상기 텅스텐 실리사이드막은 1200 내지 2000Å 두께를 갖는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 6, wherein the tungsten silicide layer has a thickness of 1200 to 2000 GPa. 제 1 항에 있어서, 상기 텅스텐 실리사이드막을 형성하는 단계 이후에, 상기 텅스텐 실리사이드막 상에 난반사 방지막을 형성하는 단계; 상기 난반사 방지막, 텅스텐 실리사이드막, 비정질 실리콘막, 폴리실리콘막 및 게이트 산화막을 패터닝하여, 게이트 전극을 형성하는 단계를 부가적으로 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, further comprising, after the forming of the tungsten silicide film, forming an anti-reflection film on the tungsten silicide film; And patterning the diffuse reflection prevention film, the tungsten silicide film, the amorphous silicon film, the polysilicon film, and the gate oxide film to form a gate electrode.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100737406B1 (en) 2006-05-22 2007-07-09 한국표준과학연구원 Preventing method against moisture penetration into a gate electrode

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