KR100254175B1 - Method of forming tungsten plug in semiconductor device - Google Patents

Method of forming tungsten plug in semiconductor device Download PDF

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KR100254175B1
KR100254175B1 KR1019970030026A KR19970030026A KR100254175B1 KR 100254175 B1 KR100254175 B1 KR 100254175B1 KR 1019970030026 A KR1019970030026 A KR 1019970030026A KR 19970030026 A KR19970030026 A KR 19970030026A KR 100254175 B1 KR100254175 B1 KR 100254175B1
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tungsten
plug
etching
metal layer
dimple
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KR1019970030026A
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KR19990005808A (en
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김종일
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a tungsten plug of a semiconductor device is provided to prevent generation of over-etching in etching a tungsten layer by filling a dimple of the tungsten layer with a photoresist film. CONSTITUTION: After an oxide film(30) and a metal layer(80) are sequentially deposited on a semiconductor substrate(20), lower wiring lines are formed in rectangular shape by a masking etching process and an insulating film(40) is deposited at the outside of the lower wiring lines. When a tungsten metal layer(60) is deposited at surface of the insulating film(40) and via hole, a dimple(62) depressed by a predetermined depth is formed at surface of the via hole. A photoresist film(70) is formed to fill the dimple(62). By removing the photoresist film(70) through a plasma dry etching method, the photoresist film(70) is filled at the dimple(62) and thus, the height of the tungsten metal layer(60) becomes constant. At this state, only a plug remains within the via hole by etching the tungsten metal layer(60) until a barrier layer(50) is exposed.

Description

반도체장치의 텅스텐플러그 형성방법Tungsten Plug Formation Method of Semiconductor Device

본 발명은 텅스텐 플러그를 형성하는 방법에 관한 것으로, 특히, 텅스텐금속층을 식각에 의하여 플러그를 형성하는 공정에서 과소 식각으로 인하여 텅스텐잔류물이 장벽층에 잔류하게 되거나 과대 식각에 의하여 텅스텐플러그에 딤플이 커지게 되어 전기적 특성이 저하되는 것을 방지하기 위하여 텅스텐층의 딤플에 감광막을 충진하여 텅스텐층 식각시에 과도식각이 발생되는 것을 방지하므로 소자의 전기적 특성을 향상시키도록 하는 반도체장치의 텅스텐플러그 형성방법에 관한 것이다.The present invention relates to a method for forming a tungsten plug, and in particular, in the process of forming a plug by etching a tungsten metal layer, tungsten residues remain in the barrier layer due to underetching or dimples are formed in the tungsten plug due to overetching. Method of forming a tungsten plug in a semiconductor device to improve the electrical characteristics of the device by filling the photoresist film in the dimple of the tungsten layer to prevent the excessive etching during the tungsten layer etching to prevent the electrical characteristics are reduced to become large It is about.

일반적으로, 반도체장치의 종류에는 여러 가지가 있고, 이 반도체장치 내에 형성되는 트랜지스터 및 커패시터등을 구성시키는 방법에는 다양한 제조기술이 사용되고 있으며, 최근에는 반도체기판 상에 산화막을 입혀 전계효과를 내도록 하는 모스형 전계효과트랜지스터(MOSFET; metal oxide semiconductor field effect transistor)와, 실리콘기판에 비하여 전자의 이동 속도가 6배나 큰 갈륨아세나이드(GaAs)를 기판으로 사용하여 전계효과를 내는 메스형 전계효과트랜지스터(MESFET; metal semiconductor field effect transistor)와, 그 이외에 절연 게이트형 전계효과 트랜지스터(IGEFT; insulator gate field effect transistor) 등의 다양한 방식의 반도체장치가 사용되고 있다.In general, there are many kinds of semiconductor devices, and various manufacturing techniques are used to configure transistors, capacitors, and the like formed in the semiconductor device. In recent years, MOS is formed by applying an oxide film on a semiconductor substrate to produce an electric field effect. A metal field semiconductor transistor (MOSFET) and a gallium arsenide (GaAs) that have six times the electron transfer speed than a silicon substrate are used as a substrate, and a mes-type field effect transistor (MESFET) produces a field effect. semiconductor devices of various types such as metal semiconductor field effect transistors and insulator gate field effect transistors (IGEFTs).

이와 같이, 반도체장치에는 배선라인과 배선라인을 서로 연결하기 위하여 텅스텐층을 증착한 후에 식각하여서 상부배선라인과 하부배선라인을 서로 연결시키는 텅스텐 플러그(Plug)를 형성시켜서 사용하게 되는 것으로, 이 플러그를 식각하는 경우에는 과소식각을 하는 경우에는 텅스텐 잔류물이 장벽층 상부에 남겨지게 되므로 이웃에 있는 다른 배선라인과 연결되어 전류가 누설되거나 쇼트가 발생되는 경우가 있으며, 이와 반대로 과대 식각을 수행하는 경우에는 플러그의 상부에 함몰되어 있는 딤플(Dimple)의 깊이가 깊어지게 되어 플러그의 상부에 연결되는 상부 배선라인 간에 단락이 발생되는 등의 경우가 발생되었다.In this way, in the semiconductor device, a tungsten layer is deposited and then etched to form a tungsten plug which connects the upper wiring line and the lower wiring line to each other in order to connect the wiring line and the wiring line. In the case of etching, the tungsten residue is left over the barrier layer when the etching is over-etched, so it may be connected to other wiring lines in the neighborhood, causing current leakage or short-circuit. In this case, the depth of the dimple recessed in the upper portion of the plug becomes deep, and a short circuit occurs between the upper wiring lines connected to the upper portion of the plug.

도 1 및 도 2 는 종래의 반도체장치에서 텅스텐 플러그를 형성하는 공정을 개략적으로 예시한 도면으로서, 반도체기판(1) 상에 산화막(3)을 도포하고 그 위에 금속층(Al)을 적층하고서 마스킹 식각공정을 통하여 하부배선라인(9)을 일정 간격으로 사각 단면 형상으로 형성하고서 그 외측으로 절연막(5)을 적층시키도록 한다.1 and 2 schematically illustrate a process of forming a tungsten plug in a conventional semiconductor device, in which an oxide film 3 is coated on a semiconductor substrate 1, and a metal layer Al is laminated thereon, thereby masking etching. Through the process, the lower wiring line 9 is formed in a square cross-sectional shape at regular intervals, and the insulating film 5 is stacked outside thereof.

그리고, 상기 절연막(5)의 상부면과 그 절연막(5) 사이에 형성된 비아홀(Via Hole)에 텅스텐이 층상으로 형성된 금속층(7)을 적층하게 되면 텅스텐이 비아홀에 주입되면서 그 상부면에 바람직하지 않은 하부로 일정깊이 함몰된 요홈부(8)가 형성되어 진다.In addition, when the tungsten layered metal layer 7 is laminated in the via hole formed between the upper surface of the insulating film 5 and the insulating film 5, the tungsten is injected into the via hole, which is not preferable. The recessed part 8 which is recessed to a predetermined depth to the lower part is formed.

한편 도 2에 도시된 바와 같이, 텅스턴금속층(7)을 식각공정을 통하여 식각하게 되면, 식각물질이 식각을 하면서 플러그(11)를 형성하게 되고, 이 플러그(11)의 상부에는 식각으로 인한 딤플(10)이 형성되어지게 되고, 이 플러그(11)의 상부면에 상부배선라인(미도시)이 마스킹 시각공정으로 통하여 형성되어 플러그(11)에 의하여 하부배선라인(9)과 연결되어지는 것이다.Meanwhile, as shown in FIG. 2, when the tungsten metal layer 7 is etched through an etching process, an etching material is etched to form a plug 11, and an upper portion of the plug 11 is formed by etching. The dimple 10 is formed, and an upper wiring line (not shown) is formed on the upper surface of the plug 11 through a masking visual process to be connected to the lower wiring line 9 by the plug 11. will be.

그런데, 종래에는 상기한 플러그(11)를 형성하기 위하여 식각을 할 때 과소하게 식각이 이루어지게 되면, 텅스텐 잔류물이 장벽층(6)상에 남겨지게 되어 쇼트 혹은 전기 누설을 발생시키는 문제가 있으며, 만약 과대 식각이 발생되는 경우에는 플러그(11)의 딤플(10)이 크게 형성되어 상부에 접촉되는 상부배선라인과 접촉면적이 적음으로 인한 접촉 저항이 커지게 되어 동작 특성이 저하되는 문제점등이 있었다.However, in the related art, when the etching is excessively performed during the etching to form the plug 11, the tungsten residue is left on the barrier layer 6, causing short or electrical leakage. If excessive etching occurs, the dimple 10 of the plug 11 is formed large, and the contact resistance is increased due to the small contact area and the upper wiring line contacting the upper part. there was.

한편, 상기한 문제를 해결하기 위하여 텅스텐을 식각한 후에 플러그의 상부면을 평탄화시키기 위하여 화학 기계적 연마(Chemical Mechanical Polishing)를 적용하는 경우도 있으나, 이 방식의 경우에는 장비가 고가이고, 작업시간이 이중으로 들게 되어 생산성이 저하되는 등의 단점이 있었다.In order to solve the above problem, chemical mechanical polishing may be applied to planarize the upper surface of the plug after etching tungsten, but in this case, the equipment is expensive and the working time is long. There are disadvantages such as lifting productivity due to the double.

본 발명은 이러한 점을 감안하여 안 출한 것으로서, 텅스텐금속층을 식각에 의하여 플러그를 형성하는 공정에서 과소 식각으로 인하여 텅스텐 잔류물이 장벽층에 잔류하게 되거나 과대 식각에 의하여 텅스텐 플러그에 딤플이 커지게 되어 전기적 특성이 저하되는 것을 방지하기 위하여 텅스텐층의 딤플에 감광막을 충진하여 텅스텐층 식각시에 과도식각이 발생되는 것을 방지하므로 소자의 전기적 특성을 향상시키도록 하는 것이 목적이다.The present invention has been made in view of this point, in the process of forming the plug by etching the tungsten metal layer, the tungsten residue is left in the barrier layer due to underetching, or the dimple becomes large in the tungsten plug due to overetching The purpose of the present invention is to improve the electrical characteristics of the device since the photoresist is filled in the dimples of the tungsten layer to prevent the excessive etching during the tungsten layer etching.

도 1 및 도 2는 종래의 반도체장치에서 텅스텐 플러그를 형성하는 공정을 개략적으로 예시한 도면이고,1 and 2 are diagrams schematically illustrating a process of forming a tungsten plug in a conventional semiconductor device,

도 3 내지 도 5는 본 발명에 따른 반도체장치에서 텅스텐에서 감광막을 이용하여 딤플을 제거한 상태로 플러그를 형성하는 상태를 예시한 도면이다.3 to 5 illustrate a state in which a plug is formed with a dimple removed using a photosensitive film in tungsten in the semiconductor device according to the present invention.

-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing

20 : 반도체기판 30 : 산화막20 semiconductor substrate 30 oxide film

40 : 절연막 50 : 장벽층40: insulating film 50: barrier layer

60 : 텅스텐 금속층 62 : 딤플60: tungsten metal layer 62: dimple

70 : 감광막 80 : 금속층70 photosensitive film 80 metal layer

이러한 목적은 반도체장치에서 텅스텐 금속층을 식각하여서 플러그를 형성하는 방법에 있어서, 장벽층의 상부와 비아홀내에 텅스텐으로 된 금속층을 증착하고, 이 금속층의 상부에 감광막을 도포하여 금속층의 상부에 형성된 딤플에 감광막을 충진하는 단계와, 상기 단계 후에 상기 감광막과 금속층을 식각공정에 의하여 동시에 제거하여 비아홀내에 플러그만을 남겨 놓는 단계와, 상기 단계 후에 플러그의 상부면에서 미처 제거되지 않은 감광막의 잔류물을 제거하는 단계로 이루어진 것을 특징으로 반도체장치의 텅스텐플러그 형성방법을 제공함으로써 달성된다.The purpose is to form a plug by etching a tungsten metal layer in a semiconductor device, by depositing a tungsten metal layer in the upper part of the barrier layer and the via hole, and applying a photoresist film on the upper part of the metal layer to a dimple formed on the upper part of the metal layer. Filling the photoresist film, and simultaneously removing the photoresist film and the metal layer by an etching process, leaving only the plug in the via hole, and removing the residues of the photoresist film that have not been removed from the upper surface of the plug after the step. It is achieved by providing a method for forming a tungsten plug of a semiconductor device, characterized in that the step.

그리고, 상기 텅스텐은 화학기상 증착법(CVD)에 의하여 형성되며, 상기 텅스텐 금속막과 감광막은 아르곤(Ar)가스에 설퍼릭 헥사플루오라이드(SF6)가스가 일정비율로 함유한 가스 혹은 설퍼릭 헥사플루오라이드 가스에 클로라인(Cl2)가스가 일정비율로 함유한 가스를 이용하여 플라즈마 건식식각에 의하여 이루어진다.In addition, the tungsten is formed by chemical vapor deposition (CVD), and the tungsten metal film and the photosensitive film are gas or sulfur hexa containing argon (Ar) gas and sulfur hexafluoride (SF 6 ) gas at a predetermined ratio. The fluoride gas is formed by plasma dry etching using a gas containing chlorine (Cl 2 ) gas at a predetermined ratio.

이하, 첨부한 도면에 의거하여 본 발명에 따른 텅스텐플러그 형성방법에 대하여 상세히 설명한다.Hereinafter, a tungsten plug forming method according to the present invention will be described in detail with reference to the accompanying drawings.

도 3에 도시된 바와 같이, 반도체기판(20) 상에 산화막(30)을 도포하고 그 위에 금속층(80)을 적층하고서 마스킹 식각공정을 통하여 하부배선라인을 일정 간격으로 사각 단면 형상으로 형성하고서 그 외측으로 절연막(40)을 적층시키도록 한다.As shown in FIG. 3, the oxide layer 30 is coated on the semiconductor substrate 20, the metal layer 80 is stacked thereon, and the lower wiring lines are formed in a rectangular cross-sectional shape at regular intervals through a masking etching process. The insulating film 40 is laminated on the outside.

그리고, 상기 절연막(40)의 상부면과 그 절연막(40) 사이에 형성된 비아홀(Via Hole)에 텅스텐이 층상으로 형성된 텅스텐 금속층(60)을 적층하게 되면 텅스텐이 비아홀에 주입되면서 그 상부면에 바람직하지 않은 하부로 일정깊이 함몰된 딤플(62)이 형성되어 지게 되며, 그 위로 딤플(62)을 충진시킬 수 있는 감광막(70)을 일정 두께로 형성시키도록 한다.In addition, when the tungsten metal layer 60 in which tungsten is formed in a layer is stacked in the via hole formed between the upper surface of the insulating film 40 and the insulating film 40, the tungsten is injected into the via hole, which is preferable to the upper surface of the insulating film 40. A dimple 62 recessed to a predetermined depth is formed at a lower portion thereof, and a photoresist film 70 capable of filling the dimple 62 is formed to have a predetermined thickness.

이와 같이, 도 4에 도시된 바와 같이, 상기 감광막(70)과 금속층(60)을 아르곤(Ar)가스에 설퍼릭 헥사플루오라이드(SF6)가스가 일정비율로 함유된 가스 혹은 설퍼릭 헥사플루오라이드 가스에 클로라인(Cl2)가스가 일정비율로 함유된 가스를 이용하여 플라즈마 건식식각 방법에 의하여 감광막(70)을 제거하여서 텅스텐 금속층(60)의 딤플(62)에 감광막(70)이 충진되고 텅스텐 금속층(60)의 높이가 일정하게 된다.As such, as shown in FIG. 4, the photoresist 70 and the metal layer 60 are composed of argon (Ar) gas in a ratio of sulfur hexafluoride (SF 6 ) gas or sulfur hexafluorine. The photosensitive film 70 is filled in the dimple 62 of the tungsten metal layer 60 by removing the photosensitive film 70 by a plasma dry etching method using a gas containing a constant ratio of chlorine (Cl 2 ) gas in the ride gas. As a result, the height of the tungsten metal layer 60 becomes constant.

이러한 상태에서 도 5에 도시된 바와 같이, 딤플(62)이 감광막(70)으로 매립되어 있는 텅스텐 금속층(60)을 장벽층(50)이 노출될 때까지 계속하여 식각하여 제거하면 비아홀 내에 플러그(90)만이 수평 상태로 남겨지게 되는 상태가 되는 것으로서, 이때, 텅스텐 금속층(60)과 딤플(62)에 매립되어 있는 감광막(70)의 식각 선택비는 거의 1:1로 동일하므로 플러그(90)의 상부면이 거의 수평 상태로 균일하게 식각 되어진다.In this state, as shown in FIG. 5, when the tungsten metal layer 60 in which the dimple 62 is embedded with the photoresist layer 70 is continuously etched and removed until the barrier layer 50 is exposed, the plug in the via hole is removed. Only 90 is to be left in a horizontal state. At this time, since the etching selectivity of the photosensitive film 70 embedded in the tungsten metal layer 60 and the dimple 62 is almost equal to 1: 1, the plug 90 The upper surface of is etched uniformly in almost horizontal state.

그리고, 상기 단계 후에 플러그(90)의 상부면에서 미처 제거되지 않은 감광막(70)의 잔류물을 제거하기 위하여 플러그(90)의 상부면을 씻어내도록 하며, 그 이후에는 통상적으로 이용되는 차후의 공정을 진행하도록 한다.After the step, the upper surface of the plug 90 is washed to remove residues of the photoresist film 70 which have not been removed from the upper surface of the plug 90, and then a subsequent process which is commonly used. Let's proceed.

따라서, 상기한 바와 같이 본 발명에 따른 텅스텐플러그 형성방법을 이용하게 되면, 텅스텐금속층을 식각에 의하여 플러그를 형성하는 공정에서 과소 식각으로 인하여 텅스텐 잔류물이 장벽층에 잔류하게 되거나 과대 식각에 의하여 텅스텐 플러그에 딤플이 커지게 되어 전기적 특성이 저하되는 것을 방지하기 위하여 텅스텐층의 딤플에 감광막을 충진하여 텅스텐층 식각시에 과도식각이 발생되는 것을 방지하므로 소자의 전기적 특성을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.Therefore, when the tungsten plug forming method according to the present invention is used as described above, the tungsten residue remains in the barrier layer due to underetching in the process of forming the plug of the tungsten metal layer by etching, or the tungsten by excessive etching It is very useful to improve the electrical characteristics of the device by filling the photoresist film in the dimples of the tungsten layer to prevent excessive etching during the tungsten layer etching in order to prevent the electrical characteristics from deteriorating due to the large dimples in the plug. It is an effective invention.

또한, 텅스텐 금속막 식각 이후에 확실한 평탄화를 위하여 화학 기계적 연마 방법(CMP)을 사용하더라도 딤플이 발생될 염려가 없으므로 과도 식각을 이용할 수 있고 그로 인하여 장벽층 상에 존재하는 텅스텐 잔류물이 별로 없으므로 잔류물을 제거하는 시간을 줄일 수 있어서 공정 상에서 작업성을 향상시키는 장점을 지니게 된다.In addition, even if the chemical mechanical polishing method (CMP) is used to ensure the planarization after the tungsten metal film etching, there is no fear of dimples, so over-etching can be used, and as a result, few tungsten residues on the barrier layer remain. The time to remove water has the advantage of improving workability in the process.

Claims (1)

반도체장치의 턴스텐플러그 제조 방법에 있어서,In the method for manufacturing a turn stung plug of a semiconductor device, 하부구조물이 생성된 반도체기판의 층간 절연막의 비아홀에 장벽층을 증착하는 단계;Depositing a barrier layer in a via hole of an interlayer insulating layer of a semiconductor substrate on which a substructure is formed; 상기 비아홀내에 매립되도록 털스텐으로 된 금속층을 증착하고, 이 금속층의 상부에 감광막을 도포하여 금속층의 상부에 형성된 딤플에 감광막을 충진하는 단계;Depositing a metal layer made of tulle to be embedded in the via hole, and applying a photoresist film to the upper portion of the metal layer to fill the dimple formed in the upper portion of the metal layer; 상기 감광막과 금속응을 동시에 식각하되, Ar가스에 SF6가스를 일정비율로 함유한 가스의 플라즈마 건식식각을 이용하여 상기 비아홀내에 장벽층 및 금속층의 플러그만을 남겨 놓는 단계; 및Simultaneously etching the photoresist and the metallization, leaving only a plug of the barrier layer and the metal layer in the via hole by using plasma dry etching of a gas containing SF 6 gas in a predetermined ratio in Ar gas; And 상기 플러그의 상부면에 미처 제거되지 않은 감광막의 잔류물을 제거하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체장치의 텅스턴플러그 형성방법.And removing residues of the photoresist film which have not been removed from the upper surface of the plug.
KR1019970030026A 1997-06-30 1997-06-30 Method of forming tungsten plug in semiconductor device KR100254175B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100698742B1 (en) * 2005-10-24 2007-03-23 동부일렉트로닉스 주식회사 Fabricating method of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05299397A (en) * 1992-04-21 1993-11-12 Sony Corp Forming method for metal plug
JPH05347270A (en) * 1992-04-14 1993-12-27 Sony Corp Metal plug forming method and wafrr treating device thereby

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05347270A (en) * 1992-04-14 1993-12-27 Sony Corp Metal plug forming method and wafrr treating device thereby
JPH05299397A (en) * 1992-04-21 1993-11-12 Sony Corp Forming method for metal plug

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100698742B1 (en) * 2005-10-24 2007-03-23 동부일렉트로닉스 주식회사 Fabricating method of semiconductor device

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