KR100230349B1 - Forming method of metal contact - Google Patents

Forming method of metal contact Download PDF

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KR100230349B1
KR100230349B1 KR1019920005406A KR920005406A KR100230349B1 KR 100230349 B1 KR100230349 B1 KR 100230349B1 KR 1019920005406 A KR1019920005406 A KR 1019920005406A KR 920005406 A KR920005406 A KR 920005406A KR 100230349 B1 KR100230349 B1 KR 100230349B1
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forming
layer
insulating film
etch stop
contact
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KR1019920005406A
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KR930020583A (en
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장택용
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윤종용
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 셀프얼라인에 의한 고집적 DRAM의 콘택형성방법에 관한 것으로, 반도체장치의 금속배선 콘택형성방법에 있어서, 반도체기판위에 트랜지스터를 형성한 후 상기 트랜지스터상에는 다층의 절연막을 형성하고 그 측면에는 스페이서를 형성하는 공정과, 상기 다층의 절연막 및 스페이서상에 식각저지층을 형성하는 공정, 상기 식각저지층상에 평탄화층을 형선한 후 포토리소그래피공정에 의해 콘택부위에 해당하는 부분의 상기 평탄화층을 식각하는 공정, 상기 남겨진 평탄화층을 마스크로 하여 상기 식각저지층을 식각한 후 결과물을 건식산화방식에 의해 산화시켜 상기 식각저지층 측면에 산화막을 형성하는 공정, 및 셀프얼라인방식에 의해 콘택부위를 오픈시킨 후 도전층을 증착하고 금속배선패턴으로 패터닝하는 공정이 구비된 것을 특징으로 하는 본 발명에 의하면, 셀프얼라인콘택공정을 이용하면서도 금속배선층의 패터닝을 용이하게 행할 수 있는 콘택형성방법이 제공되므로 디바이스 제조공정에 적용했을때 보다 신뢰성 높은 디바이스의 실현에 기여할 수 있게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a highly integrated DRAM contact by self-alignment. In the method for forming a metal wiring contact of a semiconductor device, after forming a transistor on a semiconductor substrate, a multilayer insulating film is formed on the transistor, and a spacer is formed on the side thereof. Forming a etch stop layer on the multilayer insulating film and the spacer, forming a planarization layer on the etch stop layer, and then etching the planarization layer corresponding to the contact portion by a photolithography process. And etching the etch stop layer using the remaining planarization layer as a mask and oxidizing the resultant by a dry oxidation method to form an oxide film on the etch stop layer side, and a contact portion by a self-align method. After opening, a process of depositing a conductive layer and patterning the metallization pattern is provided. According to the present invention, a contact forming method capable of easily patterning a metal wiring layer while using a self-aligned contact process is provided, thereby contributing to the realization of a more reliable device when applied to a device manufacturing process.

Description

금속배선 콘택형성방법Metal wiring contact formation method

제1(a)도 및 제1(b)도는 종래의 금속배선 콘택형성방법을 도시한 것이고,1 (a) and 1 (b) show a conventional metallization contact forming method,

제2(a)도 내지 제2(d)도는 본 발명의 일실시예에 의한 금속배선 콘택형성방법을 도시한 것이며,2 (a) to 2 (d) show a metallization contact forming method according to an embodiment of the present invention,

제3(a)도 및 제3(b)도는 본 발명의 다른 실시예의 의한 금속배선 콘택형성방법을 도시한 것이다.3 (a) and 3 (b) show a metallization contact forming method according to another embodiment of the present invention.

본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 셀프얼라인에 의한 고집적 DRAM의 콘택형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact of a highly integrated DRAM by self-alignment.

반도체 메모리장치가 고집적화되어 감에 따라 메모리셀 크기도 미세화되어 비트선접속을 위한 다이렉트콘택(Direct contact) 및 메모리셀의 커패시터전극접속을 위한 매몰콘택(Buried Contact)의 크기도 더욱 작아질 것이 요구되고 있다. 또한 비트선형성공정상 스트링거(Stringer)와 같은 디바이스에 나쁜 영향을 미치는 결함이 생길 수 있음에 따라 이러한 문제를 해결하기 위해 하지층(Under layer)의 평탄화가 요구된다. 그러나 하지층을 평탄화시키게 되면 요철부위를 이용하여 에치량을 조절하여 콘택부위만을 오픈시키는 기술인 셀프얼라인콘택(self-align contact) 공정을 실시할 수 없는 문제점이 있다.As semiconductor memory devices become more integrated, memory cell sizes are also miniaturized, so that the size of the direct contact for bit line connection and the buried contact for capacitor electrode connection of the memory cell are also required to be smaller. have. In addition, as the bit-linearity process may have a defect that adversely affects a device such as a stringer, an underlayer planarization is required to solve this problem. However, when the underlying layer is planarized, there is a problem in that a self-aligned contact process, which is a technology of opening only the contact portion by adjusting the amount of etch using the uneven portion, cannot be performed.

제1(a)도 및 제1(b)도를 참조하여 종래의 금속배선 콘택형성방법을 설명하면 다음과 같다.Referring to FIGS. 1 (a) and 1 (b), a conventional metallization contact forming method will be described as follows.

제1(a)도는 셀프얼라인콘택기술을 이용하여 콘택홀을 형성한 후 금속배선이 되는 도전층(10)을 형성한 것을 도시한 것이다. 그러나 이 방법은 셀프얼라인콘택기술 자체가 디바이스의 요철부위를 이용한 것이기 때문에 콘택홀 형성후 도전층을 증착한 다음 금속배선패턴을 형성할 때 상기 요철부위로 인해 에칭이 매우 어렵게 되는 문제가 있다.FIG. 1 (a) shows the formation of the conductive layer 10 which becomes the metal wiring after forming the contact hole by using the self-aligned contact technique. However, since the self-aligned contact technology itself uses uneven portions of the device, etching is very difficult due to the uneven portions when the conductive layer is deposited after forming the contact hole and then the metal wiring pattern is formed.

제1(b)도는 상기의 문제점을 해결하기 위해 먼저 절연층(7)으로 평탄화시킨 후에 콘택을 형성하고 도전층(10)을 증착시킨 것을 도시한 것이다. 그러나 이 방법은 콘택부위를 셀프얼라인콘택공정으로 형성할 수 없으므로 미세콘택형성이 어려울 뿐 아니라 반도체기판(1)의 콘택부위까지 에칭한 후 기타 다른 도전층, 예컨대 게이트전극(3)과의 단락(short)을 방지하기 위한 스페이서(8)를 형성한 다음 도전층을 형성해야 하는 공정상의 번거로움이 따른다. 제1(a)도 및 제1(b)도에서 미설명부호 2는 필드산화막, 4는 스페이서, 5는 보호절연막, 6은 중간절연막을 나타낸다. 따라서 본 발명은 상술한 문제점들을 해결하기 위해 셀프얼라인콘택 공정을 이용하면서도 금속배선층의 패터닝을 용이하게 행할 수 있는 콘택형성방법을 제공하는 것을 그 목적으로 한다.FIG. 1 (b) shows that in order to solve the above problem, first, the insulating layer 7 is planarized to form a contact, and then the conductive layer 10 is deposited. However, this method is difficult to form a contact because the contact portion cannot be formed by a self-aligned contact process, and after etching to the contact region of the semiconductor substrate 1, a short circuit with other conductive layers such as the gate electrode 3 is performed. Forming a spacer 8 to prevent a short is followed by a process troublesome to form a conductive layer. In FIGS. 1 (a) and 1 (b), reference numeral 2 denotes a field oxide film, 4 a spacer, 5 a protective insulating film, and 6 an intermediate insulating film. Accordingly, an object of the present invention is to provide a contact forming method that can easily pattern a metal wiring layer while using a self-aligned contact process to solve the above problems.

상기 목적을 달성하기 위해 본 발명의 방법은 반도체장치의 금속배선 콘택형성방법에 있어서, 반도체기판위에 트랜지스터를 형성한 후 상기 트랜지스터상에는 다층의 절연막을 형성하고 그 측면에는 스페이서를 형성하는 공정과, 상기 다층의 절연막 및 스페이서상에 식각저지층을 형성하는 공정, 상기 식각저지층상에 평탄화층을 형성한 후 포토리소그래피공정에 의해 콘택부위에 해당하는 부분의 상기 평탄화층을 식각하는 공정, 상기 남겨진 평탄화층을 마스크로 하여 상기 식각저지층을 식각한 후 결과물을 건식산화방식에 의해 산화시켜 상기 식각저지층 측면에 산화막을 형성하는 공정, 및 셀프얼라인방식에 의해 콘택부위를 오픈시킨 후 도전층을 증착하고 금속배선패턴으로 패터닝하는 공정이 구비된 것을 특징으로 하며, 또한 반도체장치의 금속배선 콘텍형성방법에 있어서, 반도체기판위에 트랜지스터를 형성한 후 상기 트랜지스터를 둘러싸도록 트랜지스터의 게이트전극위에는 보호절연막을 형성하고 상기 게이트전극 및 보호절연막의 측면에는 스페이서 산화막을 형성하는 공정과, 상기 결과물 전면에 산화마스크층 및 중간절연막을 순차적으로 형성하는 공정, 상기 중간절연막상에 식각저지층을 형성하는 공정, 상기 식각저지층상에 평탄화층을 형성한 후 포토리소그래피공정에 의해 콘택부위에 해당하는 부분의 상기 평탄화층을 식각하는 공정, 상기 남겨진 평탄화층을 마스크로 하여 상기 식각저지층을 식각한 후 결과물을 습식산화분위기에서 산화시키는 공정, 및 셀프얼라인방식에 의해 콘택부위를 오픈시킨 후 도전층을 증착하고 금속배선패턴으로 패터닝하는 공정이 구비된 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a metal wiring contact in a semiconductor device, comprising: forming a transistor on a semiconductor substrate, forming a multilayer insulating film on the transistor, and forming a spacer on the side thereof; Forming an etch stop layer on the multilayer insulating layer and the spacer, forming a planarization layer on the etch stop layer, and then etching the planarization layer of a portion corresponding to the contact portion by a photolithography process, and leaving the planarization layer Etching the etch stop layer using a mask as a mask and oxidizing the resultant by a dry oxidation method to form an oxide film on the side of the etch stop layer, and opening a contact portion by a self-aligned method and depositing a conductive layer. And patterning the metal wiring pattern. A method of forming a metal interconnect contact, comprising: forming a transistor on a semiconductor substrate and then forming a protective insulating film on the gate electrode of the transistor so as to surround the transistor, and forming a spacer oxide film on the side of the gate electrode and the protective insulating film; A step of sequentially forming an oxide mask layer and an intermediate insulating film on the entire surface; a step of forming an etch stop layer on the intermediate insulating film; and a portion corresponding to a contact portion by a photolithography process after forming a planarization layer on the etch stop layer Etching the planarization layer, etching the etch stop layer using the remaining planarization layer as a mask, oxidizing the resultant in a wet oxidation atmosphere, and opening a contact region by a self-aligning method, and then conducting a conductive layer. Is deposited and patterned into a metallization pattern. The features.

이하, 도면을 참조하여 본 발명을 상세히 설명한다. 제2(a)도 내지 제2(d)도는 본 발명의 일실시예를 나타낸다.Hereinafter, the present invention will be described in detail with reference to the drawings. 2 (a) to 2 (d) show one embodiment of the present invention.

제2(a)도를 참조하면, 실리콘기판(1)상에 트랜지스터를 형성하고 상기 트랜지스터를 둘러싸도록 트랜지스터의 게이트전극(3)위에는 보호절연막(5), 예컨대 산화막을 형성하고 게이트전극(3) 및 상기 산화막(5)의 측면에는 스페이서산화막(4)을 형성한 다음, 결과물 전면에 중간절연막(6), 예컨대 산화막을 증착한다. 이어서 식각저지증(Etch stop layer)을 상기 중간절연막(6)상에 형성하는데 이때 식각저지층으로는 산화막과의 식각선택비가 높은 폴리실리콘 또는 단결정실리콘과 같은 물질을 사용할 수 있는데 본 발명에서는 폴리실리콘을 사용하였다.Referring to FIG. 2 (a), a protective insulating film 5, for example, an oxide film is formed on the gate electrode 3 of the transistor so as to form a transistor on the silicon substrate 1 and surround the transistor, and the gate electrode 3 is formed. And forming a spacer oxide film 4 on the side of the oxide film 5, and then depositing an intermediate insulating film 6, for example, an oxide film on the entire surface of the resultant. Next, an etch stop layer is formed on the intermediate insulating layer 6, wherein a material such as polysilicon or single crystal silicon having a high etching selectivity with respect to the oxide layer may be used as the etch stop layer. Was used.

이어서 평탄화층(12), 예컨대 BPSG막을 상기 폴리실리콘(11)상에 증착하여 평탄화시킨다. 다음에 상기 BPSG(12)위에 포토레지스트(13)를 도포하고 포토리소그래프공정에 의해 콘택부위를 오픈시킨 후 상기 BPSG막(12)을 상기 식각저지층인 폴리실리콘(11)에 이를 때까지 식각한다.A planarization layer 12, such as a BPSG film, is then deposited on the polysilicon 11 to planarize. Next, a photoresist 13 is applied on the BPSG 12 and the contact portion is opened by a photolithography process, and the BPSG film 12 is etched until the polysilicon 11, which is the etch stop layer, is reached. do.

제2(b)도를 참조하면, 상기 BPSG막(12)의 식각에 의해 노출된 부분의 상기 폴리실리콘(11)을 식각하고 상기 포토레지스트를 제거해 낸 다음, 결과물을 건식산화방법에 의해 산화시키면 상기 폴리실리콘(11)의 노출된 측면부위에 산화막(15)이 성장하게 되는데 이에 따라 상기 식각저지층으로 사용된 폴리실리콘(11)과 후속공정에 의해 형성될 도전층과 단락이 방지된다.Referring to FIG. 2 (b), when the polysilicon 11 of the portion exposed by the etching of the BPSG film 12 is etched and the photoresist is removed, the resultant is oxidized by a dry oxidation method. The oxide film 15 is grown on the exposed side portions of the polysilicon 11, thereby preventing the polysilicon 11 used as the etch stop layer and the conductive layer to be formed by a subsequent process and a short circuit.

또한 제2(c)도에 도시한 바와 같이 상기 산화공정에 의해 노출된 폴리실리콘측면부위에 산화막을 형성한 다음 다시 얇은 산화막을 증착한 후 에치백하여 스페이서(16)를 형성할 수도 있다.In addition, as shown in FIG. 2 (c), an oxide film may be formed on the polysilicon side portion exposed by the oxidation process, and then a thin oxide film may be deposited and then etched back to form a spacer 16.

제2(d)도를 참조하면, 셀프얼라인방식으로 콘택부위를 RIE(Reactiveion etching)에 의해 오픈시킨 다음 도전층(18)을 형성한다. 이어서 상기 도전층(18)을 금속배선패턴으로 패터닝하는데 이때 패터닝공정은 평탄화층인 상기 BPSG막(12)상에서 행해지므로 완벽하게 패터닝할 수 있다.Referring to FIG. 2 (d), the contact portion is opened by RIE (Reactiveion etching) in a self-aligned manner to form a conductive layer 18. Subsequently, the conductive layer 18 is patterned by a metal wiring pattern. The patterning process is performed on the BPSG film 12, which is a planarization layer, so that the patterning process can be perfectly patterned.

본 발명의 다른 실시예를 제3(a)도 및 제3(b)도를 참조하여 설명하면 다음과 같다.Another embodiment of the present invention will be described with reference to FIGS. 3 (a) and 3 (b).

먼저, 제3(a)도를 참조하면, 식각저지층으로 사용한 폴리실리콘(11)을 완벽하게 제거하기 위하여 중간절연막(6)을 형성하기 전에 매우 얇은, 예컨대 50Å∼100Å, 바람직하게는 70Å두께의 산화마스크층(20), 예컨대 Si3N4막을 형성한다(Si3N4증착공정 이전의 공정은 본 발명의 일실시예와 동일하므로 설명을 생략한다). 이어서 상기 Si3N4막(20)상에 중간절연막(6), 식각저지층인 폴리실리콘(11) 및 평탄화층인 BPSG막(12)을 차례로 형성한 다음 상기 본 발명의 일실시예와 동일한 방법에 의해 폴리실리콘(11)까지 식각해낸다.First, referring to FIG. 3 (a), in order to completely remove the polysilicon 11 used as an etch stop layer, a very thin, for example, 50 kPa to 100 kPa, preferably 70 kPa thickness is formed before the intermediate insulating film 6 is formed. An oxide mask layer 20 of, for example, a Si 3 N 4 film is formed (the process before the Si 3 N 4 deposition process is the same as in the embodiment of the present invention and description thereof is omitted). Subsequently, an intermediate insulating film 6, a polysilicon 11 as an etch stop layer, and a BPSG film 12 as a planarization layer are sequentially formed on the Si 3 N 4 film 20, and then the same as in the embodiment of the present invention. The polysilicon 11 is etched by the method.

제3(b)도를 참조하면, 상기 결과물을 습식산화분위기에서 산화시켜 상기 식각되지 않고 남아있는 폴리실리콘을 완전히 산화막(11')으로 변환시킨다. 이후 공정은 상기 일실시예와 동일하다.Referring to FIG. 3 (b), the resultant is oxidized in a wet oxidation atmosphere to completely convert the polysilicon remaining without etching into an oxide film 11 '. The process is the same as in the above embodiment.

이상 상술한 바와 같이 본 발명에 의하면, 셀프얼라인콘택공정을 이용하면서도 금속배선층의 패터닝을 용이하게 행할 수 있는 콘택형성방법이 제공되므로 디바이스제조공정에 적용했을때 보다 신뢰성 높은 디바이스의 실현에 기여할 수 있게 된다.As described above, the present invention provides a contact forming method that can easily pattern a metal wiring layer while using a self-aligned contact process, thereby contributing to the realization of a more reliable device when applied to a device manufacturing process. Will be.

Claims (16)

반도체장치의 금속배선 콘택형성방법에 있어서, 반도체기판위에 트랜지스터를 형성한 후 상기 트랜지스터상에는 다층의 절연막을 형성하고 그 측면에는 스페이서를 형성하는 공정과, 상기 다층의 절연막 및 스페이서상에 식각저지층을 형성하는 공정, 상기 식각저지층상에 평탄화층을 형성한 후 포토리소그래피공정에 의해 콘택부위에 해당하는 부분의 상기 평탄화층을 식각하는 공정, 상기 남겨진 평탄화층을 마스크로 하여 상기 식각저지층을 식각한 후 결과물을 건식산화방식에 의해 산화시켜 상기 식각저지층 측면에 산화막을 형성하는 공정, 및 셀프얼라인방식에 의해 콘택부위를 오픈시킨 후 도전층을 증착하고 금속배선패턴으로 패터닝하는 공정이 구비된 것을 특징으로 하는 금속배선 콘택형성방법.A method for forming a metallization contact in a semiconductor device, comprising: forming a transistor on a semiconductor substrate, and then forming a multilayer insulating film on the transistor and forming a spacer on the side thereof; and forming an etch stop layer on the multilayer insulating film and the spacer. Forming a planarization layer on the etch stop layer, and then etching the planarization layer of a portion corresponding to the contact portion by a photolithography process, and etching the etch stop layer using the remaining planarization layer as a mask. Thereafter, the resultant is oxidized by a dry oxidation method to form an oxide film on the side of the etch stop layer, and a process of depositing a conductive layer and patterning a metal wiring pattern by opening a contact portion by a self-alignment method. Metal wiring contact forming method, characterized in that. 제1항에 있어서, 상기 식각저지층 측면에 산화막을 형성하는 공정과 도전층을 증착하고 금속배선패턴으로 패터닝하는 공정 사이에 상기 산화막 및 평탄화층 측면에 스페이서를 형성하는 공정이 포함되는 것을 특징으로 하는 금속배선 콘택형성방법.The method of claim 1, further comprising forming a spacer on the side of the oxide layer and the planarization layer between the step of forming an oxide layer on the side of the etch stop layer and the process of depositing a conductive layer and patterning the metal layer pattern. A metallization contact forming method. 제1항에 있어서, 상기 트랜지스터상에는 다층의 절연막을 형성하고 그 측면에는 스페이서를 형성하는 공정은 상기 트랜지스터를 둘러싸도록 트랜지스터의 게이트전극위에는 보호절연막을 형성하고 상기 게이트전극 및 보호절연막의 측면에는 스페이서산화막을 형성한 다음 결과물 전면에 중간절연막을 형성하는 공정임을 특징으로 하는 금속배선 콘택형성방법.2. The process of claim 1, wherein forming a multilayer insulating film on the transistor and forming a spacer on the side thereof forms a protective insulating film on the gate electrode of the transistor so as to surround the transistor, and a spacer oxide film on the side of the gate electrode and the protective insulating film. And forming an intermediate insulating film on the entire surface of the resultant. 제3항에 있어서, 상기 보호절연막 및 중간절연막은 산화막임을 특징으로 하는 금속배선 콘택형성방법.4. The method of claim 3, wherein the protective insulating film and the intermediate insulating film are oxide films. 제1항에 있어서, 상기 식각저지층은 산화막과의 식각선택비가 높은 물질로 형성함을 특징으로 하는 금속배선 콘택형성방법.The method of claim 1, wherein the etch stop layer is formed of a material having a high etching selectivity with respect to an oxide film. 제5항에 있어서, 상기 산화막과의 식각선택비가 높은 물질은 폴리실리콘 또는 단결정실리콘임을 특징으로 하는 금속배선 콘택형성방법.The method of claim 5, wherein the material having a high etching selectivity with respect to the oxide layer is polysilicon or single crystal silicon. 제1항에 있어서, 상기 평탄화층은 BPSG로 형성함을 특징으로 하는 금속배선 콘택형성방법.The method of claim 1, wherein the planarization layer is formed of BPSG. 제1항에 있어서, 상기 셀프얼라인방식에 의해 콘택부위를 오픈시키는 공정은 RIE에 의해 행하는 것을 특징으로 하는 금속배선 콘택형성방법.The method of claim 1, wherein the step of opening the contact portion by the self-aligning method is performed by RIE. 반도체장치의 금속배선 콘택형성방법에 있어서, 반도체기판위에 트랜지스터를 형성한 후 상기 트랜지스터를 둘러싸도록 트랜지스터의 게이트전극위에는 보호절연막을 형성하고 상기 게이트전극 및 보호절연막의 측면에는 스페이서 산화막을 형성하는 공정과, 상기 결과물 전면에 산화마스크층 및 중간절연막을 순차적으로 형성하는 공정, 상기 중간절연막상에 식각저지층을 형성하는 공정, 상기 식각저지층상에 평탄화층을 형성한 후 포토리소그래피공정에 의해 콘택부위에 해당하는 부분의 상기 평탄화층을 식각하는 공정, 상기 남겨진 평탄화층을 마스크로 하여 상기 식각저지층을 식각한 후 결과물을 습식산화분위기에서 산화시키는 공정, 및 셀프얼라인방식에 의해 콘택부위를 오픈시킨 후 도전층을 증착하고 금속배선패턴으로 패터닝하는 공정이 구비된 것을 특징으로 하는 금속배선 콘택형성방법.A metal wiring contact forming method of a semiconductor device, comprising: forming a transistor on a semiconductor substrate and forming a protective insulating film on the gate electrode of the transistor so as to surround the transistor and forming a spacer oxide film on the side of the gate electrode and the protective insulating film; And sequentially forming an oxide mask layer and an intermediate insulating film on the entire surface of the resultant, forming an etch stop layer on the intermediate insulating film, and forming a planarization layer on the etch stop layer, followed by a photolithography process. Etching the planarization layer in a corresponding portion, etching the etch stop layer using the remaining planarization layer as a mask, and oxidizing the resultant in a wet oxidation atmosphere, and opening a contact portion by a self-alignment method. After depositing the conductive layer and patterning the metal wiring pattern The metal wire forming the contact characterized in that the bar. 제9항에 있어서, 상기 보호절연막 및 중간절연막은 산화막임을 특징으로 하는 금속배선 콘택형성방법.10. The method of claim 9, wherein the protective insulating film and the intermediate insulating film are oxide films. 제9항에 있어서, 상기 산화마스크층은 Si3N4임을 특징으로 하는 금속배선 콘택형성방법.The method of claim 9, wherein the oxide mask layer is Si 3 N 4 . 제9항에 있어서, 상기 산화마스크층은 50Å∼100Å의 두께로 얇게 형성하는 것을 특징으로 하는 금속배선 콘택형성방법.10. The method of claim 9, wherein the oxide mask layer is formed thin in a thickness of 50 kPa to 100 kPa. 제9항에 있어서, 상기 식각저지층은 산화막과의 식각선택비가 높은 물질로 형성함을 특징으로 하는 금속배선 콘택형성방법.The method of claim 9, wherein the etch stop layer is formed of a material having a high etching selectivity with respect to an oxide film. 제13항에 있어서, 상기 산화막과의 식각선택비가 높은 물질은 폴리실리콘 또는 단결정실리콘임을 특징으로 하는 금속배선 콘택형성방법.The method of claim 13, wherein the material having a high etching selectivity with respect to the oxide layer is polysilicon or single crystal silicon. 제9항에 있어서, 상기 평탄화층은 BPSG로 형성함을 특징으로 하는 금속배선 콘택형성방법.10. The method of claim 9, wherein the planarization layer is formed of BPSG. 제9항에 있어서, 상기 셀프얼라인방식에 의해 콘택부위를 오픈시키는 공정은 RIE에 의해 행하는 것을 특징으로 하는 금속배선 콘택형성방법.10. The method of claim 9, wherein the step of opening the contact portion by the self-aligning method is performed by RIE.
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