KR100211541B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100211541B1 KR100211541B1 KR1019960023282A KR19960023282A KR100211541B1 KR 100211541 B1 KR100211541 B1 KR 100211541B1 KR 1019960023282 A KR1019960023282 A KR 1019960023282A KR 19960023282 A KR19960023282 A KR 19960023282A KR 100211541 B1 KR100211541 B1 KR 100211541B1
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- Prior art keywords
- film
- forming
- semiconductor device
- silicide
- manufacturing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 36
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 150000002500 ions Chemical class 0.000 claims abstract description 16
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 230000008021 deposition Effects 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 229910015900 BF3 Inorganic materials 0.000 claims description 3
- 238000005280 amorphization Methods 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 2
- 229910008484 TiSi Inorganic materials 0.000 abstract description 17
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 6
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 230000002860 competitive effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 13
- 238000002955 isolation Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000015271 coagulation Effects 0.000 description 1
- 238000005345 coagulation Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 실리콘 기판 상에 Ti막을 형성하고, 상기 Ti막을 Ge 이온을 주입하여 선 비정질화 시킨후에 일차 열처리하여 C49상과 C54상의 불안정한 Ti 실리사이드막을 형성하며, 상기에서 실리사이드화되지 않은 Ti막을 제거한 후, 이차로 열처리하여 안정된 C54상의 Ti 실리사이드막을 형성하였으므로, 1차 RTA는 온도가 낮거나, Ti막의 증착 두께가 얇거나 선폭이 가늘어도 쉽게 Ti 실리사이드막을 형성할 수 있도록함으로써 열 공정의 신뢰성 및 수율을 높이고, TiN과 TiSi2의 경쟁적 반응에서 초기 Ti 증착 두께에 대한 TiSi2화 두께 비가 높게되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, which comprises forming a Ti film on a silicon substrate, implanting Ge ions into the Ti film to pre-amorphize and then performing a primary heat treatment to form an unstable Ti silicide film on the C49 phase and the C54 phase, The Ti silicide film on the C54 phase is formed by the second heat treatment after the removal of the un-silicided Ti film, so that the first RTA can form the Ti silicide film easily with a low temperature, a thin Ti film, increasing the reliability and yield of the thermal process, a technique capable of TiN and is highly TiSi two pixel thickness ratio to the initial Ti deposition thickness in the competitive reactions of the TiSi 2 enhance the reliability of the process yield and device operation by allowing.
Description
제1(a)도 내지 제1(d)도는 종래 기술의 실시예에 따른 반도체소자의 제조 공정도.FIG. 1 (a) through FIG. 1 (d) also show a manufacturing process of a semiconductor device according to an embodiment of the prior art.
제2(a)도 내지 제2(f)도는 본 발명의 실시예에 따른 반도체소자의 제조 공정도.FIGS. 2 (a) through 2 (f) are diagrams showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
11 : 반도체기판 13 : 소자분리 산화막11: semiconductor substrate 13: element isolation oxide film
15 ; 게이트 산화막 17 : 게이트전극15; Gate oxide film 17: gate electrode
19 : 절연막 스페이서 21 : 소오스/드레인 영역19: insulating film spacer 21: source / drain region
23 : Ti막 24 : 비정질 Ti막23: Ti film 24: amorphous Ti film
25 : Ti실리사이드막 26 : 층간 절연막25: Ti silicide film 26: Interlayer insulating film
27 : 콘택홀27: contact hole
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 소자의 동작 속도를 증가시키고, 저항을 감소시키며 게이트전극에 의한 토플로지를 낮추기 위하여 게이트전극과 소오스/드레인 영역의 상측에 Ti 실리사이드막을 사용하는 반도체소자에서 Ti 실리사이드막의 막질 저하를 방지하고 공정을 간단하게 하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a Ti silicide film on a gate electrode and on a source / drain region in order to increase the operating speed of the device, reduce the resistance, and lower the topography due to the gate electrode. The present invention relates to a method of manufacturing a semiconductor device capable of preventing degradation of a film quality of a Ti silicide film in a device and simplifying a process, thereby improving process yield and reliability of a device operation.
반도체소자가 고집적화되어 감에 따라 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor; 이하 MOS FET라 칭함)의 게이트전극도 폭이 줄어들고 있으나, 게이트전극의 폭이 N배 줄어들면 게이트전극의 전기 저항이 N배 증가되어 반도체소자의 동작 속도를 떨어뜨리는 문제점이 있다. 따라서 게이트전극의 저항을 감소시키기 위하여 가장 안정적인 MOSFET 특성을 나타내는 폴리실리콘층/산화막 계면의 특성을 이용하여 폴리실리콘층과 실리사이드의 적층 구조인 폴리사이드가 저 저항 게이트로서 사용된다.As the semiconductor device becomes highly integrated, the width of the gate electrode of the MOS FET is also reduced. However, if the width of the gate electrode is reduced by N times, the electrical resistance of the gate electrode is reduced There is a problem that the operating speed of the semiconductor device is lowered. In order to reduce the resistance of the gate electrode, polycide, which is a stacked structure of a polysilicon layer and a silicide, is used as a low resistance gate, taking advantage of the characteristics of the polysilicon layer / oxide film interface that exhibits the most stable MOSFET characteristics.
일반적으로 반도체 회로를 구성하는 트랜지스터의 기능에서 가장 중요한 기능은 전류구동능력이며, 이를 고려하여 MOSFET의 채널 폭을 조정한다. 가장 널리 쓰이는 MOSFET는 게이트전극으로 불순물이 도핑된 폴리실리콘층을 사용하고, 소오스/드레인 영역은 반도체기판상에 불순물이 도핑된 확산 영역이 사용된다. 여기서 게이트전극의 면저항은 약 30∼70Ω/? 정도이며, 소오스/드레인 영역의 면저항은 N+의 경우에는 약 70∼150Ω/?, P+의 경우 약 100∼250Ω/? 정도이며, 게이트전극이나 소오스/드레인 영역 상에 형성되는 콘택의 경우에는 콘택 저항이 하나의 콘택당 약 30∼70Ω/? 정도이다.In general, the most important function in the function of a transistor constituting a semiconductor circuit is a current driving capability, and the channel width of the MOSFET is adjusted in consideration of this. The most widely used MOSFET uses a polysilicon layer doped with an impurity as a gate electrode, and a diffusion region doped with an impurity is used as a source / drain region on a semiconductor substrate. The gate electrode has a sheet resistance of about 30 to 70? /? And the sheet resistance of the source / drain region is about 70 to 150? /? In the case of N + and about 100 to 250? /? In the case of P +. And in the case of a contact formed on the gate electrode or the source / drain region, the contact resistance is about 30 to 70? /? Per contact. Respectively.
이와같이 게이트전극과 소오스/드레인 영역의 높은 면저항 및 콘택저항을 감소시키기 위하여 실리사이드(salicide; self-aligned silicide) 방법이나 선택적 금속막 증착 방법으로 게이트전극과 소오스/드레인 영역의 상부에만 금속 실리사이드막을 형성하여 MOS FET의 전류구동능력을 증가시켰다. 이러한 실리사이드중에서 TiSi2는 저항이 가장 낮고, 비교적 열안정성이 우수하고 제조방법이 용이하여 가장 각광받고 있다.In order to reduce the high surface resistance and contact resistance of the gate electrode and the source / drain regions, a metal silicide film is formed only on the gate electrode and the source / drain region by a salicide (self-aligned silicide) method or a selective metal film deposition method Thereby increasing the current driving capability of the MOS FET. Of these silicides, TiSi 2 has the lowest resistance, has excellent thermal stability, and is easily attracted to the manufacturing process.
Ti 실리사이드를 사용하면 게이트전극과 소오스/드레인 영역의 면저항을 약 50Ω/?, 콘택 저항은 콘택당 약 3Ω/? 이하로 현저하게 감소되어 MOSFET의 전류구동능력이 40% 이상 증가되므로 MOSFET의 고집적화가 가능하다.With Ti silicide, the contact resistance of the gate electrode and the source / drain region is about 50? /?, And the contact resistance is about 3? /? And the current driving ability of the MOSFET is increased by 40% or more, so that it is possible to highly integrate the MOSFET.
따라서 기가급 이상의 DRAM 소자나, 고집적화 및 고속동작이 요구되는 로직 소자에서는 게이트전극과 소오스/드레인 영역의 표면에 실리사이드막을 형성하여 면저항을 낮추어 줄 필요성이 증가되고 있다.Therefore, in the case of a DRAM device having a gigabyte or more or a logic device requiring high integration and high-speed operation, a need for lowering the sheet resistance by forming a silicide film on the surface of the gate electrode and the source / drain region is increasing.
제1(a)도 내지 제1(d)도는 종래 기술에 따른 반도체소자의 제조 공정도로서, MOSFET의 예이다.FIG. 1 (a) through FIG. 1 (d) are diagrams showing a manufacturing process of a semiconductor device according to the prior art, which is an example of a MOSFET.
먼저, 반도체기판(11)상에 소자분리 산화막(13)과 게이트 산화막(15)을 형성하고, 상기 게이트 산화막(15)상에 일련의 게이트전극(17)을 다결정 실리콘층 패턴으로 형성한 후, 상기 게이트전극(17)의 양측벽에 절연막 스페이서(19)를 형성한다(제1(a)도 참조).A device isolation oxide film 13 and a gate oxide film 15 are formed on a semiconductor substrate 11 and a series of gate electrodes 17 are formed on the gate oxide film 15 in a polycrystalline silicon layer pattern. An insulating film spacer 19 is formed on both side walls of the gate electrode 17 (see also FIG. 1 (a)).
그 다음 상기 게이트전극(17) 양측의 노출된 반도체기판(11)의 상부에서 비소(As) 또는 불화 붕소(BF2) 이온을 3E15/㎤ 이상의 농도로 주입하여 n+또는 p+타입의 소오스/드레인 영역(21)을 형성한다(제1(b)도 참조).Then, arsenic (As) or boron fluoride (BF 2 ) ions are implanted at a concentration of 3E15 / cm 3 or more at the top of the exposed semiconductor substrate 11 on both sides of the gate electrode 17 to form n + or p + Drain regions 21 are formed (see also FIG. 1 (b)).
그후, 상기 구조의 전표면에 실리사이드용 금속인 Ti층(23)을 10mTorr 내외의 압력으로, 기판의 온도는 25∼300정도가 되도록 하여 형성한다(제1(c)도 참조).Thereafter, a Ti layer 23, which is a metal for silicide, is applied to the entire surface of the structure at a pressure of about 10 mTorr, the temperature of the substrate is 25 ~ 300 (See Fig. 1 (c)).
그리고, 일차 급속 열처리 공정(rapid thermal press; 이하 RTP라 칭함)으로 상기 게이트전극(17)의 상부와 그 양측의 반도체기판(11)에 실리콘이 확산되어 각각의 상부에 위치한 Ti층(23)을 실리레이션 시켜 불안정한 전기적 기계적 성질을 가지는 C49상의 TiSix층(도시되지 않음)을 형성한다.Silicon is diffused in the upper portion of the gate electrode 17 and on the semiconductor substrate 11 on both sides of the gate electrode 17 by a rapid thermal press (hereinafter referred to as RTP), and the Ti layer 23 located on each upper portion is diffused To form a TiSi x layer (not shown) on C49 having unstable electrical and mechanical properties.
그리고, TiSi2화 하지 않은 Ti나 TiN층은 선택적으로 식각하여 제거하고, 상기 제1차 RTP처리된 실리사이드막을 고온에서 제2차 RTP하여 저 저항의 C54상을 가갖는 Ti 실리사이드막(25)을 형성한다.Then, the Ti or TiN layer not converted to TiSi 2 is selectively removed by etching, and the first RTP-processed silicide film is subjected to second RTP at a high temperature to form a Ti silicide film 25 having a low resistance C54 phase .
여기서, RTP 공정은 소정의 조건, 예를들어 500∼780에서 5∼40초간 다단계 열처리 방법으로 형성하는데, 퍼니스 어닐의 온도는 대부분의 TiSix가 750에서 저저항의 C54상의 TiSi2로 상전이하는 것을 참고로 하여 온도 및 시간을 결정한다(제1(d)도 참조).Here, the RTP process is performed under predetermined conditions, for example, 500 to 780 For 5 to 40 seconds. The temperature of the furnace anneal is such that most of the TiSi x is 750 (See Fig. 1 (d)) with reference to the phase transition from Ti to TiSi 2 on C54 of low resistance.
상기와 같은 종래 기술에 따른 반도체소자의 제조방법은, Ti막을 증착한 후의 일차 RTP가 질소 분위기에서 실시됨으로써 TiN과 TiSi2의 경쟁적 반응(competing reaction)에 의해 초기 증착된 Ti의 두께에 비해 형성된 Ti 실리사이드막의 두께가 얇게 박형화되어 선폭이 감소되며, 750이하의 온도에서는 상전이가 일어나지 않게되어 저항이 증가되는 문제점이 있다.In the method of manufacturing a semiconductor device according to the related art as described above, the primary RTP after depositing a Ti film is formed in a nitrogen atmosphere, so that Ti (Ti) formed compared with the thickness of Ti initially deposited by competing reaction of TiN and TiSi 2 The thickness of the silicide film is thinned to reduce the line width, and 750 Phase transition does not occur at a temperature below the above-mentioned range, resulting in an increase in resistance.
또한 상기의 문제점을 해결하기 위하여 게이트와 소오스/드레인의 면저항을 줄이기 위하여 TiSi2막을 두껍게 할 경우 소오스/드레인의 접합 누설 전류를 커지게 하는 다른 문제점이 있다.Further, in order to solve the above problems, there is another problem that when the TiSi 2 film is thickened to reduce the sheet resistance of the gate and the source / drain, the junction leakage current of the source / drain is increased.
그리고, 상기의 이유로 인해 500Å 이하로 TiSi2가 얇아지면 C49상에서 C54상으로의 상전이 온도를 증가시켜야 하는데 이 경우 응집 현상이 일어나 단선이 발생되는 또 다른 문제점이 있다.If the TiSi 2 is thinned to 500 Å or less for the above reason, the phase transition temperature from C49 to C54 phase should be increased. In this case, there is another problem that coagulation phenomenon occurs and disconnection occurs.
본 발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본 발명의 목적은 Ti막 증착 후에 불순물 이온을 이온 주입하여 Ti막을 비정질화 하여 Ti-Ti의 결합력을 약화시켜, 1차 RTA 온도가 낮거나 Ti의 증착 두께가 얇거나, 또는 선폭이 가늘어도 쉽게 TiSi2을 형성할 수 있도록 하여 열 공정의 신뢰성 및 수율을 높이고, TiN과 TiSi2의 경쟁적 반응에서 초기 Ti증착 두께에 대한 TiSi2화, 즉 실라사이드화 두께 비가 높게 되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a method of forming a Ti film by ion implanting impurity ions after Ti film deposition to amorphize the Ti film to weaken the binding force of Ti- degree of the deposition thickness thin, or the line width of thin easily to form a TiSi 2, increasing the reliability and yield of the thermal process, TiN and TiSi TiSi 2 to the initial Ti deposition thickness in a competitive reaction of the two shoes, namely sila And to provide a method of manufacturing a semiconductor device in which the side wall thickness ratio is increased to improve the process yield and the reliability of the device operation.
상기아 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device,
실리콘 반도체기판상에 Ti막을 형성하는 공정과,A step of forming a Ti film on the silicon semiconductor substrate,
상기 Ti막에 불순물 이온을 주입하여 Ti막을 비정질화시키는 공정과,Implanting impurity ions into the Ti film to amorphize the Ti film,
상기 반도체기판을 일차 열처리하여 불안정한 Ti 실리사이드막을 형성하는 공정과,Subjecting the semiconductor substrate to a first heat treatment to form an unstable Ti silicide film,
상기 반도체기판 상의 실리사이드화 되지 않은 Ti막을 제거하는 공정과,Removing the un-silicided Ti film on the semiconductor substrate;
상기 불안정한 Ti 실리사이드막을 이차 열처리하여 안정한 Ti 실리사이드막을 형성하는 공정을 구비하는 것을 특징으로 한다.And forming a stable Ti silicide film by performing a secondary heat treatment on the unstable Ti silicide film.
이하, 본 발명에 따른 반도체소자의 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제2(a)도 내지 제2(f)도는 본 발명의 실시예에 따른 반도체소자의 제조 공정도로서, MOSFET의 예이다.FIGS. 2 (a) through 2 (f) are diagrams of a process for manufacturing a semiconductor device according to an embodiment of the present invention, which is an example of a MOSFET.
먼저, N 또는 P형 반도체기판(11)상에 소자분리 영역 및 액티브 영역으로 예정되어 있는 부분에 소자분리 산화막(13)과 게이트 산화막(15)을 형성하고, 일련의 게이트전극(17)을 다결정실리콘층 패턴으로 형성한다.First, a device isolation oxide film 13 and a gate oxide film 15 are formed on an N or P type semiconductor substrate 11 at a portion scheduled to be an element isolation region and an active region. A series of gate electrodes 17 are formed in a polycrystal Silicon layer pattern.
여기서 도시되어 있지는 않으나, 상기 소자분리 산화막(13)의 형성 전후에 웰이나 채널저지층 및 문턱전압 조절을 위한 이온주입공정 등을 실시하기도 힌다.Although not shown here, a well, a channel blocking layer, and an ion implantation process for adjusting a threshold voltage may be performed before and after the formation of the device isolation oxide film 13.
그후, 상기 게이트전극(17)의 측벽에 절연막 스페이서(19)를 형성하고 비소(As) 또는 불화 붕소(BF2) 이온을 3E15/㎤ 이상의 농도를 주입하여 n+또는 p+타입의 소오스/드레인 영역(21)을 형성한다.Thereafter, an insulating film spacer 19 is formed on the sidewall of the gate electrode 17 and arsenic (As) or boron fluoride (BF 2 ) ions are implanted at a concentration of 3E15 / cm 3 or more to form n + or p + Regions 21 are formed.
이때 상기 절연막 스페이서(19)는 테오스(Tetra ethyl ortho silicate; 이하 TEOS라 칭함) 산화막의 전면 도포 및 전면 이방성식각 공정으로 형성한다. 여기서, 상기 절연막 스페이서(19)는 필요에 따라 다른 절연막, 예를들어 질화막 등으로도 형성할 수 있으며, 이온주입에 대한 손상을 방지하기 위하여 반도체기판(11)상에 잔류 산화막을 남겨 두어 손상을 방지하게 할 수도 있다(제2(a)도 참조).At this time, the insulating film spacer 19 is formed by a whole surface anisotropy etching process of a tetra ethyl ortho silicate (hereinafter referred to as TEOS) oxide film and a front anisotropic etching process. Here, the insulating film spacer 19 may be formed of another insulating film, for example, a nitride film, if necessary. In order to prevent damage to the ion implantation, a residual oxide film is left on the semiconductor substrate 11, (See also Fig. 2 (a)).
그다음 상기 구조의 전표면에 Ti막(23)을 스퍼터링 방법으로 100Å∼1000Å 정도 두께로 형성한다. 여기서 잔류 산화막이 남아 있는 경우는 잔류 산화막 제거 공정을 먼저 실시하고 Ti막(23)을 형성한다.Next, a Ti film 23 is formed on the entire surface of the structure to a thickness of about 100 Å to 1000 Å by a sputtering method. Here, if the residual oxide film remains, the residual oxide film removing step is performed first to form the Ti film 23.
그리고, 상기 Ti막(23)의 증착 조건은 스퍼터링 방법일 때 타겟으로 고순도의 Ti을 이용하여 N2(+Ar) 플라즈마 상태에서 증착압력이 종래 보다 낮은 1∼50mTorr 정도로 실시하고, 1:1 콜리메이터가 달린 장비를 이용하여 좀더 조밀한 막을 형성한다. 이때, 기판 온도는 25∼350정도가 되도록 하는데, 이는 기판 온도가 350이상일 경우 반응기 내부에서 Ti막(23)으로 산소가 침투하기 쉬워 다단계 RTP를 사용하는 공정에 적합하지 않은 단점이 있기 때문이다(제2(b)도 참조).The deposition conditions of the Ti film 23 are performed at a deposition pressure of about 1 to 50 mTorr in a N 2 (+ Ar) plasma state using Ti of high purity as a target when the sputtering method is used, To form a more dense membrane. At this time, the substrate temperature is 25 to 350 Of the substrate temperature, which is about 350 < RTI ID = 0.0 > , Oxygen tends to penetrate into the Ti film 23 in the reactor, which is not suitable for the process using multi-step RTP (see also FIG. 2 (b)).
그후, 상기 Ti막(23)을 통하여 Ge 불순물 이온을 10KeV∼60KeV의 에너지로 이온 농도가 1×1014/㎤∼5×1015/㎤로 주입하여, 상기 Ti막(23)의 일부를 비정질화시켜 비정질 Ti막(24)을 형성한다.Thereafter, an ion concentration of 1 × 10 14 / cm 3 to 5 × 10 15 / cm 3 is injected through the Ti film 23 at an energy of 10 KeV to 60 KeV, and a part of the Ti film 23 is amorphous Thereby forming an amorphous Ti film 24.
이때 상기와 같은 반도체 제조 공정에서 선 비정질화를 위해 이용하는 불순물로는 F, As, Ge 이온 등이 있으나 상기의 이온들 중 F 이온은 TiSi2의 결정질화를 억제하는 문제가 있고, As은 TiAs을 형성하여 오히려 실리사이드 반응을 억제시키는 문제가 있어, Ge 이온막이 반도체소자 제작시 고려되어야 할 여러 가지 변수에 양호한 결과를 얻을 수 있다.As impurities used for the pre-amorphization in the semiconductor manufacturing process, there are F, As, and Ge ions. However, among the ions, F ions have a problem of inhibiting the crystallization of TiSi 2 . And the silicide reaction is suppressed. Therefore, it is possible to obtain good results in various parameters to be considered in fabricating the semiconductor device.
또한 상기 이온 주입 공정시 투사 범위(Project range; 이하 Rp라 칭함)는 Ti막(23)과 반도체기판(11) 계면으로부터 투사 범위 표준 편차(이하 △Rp라 칭함) 만큼 떨어져 있도록 하여 이온 주입에 의한 손상이 Ti막(23)과 반도체기판(11)의 계면 특성을 악화시키지 않도록 한다. 이는 Ti막(23)과 반도체기판(11) 계면 근처에 Rp가 있으면 이온 주입에 의한 손상의 대부분이 계면에 존재하게 되어 후속공정으로 형성되는 Ti 실리사이드막의 막질이 떨어지고 그로인해 Ti 실리사이드막과 반도체기판(11) 간의 계면의 거칠기가 심해지고 접합 누설 전류가 증가되기 때문이다.The projection range (hereinafter referred to as Rp) during the ion implantation process is set to be apart from the interface between the Ti film 23 and the semiconductor substrate 11 by a standard deviation of projection range (hereinafter referred to as? Rp) So that the damage does not deteriorate the interface characteristics between the Ti film 23 and the semiconductor substrate 11. [ If Rp is present near the interface between the Ti film 23 and the semiconductor substrate 11, most of the damage caused by the ion implantation is present at the interface, and the film quality of the Ti silicide film formed in the subsequent process is lowered, The roughness of the interface between the semiconductor chip 11 and the junction leakage current is increased.
여기서 상기와 같은 Ge 이온주입에 의한 Ti의 비정질화를 이.에스.지.에이.티.(Enhanced Silicidation by Ge pre-Amorphized Ti ; 이하 ESGAT라 칭함) 공정이라 한다(제2(c)도 참조).Herein, the amorphization of Ti by Ge ion implantation is referred to as an ESGAT process (refer to FIG. 2 (c)) ).
그다음 상기의 Ti막(23)과 비정질 Ti층을 400∼800정도의 온도에서 10∼60초 정도의 시간동안 1차 RTP를 실시하여 소오스/드레인 영역(21)과 게이트전극(17) 위에만 C49 혹은 C54 상의 불완전한 Ti 실리사이드막(25)를 형성한다(제2(d)도 참조).Then, the Ti film (23) and the amorphous Ti layer The first RTP is performed for about 10 to about 60 seconds at a temperature of about 500 ° C. to form an incomplete Ti silicide film 25 on the C49 or C54 phase only over the source / drain region 21 and the gate electrode 17 (see also Fig.
그후, 상기의 Ti 실리사이드막(9)를 형성하지 않은 Ti막(23),(24)을 NH4OH : H2O2: H2O=1:1:5의 식각액으로 10∼60분 정도의 시간동안 선택적으로 에치하여 소오스/드레인 영역(21)과 게이트전극(17) 상부에만 Ti 실리사이드막(25)이 형성되도록 한다.Thereafter, the Ti films 23 and 24 without the Ti silicide film 9 are etched with an etching solution of NH 4 OH: H 2 O 2 : H 2 O = 1: 1: 5 for 10 to 60 minutes So that the Ti silicide film 25 is formed only over the source / drain regions 21 and the gate electrode 17. [
그다음 상기의 C49 혹은 C54 상의 불안정한 Ti 실리사이드막(25)을 700∼1000정도의 온도에서 10∼60초 정도 2차 RTP을 실시하여 모두 저저항의 C54상으로 안정된 Ti 실리사이드막(25)으로 상전이 시킨다(제2(e)도 참조).The unstable Ti silicide film (25) on the above C49 or C54 phase is then etched to 700 to 1000 (See Fig. 2 (e)). The second RTP is carried out for about 10 to about 60 seconds at a temperature of about 200 캜 and at a temperature of about 200 캜.
그후, 상기 구조의 전표면에 층간 절연막(27)을 소정 두께, 예를들어 5000∼10000Å 정도 두께로 도포하고, 700∼1000정도의 온도에서 10∼60분 정도 열처리하여 평탄화시킨 후, 콘택홀(29)을 오픈한 후에 기존의 반도체공정 그대로 후속 공정을 진행한다(제2(f)도 참조).Thereafter, an interlayer insulating film 27 is applied to the entire surface of the structure to a predetermined thickness, for example, about 5000 to 10000 angstroms, After the contact hole 29 is opened, a subsequent semiconductor process is carried out as a subsequent process (see also FIG. 2 (f)).
상기에서는 MOS FET에서 게이트전극과 소오스/드레인 영역 상에 Ti 실리사이드막을 형성하는 공정을 예로 들었으나, 다른 Ti 실리사이드막 형성 공정에서도 사용할 수 있다. 예를들어 워드선에만 형성하거나, Si/Ti/TiN/Al의 콘택 구조에서 콘택 저항이 커지는 것을 방지하기 위하여 본 발명의 사상을 적용할 수 있음은 물론이다.In the above, the process of forming a Ti silicide film on the gate electrode and the source / drain region in the MOS FET is taken as an example, but it can also be used in other Ti silicide film formation processes. For example, it is needless to say that the concept of the present invention can be applied to form only the word line or prevent the contact resistance from increasing in the contact structure of Si / Ti / TiN / Al.
상기에서 게이트전극을 다결정실리콘층으로 형성하였으나, 비정질 실리콘으로 형성한 후에 별도의 열처리 공정시 다결정화 되도록 할 수도 있다.Although the gate electrode is formed of a polycrystalline silicon layer in the above description, it may be polycrystallized in a separate heat treatment process after the amorphous silicon layer is formed.
이상에서 설명한 바와같이, 본 발명에 따른 반도체소자의 제조방법은 실리콘 기판 상에 Ti막을 형성하고, 상기 Ti막을 Ge 이온을 주입하여 선 비정질화 시킨 후에 일차 열처리하여 C49상과 C54상의 불안정한 Ti 실리사이드막을 형성하며, 상기에서 실리사이드화되지 않은 Ti막을 제거한 후, 이차로 열처리하여 안정된 C54상의 Ti 실리사이드막을 형성하였으므로, 1차 RTA 온도가 낮거나 Ti막의 증착 두께가 얇거나, 또는 선폭이 가늘어도 쉽게 Ti 실리사이드막을 형성할 수 있도록 하여 열 공정의 신뢰성 및 수율을 높이고, TiN과 TiSi2의 경쟁적 반응에서 초기 Ti 증착 두께에 대한 TiSi2화하는 두께 비가 높게 되어 공정비율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a Ti film is formed on a silicon substrate, the Ti film is doped with Ge ions to be amorphized, and then subjected to a primary heat treatment to form an unstable Ti silicide film on C49 phase and C54 phase The Ti silicide film on the C54 phase is formed by the second heat treatment after removing the un-silicided Ti film, so that the TiSi film can be easily formed even if the first RTA temperature is low, the Ti film is thin or the line width is small. The reliability and yield of the thermal process can be increased and the thickness ratio of TiSi 2 to the initial Ti deposition thickness can be increased in the competitive reaction of TiN and TiSi 2 to improve the reliability of the process ratio and device operation .
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