KR100208634B1 - 표면 실장형 반도체 장치 - Google Patents
표면 실장형 반도체 장치 Download PDFInfo
- Publication number
- KR100208634B1 KR100208634B1 KR1019940030738A KR19940030738A KR100208634B1 KR 100208634 B1 KR100208634 B1 KR 100208634B1 KR 1019940030738 A KR1019940030738 A KR 1019940030738A KR 19940030738 A KR19940030738 A KR 19940030738A KR 100208634 B1 KR100208634 B1 KR 100208634B1
- Authority
- KR
- South Korea
- Prior art keywords
- lead
- resin
- thick portion
- semiconductor device
- thick
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP93-295721 | 1993-11-25 | ||
JP29572193A JP2902919B2 (ja) | 1993-11-25 | 1993-11-25 | 表面実装型半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR100208634B1 true KR100208634B1 (ko) | 1999-07-15 |
Family
ID=17824308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940030738A KR100208634B1 (ko) | 1993-11-25 | 1994-11-22 | 표면 실장형 반도체 장치 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2902919B2 (ja) |
KR (1) | KR100208634B1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007184643A (ja) * | 2007-03-28 | 2007-07-19 | Toshiba Electronic Engineering Corp | 光半導体パッケージ |
JP5667820B2 (ja) * | 2010-09-14 | 2015-02-12 | 東芝電子エンジニアリング株式会社 | 光半導体装置 |
JP5580723B2 (ja) * | 2010-12-11 | 2014-08-27 | エンゼル工業株式会社 | 被覆ダイオードと太陽電池モジュール用端子ボックス |
JP5410465B2 (ja) * | 2011-02-24 | 2014-02-05 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
US9190606B2 (en) * | 2013-03-15 | 2015-11-17 | Allegro Micosystems, LLC | Packaging for an electronic device |
US10345343B2 (en) | 2013-03-15 | 2019-07-09 | Allegro Microsystems, Llc | Current sensor isolation |
JP5740458B2 (ja) * | 2013-12-02 | 2015-06-24 | 東芝電子エンジニアリング株式会社 | 光半導体パッケージ |
US11768230B1 (en) | 2022-03-30 | 2023-09-26 | Allegro Microsystems, Llc | Current sensor integrated circuit with a dual gauge lead frame |
-
1993
- 1993-11-25 JP JP29572193A patent/JP2902919B2/ja not_active Expired - Lifetime
-
1994
- 1994-11-22 KR KR1019940030738A patent/KR100208634B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP2902919B2 (ja) | 1999-06-07 |
JPH07147360A (ja) | 1995-06-06 |
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Date | Code | Title | Description |
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20120329 Year of fee payment: 14 |
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FPAY | Annual fee payment |
Payment date: 20130329 Year of fee payment: 15 |
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LAPS | Lapse due to unpaid annual fee |