KR100203382B1 - Thin film transistor array substrate and manufacturing method thereof - Google Patents
Thin film transistor array substrate and manufacturing method thereof Download PDFInfo
- Publication number
- KR100203382B1 KR100203382B1 KR1019960034340A KR19960034340A KR100203382B1 KR 100203382 B1 KR100203382 B1 KR 100203382B1 KR 1019960034340 A KR1019960034340 A KR 1019960034340A KR 19960034340 A KR19960034340 A KR 19960034340A KR 100203382 B1 KR100203382 B1 KR 100203382B1
- Authority
- KR
- South Korea
- Prior art keywords
- electrode
- signal line
- semiconductor layer
- source electrode
- thin film
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 49
- 239000010409 thin film Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 81
- 239000011241 protective layer Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 239000011521 glass Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
액정표시소자의 박막트랜지스터 어레이기판은 소스전극 및 신호선의 아래의 반도체층이 테이퍼형상으로 에칭되어 소스전극 및 신호선의 안쪽에서 바깥쪽으로 점점 경사지는 형상으로 형성되어 있다. 게이트절연층 위에 형성되는 화소전극은 소스전극 및 신호선 아래에서 그 두께가 점점 얇아져 반도체층의 테이퍼면의 일부와 겹치게 되어 박막트랜지스터와 화소전극 및 신호선과 화소 전극 사이의 간격이 거의 없어지게 되어 개구율이 향상된다.The thin film transistor array substrate of the liquid crystal display device is formed in such a manner that the semiconductor layers below the source electrode and the signal line are etched in a tapered shape and gradually inclined from the inside of the source electrode and the signal line to the outside. The pixel electrode formed on the gate insulating layer becomes thinner and thinner under the source electrode and the signal line to overlap with a part of the tapered surface of the semiconductor layer, so that the gap between the thin film transistor and the pixel electrode and the signal line and the pixel electrode is almost eliminated. Is improved.
Description
텔레비젼이나 퍼스널컴퓨터의 표시장치에 주로 사용되고 있는 CRT(cathod ray tube)는 대면적의 화면을 만들 수 있다는 장점이 있지만, 이러한 대면적의 화면을 만들기 위해서는 전자총(electron gun)과 발광물질이 도포된 스크린과의 거리가 일정 이상을 유지해야만 하기 때문에 그 부피가 커지는 문제가 있었다. 따라서, CRT는 현재 활발하게 연구되고 있는 벽걸이용 텔레비젼 등에 적용할 수 없을 뿐만 아니라, 근래에 주목받고 있는 휴대용 텔레비젼이나 노트북 컴퓨터 등과 같이 저전력을 필요로 하며 소형화를 요구하는 전자 제품에도 적용할 수가 없었다.The CRT (cathod ray tube), which is mainly used for display devices of televisions and personal computers, has the advantage of making a large area screen, but in order to make such a large area screen, an electron gun and a screen coated with a light emitting material Because the distance between the and must maintain a certain amount, there was a problem that the volume becomes large. Therefore, the CRT is not only applicable to wall-mounted televisions, which are currently being actively researched, but also to electronic products requiring low power and requiring miniaturization, such as portable TVs and notebook computers, which are attracting attention in recent years.
이러한 표시장치의 요구에 부응하여 LCD(liquid crystal display), PDP(plasma display panel), ELD(electroluminescent display), VFD(vacuum fluorescent display)와 같은 여러 가지의 평판표시장치가 연구되고 있지만, 그중에서도 LCD(액정표시장치)가 여러 가지의 단점에도 불구하고 화질이 우수하며 저전력을 사용한다는 점에서 근래에 가장 활발하게 연구되고 있다. 이러한 LCD로는 단순매트릭스(passive matrix) 구동방식 LCD와 액티브매트릭스(active matrix) 구동방식 LCD와 액티브매트릭스(actrive matrix) 구동방식 LCD가 있는데, 이 중에서도 AMLCD가 각각의 화소를 독립적으로 구동시킴으로써, 인접화소의 데이터신호에 의한 영향을 최소화시켜서 콘드라스트비(contrast ratio)를 높이면서 주사선수를 증가시킬 수 있기 때문에 근래의 LCD에 주로 사용되고 있다.In response to the needs of such display devices, various flat panel display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), electroluminescent displays (ELDs), and vacuum fluorescent displays (VFDs) have been studied. In spite of various drawbacks, liquid crystal displays have been researched most recently in that they have excellent image quality and use low power. Such LCDs include passive matrix drive LCDs, active matrix drive LCDs, and active matrix drive LCDs. Since it is possible to increase the number of injection players while increasing the contrast ratio by minimizing the influence of the data signal, it is mainly used in modern LCDs.
도 1은 일반적인 LCD의 TFT 어래이기판을 나타내는 도면으로서, 설명의 편의를 위하여 상기한 도면에서는 LCD에 형성된 수많은 화소중 한 화소만을 나타내었다. 도면에 나타낸 바와 같이, 화소 영역은 종횡으로 배열된 신호선(11) 및 주사선(12)에 의해 정의된다. 화소영역내의 신호선(11)과 주사선(12)의 교차점에는 게이트전극(14)이 주사선(12)에 연결되고 소스전극(13a)이 신호선(11)에 연결된 TFT가 형성되어 있다. 화소전극(15)은 화소영역내에 적층되어 TFT의 드레인전극(13b)에 접속된다.FIG. 1 is a view illustrating a TFT array board of a general LCD. For the convenience of description, only one pixel among a large number of pixels formed in the LCD is shown. As shown in the figure, the pixel region is defined by the signal lines 11 and the scanning lines 12 arranged vertically and horizontally. At the intersection of the signal line 11 and the scan line 12 in the pixel region, a TFT in which the gate electrode 14 is connected to the scan line 12 and the source electrode 13a is connected to the signal line 11 is formed. The pixel electrode 15 is stacked in the pixel region and connected to the drain electrode 13b of the TFT.
도 2는 상기한 도 1의 A-A' 선 단면도로서, 종래의 TFT 어레이기판을 나타낸다. 기판(10)위에는 게이트전극(14)이 형성되어 있으며, 상기한 게이트전극(14) 및 기판(10)위에 게이트절연층(16)이 형성된다. 비정질 실리콘(a-Si)으로 이루어진 반도체층(18)은 게이트절연층(16)을 사이에 두고 게이트전극(14)위에 배치되어 채널층(channel layer)을 형성하며, 그 위의 양쪽에 소스전극(13a)과 드레인전극(b)이 형성된다. 도면에는 나타내지 않았지만, 소스전극(13a) 및 드레인전극(13b)과 반도체층(18) 사이에는 n+층이 적층되어 오우믹컨캑트층(ohmic contact layer)을 형성한다. 화소전극(15)은 화소 영역에 형성되는데, 드레인전극(13b)과 전기적으로 접속되기 위해 상기한 드레인전극(131b)과 오버랩(over lap)되어 있다. 이 화소전극(15)은 ITO(indium tin oxide) 와 같은 투명한 물질로서, 이러한 구조를 탑(top) ITO 구조라 한다. 상기한 화소전극(15), TFT위에 보호막(20)이 적층되어 TFT 어레이기판이 완성된다.FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1 and shows a conventional TFT array substrate. The gate electrode 14 is formed on the substrate 10, and the gate insulating layer 16 is formed on the gate electrode 14 and the substrate 10. The semiconductor layer 18 made of amorphous silicon (a-Si) is disposed on the gate electrode 14 with the gate insulating layer 16 therebetween to form a channel layer, and source electrodes on both sides thereof. 13a and the drain electrode b are formed. Although not shown in the figure, an n + layer is stacked between the source electrode 13a and the drain electrode 13b and the semiconductor layer 18 to form an ohmic contact layer. The pixel electrode 15 is formed in the pixel region, and overlaps the drain electrode 131b to be electrically connected to the drain electrode 13b. The pixel electrode 15 is a transparent material such as indium tin oxide (ITO), and this structure is called a top ITO structure. The protective film 20 is stacked on the pixel electrode 15 and the TFT to complete the TFT array substrate.
상기한 구조의 TFT 어레이기판이 LCD에 적용되었을 때 수 많은 화소가 액정패널(liquid pannel)에 형성되며, 각각의 화소가 액정패널의 외부에 부착된 외부구동회로부의 신호에 의해 작동하게 된다. 즉, 주사선(14)에 외부구동회로로부터 전압이 인가되면, TFT가 턴온됨과 동시에 신호선(11)으로 입력된 신호가 FTF를 통해 화소전극(15)에 인가된다. 이 신호가 TFT 어레이기판과 대향전극 및 컬러필터층(color filter layer)이 형성되어 있는 컬러필터기판 사이의 액정층에 인가되어 상기한 액정층을 투과하는 빛의 양을 제어함으로써 원하는 화상을 얻게 된다.When the TFT array substrate having the above structure is applied to an LCD, a number of pixels are formed in a liquid pannel, and each pixel is operated by a signal of an external driving circuit portion attached to the outside of the liquid crystal panel. That is, when a voltage is applied to the scan line 14 from the external driving circuit, the TFT is turned on and the signal input to the signal line 11 is applied to the pixel electrode 15 through the FTF. This signal is applied to the liquid crystal layer between the TFT array substrate, the counter electrode and the color filter substrate on which the color filter layer is formed, thereby controlling the amount of light passing through the liquid crystal layer to obtain a desired image.
LCD에서 실제로 화상이 나타나는 영역은 화소전극(15)이 형성되어 있는 영역이다. 그러나, 도면에 나타낸 바와 같이 화소전극(15)이 소스전극(13a) 과의 단락을 방지하기 위해 소스전극(13a) 과 일정한 간격( t1)을 두고 형성되기 때문에 실제의 영역은 화소영역 보다 작게 되어 개구율이 저하된다.The area where the image actually appears in the LCD is the area where the pixel electrode 15 is formed. However, as shown in the drawing, since the pixel electrode 15 is formed at a predetermined distance t1 from the source electrode 13a to prevent a short circuit with the source electrode 13a, the actual area becomes smaller than the pixel area. The aperture ratio is lowered.
더욱이, 상기한 간격(t1) 으로의 빛의 누설은 LCD의 화질을 저하시키는 결정적인 요인이 되기 때문에, TFT 어레이기판이나 컬러필터기판에 차광층을 형성하여 빛의 누설을 방지해야만 하지만, 이 차광층은 빛의 누설을 완전히 차단하기 위해 화소전극(15)의 일부와 겹치게 되어 LCD의 개구율이 더욱 저하될 뿐만 아니라, 상기한 차광층 영역으로 빛이 투과되지 않기 때문에, 화면이 어두워 진다.Furthermore, since light leakage at the above interval t1 is a decisive factor for degrading the image quality of the LCD, a light shielding layer must be formed on a TFT array substrate or a color filter substrate to prevent light leakage. The silver overlaps with a part of the pixel electrode 15 to completely block the leakage of light, and not only the aperture ratio of the LCD is further lowered, but also the light is not transmitted to the light shielding layer area, thereby darkening the screen.
이러한 현상은 TFT에서 뿐만 아니라, 도 3의 신호선(11)에서도 마찬가지다. 오히려, 신호선(11) 영역에서는 신호선(11) 양측면에 간격(t2)이 생기기 때문에 2t2만큼의 영역으로 빛이 누설되기 때문에, 개구율이 더욱 저하되고 화면의 밝기 역시 더욱 나빠진다.This phenomenon is the same not only in the TFT but also in the signal line 11 of FIG. On the contrary, in the area of the signal line 11, since the gap t 2 is formed on both sides of the signal line 11, light leaks into the area of 2t 2 , so that the aperture ratio is further lowered and the brightness of the screen is further worsened.
본 발명은 상기한 점을 감안하여 이루어진 것으로, 화소전극과 박막트랜지스터 및 화소전극과 신호선의 간격을 줄임으로써 개구율이 향상된 액정표시소자의 박막트랜지스터 어레이기판 및 그 제조방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and an object thereof is to provide a thin film transistor array substrate of a liquid crystal display device having an improved aperture ratio by reducing the distance between the pixel electrode, the thin film transistor, and the pixel electrode and the signal line.
상기한 목적을 달성하기 위해, 본 발명에 따른 액정표시소자의 박막트랜지스터 어레이기판은 투명한 유리기판과, 기판 위에 형성된 게이트전극 및 주사선과, 게이트 전극 위에 적층된 게이트절연층과, 게이트절연층 위에 소스전극과 신호선의 밑면의 일부와 접한 상태에서 기판쪽으로 갈수록 완만하게 경사지는 테이퍼형상의 반도체층과, 상기한 반도체층 위에 형성된 소스전극과 드레인전극 및 신호선과, 게이트절연층 위에 적층된 화소전극과, 기판 전체에 걸쳐서 적층된 보호층으로 구성된다.In order to achieve the above object, a thin film transistor array substrate of a liquid crystal display device according to the present invention is a transparent glass substrate, a gate electrode and a scan line formed on the substrate, a gate insulating layer stacked on the gate electrode, a source on the gate insulating layer A tapered semiconductor layer gradually inclined toward the substrate in contact with a portion of the bottom surface of the electrode and the signal line, a source electrode, a drain electrode and a signal line formed on the semiconductor layer, a pixel electrode stacked on the gate insulating layer, It consists of a protective layer laminated over the whole substrate.
화소전극은 소스전극과 신호선의 양측면 중 적어도 한쪽의 밑면에 테이퍼형상으로 형성된 반도체층의 경사면까지 형성되어 화소전극과 소스전극 및 화소전극과 신호선 사이의 간격이 감소된다.The pixel electrode is formed up to an inclined surface of the semiconductor layer formed in a tapered shape on at least one of both side surfaces of the source electrode and the signal line, thereby reducing the distance between the pixel electrode and the source electrode and the pixel electrode and the signal line.
화소전극 위에 보호층이 적층되어 있는 대신에, 보호층 위에 화소 적극이 형성되어 있는 구조도 가능하다. 이때, 화소전극과 소스/드레인전극은 보호층이 형성된 컨택트홀을 통해 전기적으로 접속된다.Instead of the protective layer being laminated on the pixel electrode, a structure in which the pixel positive electrode is formed on the protective layer is also possible. In this case, the pixel electrode and the source / drain electrode are electrically connected through the contact hole in which the protective layer is formed.
제1도는 종래의 액정표시소자의 평면도1 is a plan view of a conventional liquid crystal display device
제2도는 제1도의 A-A' 선 단면도.2 is a cross-sectional view taken along the line A-A 'of FIG.
제3도는 제1도의 B-B'선 단면도.3 is a cross-sectional view taken along the line B-B 'of FIG.
제4도는 본 발명의 일실시예에 따른 액정표시소자의 제조 공종을 나타내는 도면.4 is a view showing a manufacturing model of the liquid crystal display device according to an embodiment of the present invention.
제5도는 제1도의 B-B'선 단면도.5 is a cross-sectional view taken along the line B-B 'of FIG.
제6도는 제5도의 D부분 확대도.6 is an enlarged view of portion D of FIG.
제7도는 본 발명의 다른 실시예에 따른 액정표시소자의 박막트랜지스터 어레이기판을 나타내는 도면.7 is a view showing a thin film transistor array substrate of a liquid crystal display device according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
100 : 유리기판 111 : 신호선100: glass substrate 111: signal line
113 : 금속층 113a : 소스전극113: metal layer 113a: source electrode
113b : 드레인 전극 114 : 주사선113b: drain electrode 114: scanning line
115 : 화소전극 116 : 게이트절연층115: pixel electrode 116: gate insulating layer
118 : 반도체층 120 : 보호층118: semiconductor layer 120: protective layer
130 : 포토레지스트130: photoresist
이하, 첨부한 도면을 참조하여 본 발명에 따른 LCD의 TFT어레이기판에 대하여 상세히 설명한다.Hereinafter, a TFT array substrate of an LCD according to the present invention will be described in detail with reference to the accompanying drawings.
도 4는 본 발명에 따른 TFT 어레이기판의 제조방법을 나타내는 도면이다. 우선, 도 4(a)에 나타낸 바와 같이 투명한 유리기판(100) 위에 Cr, Mo, Al 또는 Al합금을 스퍼터링(sputtering)방법으로 적층하고 포토에칭하여 케이트전극(114)을 형성한다. 그후, 도 4(b)에 나타낸 바와 같이 기판(100) 및 게이트 전극(114) 위에 게이트절연층(116), 반도체층(118a) 및 금속층(113)을 연속 적층한다. 게이트절연층(116)은 SiNx층이나 SiO₂층으로 플라즈마 CVD(plasma chemical vapar deposition) 방법에 의해 적층되며, 반도체층(118a)도 역시 비정질실리콘(a-Si)을 플라즈마 CVD방법으로 적층하여 형성한다. 또한, 금속층(113)은 Al이나 Al합금을 스퍼터링방법으로 적층함으로써 형성된다.4 is a view showing a method of manufacturing a TFT array substrate according to the present invention. First, as shown in FIG. 4A, Cr, Mo, Al, or Al alloys are laminated on a transparent glass substrate 100 by sputtering, and photoetched to form a gate electrode 114. Thereafter, as shown in FIG. 4B, the gate insulating layer 116, the semiconductor layer 118a, and the metal layer 113 are successively stacked on the substrate 100 and the gate electrode 114. The gate insulating layer 116 is laminated by a SiNx layer or SiO2 layer by plasma chemical vapor deposition (CVD), and the semiconductor layer 118a is also formed by laminating amorphous silicon (a-Si) by plasma CVD. . In addition, the metal layer 113 is formed by laminating Al or Al alloy by the sputtering method.
이어서, 도 4(c)에 나타낸 바와 같이 상기한 금속층(113)을 포토에칭하여 소스전극(113a) 및 드레인전극(113b) 을 형성한 후, 도 4(d)에 나타낸 바와 같이 포토레지스트(photoresist;130)를 도포한 상태에서 반도체층(118)을 에칭한다. 이때, 포토레지스트(130)를 드레인전극(113b)은 완전히 덮고 있고 소스전극(113a)은 중간 정도까지만 덮도록 한 후에 등방성에칭(isotropic etching)을 실시하면, 드레인 전극(113b)쪽의 반도체층(118)은 포토레지스트에 의해 상기한 드레인전극(113b) 보다 더 큰 폭으로 되며, 소스전극(113a)쪽의 반도체층(118)은 소스전극(113a)에 의해 블로킹된 아래의 반도체층(118) 아래까지 일부에칭 된다. 따라서, 도면에 나타낸 바와 같이 소스전극(113a) 아래의 반도체층(118)은 소스전극(113a)의 밑면에서부터 게이트절연층(116)으로 갈수록 서서히 폭이 커지는 완만한 형태로 경사지게 된다.Subsequently, as shown in FIG. 4C, the metal layer 113 is photoetched to form a source electrode 113a and a drain electrode 113b, and then a photoresist as shown in FIG. 4D. The semiconductor layer 118 is etched while the 130 is coated. At this time, if the photoresist 130 is completely covered with the drain electrode 113b and the source electrode 113a is covered only to the middle, and isotropic etching is performed, the semiconductor layer (the side of the drain electrode 113b) 118 is larger than the drain electrode 113b by the photoresist, and the semiconductor layer 118 on the side of the source electrode 113a is blocked by the source electrode 113a. Some are etched down. Therefore, as shown in the figure, the semiconductor layer 118 under the source electrode 113a is inclined in a gentle shape gradually increasing in width from the bottom of the source electrode 113a to the gate insulating layer 116.
그 후, 도 4(e)에 나타낸 바와 같이 포토레지스트를 제거한 후, 기판(100) 전체에 걸쳐서 ITO와 같은 투명전극을 스퍼터링방법으로 적층하고 포토에칭하여 화소전극(115)은 상기한 드레인전극(113b)과 일부가 오버랩되어 전기적으로 접속된다. 한편, 인접 화소(도면에서 소스전극의 왼쪽)에서는 ITO의 적층이 소스전극(113a)에 의해 방해받기 때문에, 소스전극(113a)까지는 일정한 두께를 유지하다가 소스전극(113a) 아래에서부터 점차 그 두께가 작아진다. 결국, 화소전극(115)이 소스전극(113a) 아래의 테이퍼경사면까지 형성되지만, 그 두께가 작기 때문에, 소스전극(113a)과는 단락되는 일이 없게 된다. 이어서, SiNx나 SiO₂ 등의 절연물질을 적층하여 보호층(120)을 형성한다.Thereafter, as shown in FIG. 4E, after removing the photoresist, a transparent electrode such as ITO is stacked on the entire substrate 100 by sputtering and photoetched to thereby etch the pixel electrode 115. A part of 113b) overlaps and is electrically connected. On the other hand, in the adjacent pixels (the left side of the source electrode in the drawing), since the stacking of ITO is disturbed by the source electrode 113a, the thickness of the source electrode 113a remains constant until the thickness of the source electrode 113a gradually increases from below the source electrode 113a. Becomes smaller. As a result, although the pixel electrode 115 is formed to the tapered slope below the source electrode 113a, since the thickness is small, the pixel electrode 115 is not shorted with the source electrode 113a. Subsequently, an insulating material such as SiNx or SiO 2 is stacked to form the protective layer 120.
다음에, 도 4(e)를 참조하여 TFT 어레이기판의 구조를 상세히 설명한다. 이때의 TFT 어레이기판은 탑ITO 구조로서, 도 1 및 도 2에 나타낸 종래의 어레이기판과는 반도체층만 다를 뿐 다른 모든 구조는 동일하다. 따라서, 그 평면도는 종래와 동일하므로 설명의 편의를 위해 도 4(e)를 도 1의 A-A'선 단면도로서 설명한다. 이것은 도 1의 B-B'선 단면도인 도 5에도 적용된다.Next, the structure of the TFT array substrate will be described in detail with reference to Fig. 4E. At this time, the TFT array substrate has a top ITO structure, and all other structures are the same except that the semiconductor layer is different from the conventional array substrate shown in FIGS. 1 and 2. Therefore, the plan view is the same as the conventional one, and for convenience of description, FIG. This also applies to FIG. 5, which is a cross-sectional view taken along line B-B 'of FIG. 1.
도면에 나타낸 바와 같이, 기판(100) 위에는 게이트전극(114)이 형성되어 있고, 그 위에 게이트절연층(116)이 형성되어 있다. 게이트절연층(116) 위에는 a-Si로 이루어진 반도체층(118)이 형성되어 있고, 상기한 반도체층(118)의 양측면에 소스전극(113a) 및 드레인전극(113b)이 형성되어 있으며, 그 위에 보호층(120)이 적층되어 있다. 드레인전극(113b) 아래의 반도체층(118)은 드레인 전극(113b) 보다 넓은 폭으로 형성되어 상기한 트레인 전극(113b)이 완전히 반도체층(118) 위에 형성된다. 소스전극(113a) 아래의 반도체층(118)은 등방성 에칭에 의해 소스전극(113a)의 밑면에서부터 게이트절연층(116)으로 갈수록 완만하게 소스전극(113a)의 바깥쪽으로 경사지는 테이퍼형상으로 된다.As shown in the figure, a gate electrode 114 is formed on the substrate 100, and a gate insulating layer 116 is formed thereon. A semiconductor layer 118 made of a-Si is formed on the gate insulating layer 116, and source and drain electrodes 113a and 113b are formed on both sides of the semiconductor layer 118. The protective layer 120 is laminated. The semiconductor layer 118 under the drain electrode 113b is formed to have a wider width than the drain electrode 113b so that the above-described train electrode 113b is completely formed over the semiconductor layer 118. The semiconductor layer 118 under the source electrode 113a is tapered in an outward direction of the source electrode 113a from the bottom of the source electrode 113a to the gate insulating layer 116 by isotropic etching.
따라서, 화소영역에서는 화소전극(115) 이 드레인전극(113b)과는 겹치게되고, 인접 화소영역에서는 화소전극(115)이 소스전극(113a) 아래에 형성된 반도체층(118)의 테이퍼경사면까지 두께가 서서히 작아지는 형상으로 적층된다.Therefore, in the pixel region, the pixel electrode 115 overlaps the drain electrode 113b, and in the adjacent pixel region, the pixel electrode 115 has a thickness up to the tapered slope of the semiconductor layer 118 formed under the source electrode 113a. It is laminated in a shape that gradually decreases.
따라서, 인접화소, 즉 소스전극(113a)쪽에서는 화소전극(115)이 소스전극(113a) 아래의 테이퍼경사면까지 형성되어 소스전극(113a)과 화소전극(115) 사이의 간격(t3)이 거의 0으로 된다. 이것은 액정분자가 작동하는 범위, 즉 화상이 실제로 제공되는 영역이 그만큼 커진다는 것을 의미한다.Therefore, in the adjacent pixel, that is, the source electrode 113a side, the pixel electrode 115 is formed up to the tapered slope below the source electrode 113a, so that the distance t3 between the source electrode 113a and the pixel electrode 115 is substantially reduced. It becomes zero. This means that the range in which the liquid crystal molecules operate, i.e., the area where the image is actually provided, becomes large.
이러한 현상은 도 5에 나타낸 신호선(111)에서도 마찬가지이다. 신호선(111)은 TFT의 반도체층(118a)의 에칭공정시 TFT의 소스전극(113a)쪽의 에칭과 마찬가지로 금속층에 의해 등방성에칭되어, 도 6에 나타낸 바와 같이 화소전극(115)이 신호선(111) 아래에 형성된다. 이때, 상기한 현상은 신호선(111)의 양 측면에 발생하기 때문에, 신호선(111)과 화소전극(115) 사이의 간격(t4)이 거의 0으로 된다. 따라서, 화상의 실제로 제공되는 영역, 즉 개구율이 향상될 뿐만 아니라 빛이 차단되는 영역이 감소하므로 화면의 밝기가 향상된다.This phenomenon also applies to the signal line 111 shown in FIG. The signal line 111 is isotropically etched by the metal layer in the same manner as the etching of the source electrode 113a of the TFT during the etching process of the semiconductor layer 118a of the TFT, and the pixel electrode 115 is formed by the signal line 111 as shown in FIG. Is formed below. At this time, the above phenomenon occurs on both sides of the signal line 111, so that the interval t4 between the signal line 111 and the pixel electrode 115 becomes almost zero. Therefore, the area actually provided in the image, that is, the aperture ratio is improved, as well as the area in which light is blocked, thereby reducing the brightness of the screen.
도 7은 본 발명의 다른 실시예에 따른 LCD의 TFT 어레이기판의 단면도로서, IOP(ITO on passivation)구조를 나타낸다. 이 구조가 탑ITO 구조와 다른점은 화소전극(115)이 보호층(120) 위에 형성되어 있다는 것이다. 따라서, 소스전극(113a) 아래의 절연층(116)에는 보호층(120)이 반도체층(118)의 테이퍼 경사면까지 보통 보다 얇은 두께로 적층되고, 그위에 역시 얇은 두께로 화소전극(115)이 적층된다. 이 때에도, 소스전극(113a) 아래의 보호층(120)과 화소 전극(115)의 두께가 매우 작기 때문에 소스전극(113a)과 일정한 거리를 두고 절연된다. 또한, 드레인전극(113b) 과 화소전극(115)의 연결은 보호층(120)에 형성된 컨택트홀(contact hole)을 통해 이루어 진다. 따라서, 이러한 IOP구조의 어레이기판도 탑ITO구조의 어레이기판과 동일한 작용 및 효과를 얻을 수 있다.7 is a cross-sectional view of a TFT array substrate of an LCD according to another embodiment of the present invention, showing an IOP (ITO on passivation) structure. The difference between the structure and the top ITO structure is that the pixel electrode 115 is formed on the passivation layer 120. Accordingly, the protective layer 120 is laminated on the insulating layer 116 under the source electrode 113a to a taper inclined surface of the semiconductor layer 118 to a thickness thinner than usual, and the pixel electrode 115 is also thinned thereon. Are stacked. In this case, since the thickness of the protective layer 120 and the pixel electrode 115 under the source electrode 113a is very small, the insulating layer is insulated from the source electrode 113a at a certain distance. In addition, the drain electrode 113b and the pixel electrode 115 are connected to each other through a contact hole formed in the protective layer 120. Therefore, such an array substrate of the IOP structure can also obtain the same operation and effect as the array substrate of the top ITO structure.
본 발명은 상기한 바와 같이 소스전극 및 신호선 아래의 반도체층을 등방성에칭함으로써 화소전극을 소스전극 및 신호선 아래에 두께가 얇은 층으로 형성하기 때문에, 액정표시소자에서 빛이 누설되는 영역인 화소 전극과 소스전극 사이 및 화소전극과 신호선 사이의 간격을 감소시킬 수 있게 된다. 따라서, 개구율이 증대되며 화면의 밝기가 향상된 액정표시소자를 얻을 수 있게 된다.According to the present invention, since the pixel electrode is formed as a thin layer under the source electrode and the signal line by isotropically etching the semiconductor layer under the source electrode and the signal line, the pixel electrode is a region where light leaks from the liquid crystal display device. The distance between the source electrode and the pixel electrode and the signal line can be reduced. Therefore, it is possible to obtain a liquid crystal display device having an increased aperture ratio and improved screen brightness.
Claims (16)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960034340A KR100203382B1 (en) | 1996-08-20 | 1996-08-20 | Thin film transistor array substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960034340A KR100203382B1 (en) | 1996-08-20 | 1996-08-20 | Thin film transistor array substrate and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980015109A KR19980015109A (en) | 1998-05-25 |
| KR100203382B1 true KR100203382B1 (en) | 1999-07-01 |
Family
ID=19470013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960034340A KR100203382B1 (en) | 1996-08-20 | 1996-08-20 | Thin film transistor array substrate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100203382B1 (en) |
-
1996
- 1996-08-20 KR KR1019960034340A patent/KR100203382B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980015109A (en) | 1998-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100241287B1 (en) | A method for fabricating liquid crystal display device | |
| US8362491B2 (en) | Liquid crystal display device and method for fabricating the same | |
| JPS6045219A (en) | Active matrix type display device | |
| US5874326A (en) | Method for fabricating thin film transistor | |
| US7671931B2 (en) | Liquid crystal display device and method of fabricating the same | |
| JPH1010548A (en) | Active matrix substrate and its production | |
| JPH0814669B2 (en) | Matrix type display device | |
| JPH08328040A (en) | Active-matrix liquid-crystal display device | |
| KR100333179B1 (en) | Thin film transistor liquid crystal display device and manufacturing method thereof | |
| US6654094B2 (en) | Method of fabricating a liquid crystal display with redundant interconnections | |
| KR20070002748A (en) | Lipuid crystal display device and method for fabricating the same | |
| JPH10268357A (en) | Liquid crystal display device | |
| US6307611B1 (en) | Method for manufacturing pixel electrodes of liquid crystal display | |
| US20050030464A1 (en) | LCD display of slim frame structure | |
| KR100203382B1 (en) | Thin film transistor array substrate and manufacturing method thereof | |
| KR100202224B1 (en) | Thin film transistors and manufacturing method thereof | |
| KR100308155B1 (en) | A liquid crystal display device and a method of fabricating thereof | |
| KR100205258B1 (en) | Thin film transistor array substrate and its manufacturing method of liquid crystal display element | |
| KR100284810B1 (en) | Liquid Crystal Display and Method Thereof | |
| US6844901B2 (en) | Liquid crystal display device and method of manufacturing the same | |
| KR20000003169A (en) | Capacitor having assist capacitance of liquid crystal display element and forming method of the same | |
| KR20030062592A (en) | Thin film transistor substrate for liquid crystal display (LCD) and Method of manufacturing the same | |
| KR100466393B1 (en) | Thin film transistor liquid crystal display | |
| JPH0926584A (en) | Dry etching method of transparent conductive film | |
| KR100923674B1 (en) | A liquid crystal display device having sufficient storage capacitance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20121228 Year of fee payment: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20131227 Year of fee payment: 16 |
|
| FPAY | Annual fee payment |
Payment date: 20150227 Year of fee payment: 17 |
|
| FPAY | Annual fee payment |
Payment date: 20160226 Year of fee payment: 18 |
|
| EXPY | Expiration of term |