KR100197982B1 - Method of manufacturing mosfet - Google Patents
Method of manufacturing mosfet Download PDFInfo
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- KR100197982B1 KR100197982B1 KR1019950046978A KR19950046978A KR100197982B1 KR 100197982 B1 KR100197982 B1 KR 100197982B1 KR 1019950046978 A KR1019950046978 A KR 1019950046978A KR 19950046978 A KR19950046978 A KR 19950046978A KR 100197982 B1 KR100197982 B1 KR 100197982B1
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- refractory metal
- silicide
- metal layer
- gate
- layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000003870 refractory metal Substances 0.000 claims abstract description 46
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 40
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 24
- 230000005669 field effect Effects 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 25
- 238000002955 isolation Methods 0.000 claims description 15
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000007669 thermal treatment Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229910015900 BF3 Inorganic materials 0.000 description 8
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 모스전계효과 트랜지스터의 제조방법에 관한 것으로, 본 발명은 게이트, 소오스/드레인이 형성된 영역의 상부에 산화질화막을 형성하고, 상기 산화질화막의 상부에 내화물금속층을 형성하고, 상기 내화물금속층과 산화질화막을 열처리하여 상기 게이트와 소오스/드레인의 상부면에 실리사이드를 형성하고, 실리사이드로 형성되지 않은 산화질화막과 내화물금속을 식각하여 소오스/드레인 접합의 저항값을 감소하여 얕은 깊이의 접합을 형성한다.The present invention relates to a method for manufacturing a MOS field effect transistor, the present invention is to form an oxynitride film on the gate, the source / drain region is formed, a refractory metal layer on the oxynitride film, the refractory metal layer and The oxynitride film is heat-treated to form silicide on the top surface of the gate and the source / drain, and to etch the oxide / nitride film and the refractory metal which are not formed of the silicide to reduce the resistance value of the source / drain junction to form a shallow depth junction. .
Description
제1a도 내지 제1d도는 종래의 실시예에 따른 모스 전계 효과 트랜지스터의 제조 공정도.1A to 1D are manufacturing process diagrams of a MOS field effect transistor according to a conventional embodiment.
제2도는 상기 종래의 실시예에 따라 형성된 모스 전계 효과 트랜지스터의 실리사이드 표면에서부터 접합이 형성된 영역쪽으로의 거리에 따른 도펀트 농도를 도시한 그래프도.2 is a graph showing the dopant concentration according to the distance from the silicide surface of the MOS field effect transistor formed according to the conventional embodiment toward the region where the junction is formed.
제3a도 내지 제3d도는 본 발명의 일 실시예에 따른 모스 전계 효과 트랜지스터의 제조 공정도.3A to 3D are process diagrams of manufacturing a MOS field effect transistor according to an embodiment of the present invention.
제4도는 상기 본 발명의 일 실시예에 따라 형성된 모스 전계 효과 트랜지스터의 실리사이드 표면에서부터 접합이 형성된 영역쪽으로의 거리에 따른 붕소 농도를 도시한 그래프도.4 is a graph showing boron concentration according to a distance from a silicide surface of a MOS field effect transistor formed according to an embodiment of the present invention toward a region in which a junction is formed.
제5a도 내지 제5d도는 본 발명의 이 실시예에 따른 모스 전계 효과 트랜지스터의 제조 공정도.5A to 5D are manufacturing process diagrams of a MOS field effect transistor according to this embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : 소자분리막1: semiconductor substrate 2: device isolation film
3 : 게이트 산화막 4 : 게이트3: gate oxide film 4: gate
5 : 산화막 스페이서 6 : 소오스/드레인5 oxide film spacer 6 source / drain
7 : 내화물금속층 8 : 실리사이드막7: refractory metal layer 8: silicide film
9 : 산화질화막9: oxynitride film
본 발명은 모스전계효과 트랜지스터(Metal Oxide Semiconduct Field Effect Transister 이하, MOSFET라 한다. )의 제조방법에 관한 것으로, 특히 소오스/드레인 접합의 저항값을 감소하므로써, 얕은 깊이의 접합을 형성할 수 있는 MOSFET제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS field effect transistor (hereinafter referred to as a MOSFET), and in particular, a MOSFET capable of forming a shallow depth junction by reducing the resistance value of a source / drain junction. It relates to a manufacturing method.
반도체소자의 집적도 증가에 따른 얕은 깊이의 소오스/드레인 접합 형성은 고집적소자에 중요한 공정이 되고 있다. 256M 디램급 이상의 고집적 반도체소자는 0.25 ㎛ 이하의 접합깊이를 요구한다.Shallow depth source / drain junction formation is becoming an important process for highly integrated devices with increasing integration of semiconductor devices. Highly integrated semiconductor devices of 256M DRAM or higher require a junction depth of 0.25 μm or less.
일반적으로 금속배선 형성 공정에서, 실리콘 반도체기판의 상부에 MOSFET또는 캐패시터를 포함하는 도전층을 형성하고, 상기 도전층의 상부에 절연층을 형성하고, 콘택홀용 마스크로 상기 절연층을 도전층이 노출될 때까지 식각하여 콘택홀을 형성하고, 상기 구조의 전 표면에 티타늄 또는 티타늄질화막으로 확산방지막을 형성하고, 상기 확산방지막의 상부에 알루미늄으로 금속배선을 형성한다.Generally, in the metallization forming process, a conductive layer including a MOSFET or a capacitor is formed on the silicon semiconductor substrate, an insulating layer is formed on the conductive layer, and the conductive layer is exposed by a contact hole mask. Etch until a contact hole is formed, a diffusion barrier is formed of titanium or titanium nitride on the entire surface of the structure, and a metal wiring is formed of aluminum on the diffusion barrier.
그러나, 상기 티타늄 또는 티타늄질화막은 소오스/드레인 접합과의 접합저항을 상승시킨다. 또한, 고농도로 도핑된 소오스/드레인 접합은 저항이 300 μΩ㎝ 이상이므로, 고집적소자에 적용하기에는 접촉저항이 크다.However, the titanium or titanium nitride film increases the junction resistance with the source / drain junction. In addition, the highly doped source / drain junction has a resistance of 300 µΩcm or more, and therefore has a large contact resistance for application to high integration devices.
이를 해결하기 위한 방법중의 하나는 게이트의 상부와 소오스/드레인의 상부에 실리사이드막을 형성하여 게이트와, 소오스/드레인의 저항을 최소화할 수 있다. 이때, 게이트와 소오스/드레인 접합의 면저항(Rs)은 10Ω/㎠ 이하가 된다.One of the methods to solve this problem is to form a silicide film on the top of the gate and the top of the source / drain to minimize the resistance of the gate and the source / drain. At this time, the sheet resistance R s of the gate and the source / drain junction is 10 kW / cm 2 or less.
제1a도 내지 제1d도는 종래의 실리사이드를 이용한 MOSFET형성 공정도이다.1A to 1D are diagrams illustrating MOSFET formation using conventional silicides.
제1a도를 참조하면, 실리콘 반도체기판(1)의 소자분리영역에 소자분리막(2)을 형성하고, 노출된 반도체기판(1)의 상부에 게이트산화막(3)을 형성한다.Referring to FIG. 1A, an isolation layer 2 is formed in an isolation region of a silicon semiconductor substrate 1, and a gate oxide layer 3 is formed on the exposed semiconductor substrate 1.
그 다음, 상기 게이트산화막(3)의 상부에 폴리실리콘층을 증착한 후, 식각하여 게이트(4)를 형성하고, 상기 게이트(4)의 측벽에 산화막스페이서(5)를 형성한다.Then, after depositing a polysilicon layer on the gate oxide film 3, the gate 4 is formed by etching, and an oxide film spacer 5 is formed on the sidewall of the gate 4.
제1b도를 참조하면, 노출된 반도체기판(1)의 상부에서 비소(As) 또는 불화붕소(BF2) 이온을 3E15/㎠ 이상의 농도로 주입하여 n+또는 p+타입의 소오스/드레인(6)을 형성한다.Referring to FIG. 1B, arsenic (As) or boron fluoride (BF 2 ) ions are implanted at a concentration of 3E15 / cm 2 or more on the exposed semiconductor substrate 1 to provide a source / drain of n + or p + type 6 ).
제1c도를 참조하면, 상기 구조의 전 표면에 몰라브덴, 탄탈, 텅스텐, 티타늄, 코발트, 니켈, 백금중의 하나인 내화물금속층(7)을 형성한다.Referring to FIG. 1C, a refractory metal layer 7 of molybdenum, tantalum, tungsten, titanium, cobalt, nickel, or platinum is formed on the entire surface of the structure.
제1d도를 참조하면, 상기 내화물금속층(7)을 제1차 단시간 급속열처리 하므로써, 상기 내화물금속층(7)과, 게이트(4)와 소오스/드레인(6)의 실리콘이 반응하여 실리사이드(도시하지 않음)을 형성하고, 반응하지 않는 내화물금속층을 식각한 후, 제1차 단시간 급속열처리된 실리사이드를 제2차 단시간 급속열처리하여 실리사이드(8)를 형성한다.Referring to FIG. 1D, the refractory metal layer 7 reacts with the silicide (not shown) by reacting the refractory metal layer 7 with the silicon of the gate 4 and the source / drain 6 by the first short-time rapid heat treatment. After the non-reacting refractory metal layer is etched, and the first short time rapid heat treatment silicide is subjected to the second short time rapid heat treatment to form the silicide 8.
그러나, 종래의 실리사이드를 이용한 MOSFET제조방법은 비소(As) 또는 붕소(B)이온이 내화물금속과 반응하여 실리사이드의 성장을 방해하여 실리사이드가 불균일한 두께로 형성되므로써, 접합층의 깊이가 불균일하게 된다. 또, 실리사이드와 실리콘 계면의 도펀트농도가 감소하여 접촉저항이 상승하게 되는 문제점이 있다.However, in the conventional MOSFET manufacturing method using the silicide, as the arsenic (As) or boron (B) ions react with the refractory metal to inhibit the growth of the silicide, the silicide is formed to have a non-uniform thickness, resulting in uneven thickness of the bonding layer. . In addition, the dopant concentration of the silicide and the silicon interface is reduced, there is a problem that the contact resistance is increased.
제2도는 상기 제1a도 내지 제1d도의 제조 공정도에 의하여 형성된 MOSFET의 실리사이드 표면에서부터 접합이 형성된 영역쪽으로의 거리에 따른 도펀트 농도를 도시한 그래프도이다.FIG. 2 is a graph showing the dopant concentration according to the distance from the silicide surface of the MOSFET formed by the manufacturing process diagram of FIGS. 1A to 1D to the region where the junction is formed.
제2도를 참조하면, 실리사이드와 실리콘 계면에서 도펀트의 농도가 급격히 감소함을 알 수 있고, a 경우에 비하여 상대적으로 얕은 접합인 b의 경우에 농도변화가 더 큰 것을 알 수 있다.Referring to FIG. 2, it can be seen that the concentration of the dopant is rapidly decreased at the silicide and silicon interface, and the concentration change is larger in the case of b, which is a relatively shallow junction, than in the case of a.
따라서, 본 발명의 목적은 상기 문제점을 해결하기 위한 것으로, 본 발명은 게이트, 소오스/드레인이 형성된 구조의 전 표면에 도펀트의 확산계수가 낮은 산화질화막을 확산방지막으로 형성하여 실리사이드 형성을 위한 열공정시, 내화물금속과 도펀트와의 반응을 방지하므로써, 소오스/드레인 접합깊이를 균일하게 형성할 수 있으며, 소오스/드레인 저항값이 감소하여 얕은 깊이의 접합을 형성할 수 있는 MOSFET제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to solve the above problems, and the present invention is to form an oxynitride film having a low diffusion coefficient of dopant as a diffusion barrier on the entire surface of the gate, source / drain formed structure during the thermal process for silicide formation By preventing the reaction between the refractory metal and the dopant, the source / drain junction depth can be formed uniformly, and the source / drain resistance value is reduced to provide a MOSFET manufacturing method that can form a shallow depth junction. There is this.
상기 목적을 달성하기 위한 본 발명의 MOSFET제조방법의 제1특징은 반도체기판의 소자분리영역에 소자분리막을 형성하고, 반도체기판의 액티브영역에 게이트산화막, 게이트를 차례로 형성하고, 상기 게이트의 측벽에 산화막스페이서를 형성하고, 상기 게이트와 산화막스페이서를 마스크로 사용하여 n+또는 p+타입의 소오스/드레인을 형성한 반도체소자의 제조방법에 있어서,A first aspect of the MOSFET manufacturing method of the present invention for achieving the above object is to form a device isolation film in the device isolation region of the semiconductor substrate, and to form a gate oxide film, a gate in the active region of the semiconductor substrate, and to the sidewall of the gate A method of manufacturing a semiconductor device in which an oxide film spacer is formed and an n + or p + type source / drain is formed using the gate and the oxide film spacer as a mask.
상기 구조의 전표면에 산화질화막을 형성하는 단계와,Forming an oxynitride film on the entire surface of the structure;
상기 산화질화막의 상부에 내화물금속층을 형성하는 단계와,Forming a refractory metal layer on the oxynitride film;
상기 내화물금속층과 산화질화막을 열처리하여 상기 게이트와 소오스/드레인의 상부면에 실리사이드를 형성하는 단계와,Heat-treating the refractory metal layer and the oxynitride layer to form silicide on the top surfaces of the gate and the source / drain;
산화질화막과 내화물금속층중 실리사이드로 형성되지 않은 부분을 식각하는 단계를 포함하는 것이다.Etching the portion of the oxynitride film and the refractory metal layer, which is not formed of silicide.
상기 목적을 달성하기 위한 본 발명의 MOSFET제조 방법의 제2특징은 반도체기판의 소자분리영역에 소자분리막을 형성하고, 반도체기판의 액티브영역에 게이트산화막, 게이트를 차례로 형성하고, 상기 게이트의 측벽에 산화막스페이서를 형성한 반도체 소자의 제조방법에 있어서,According to a second aspect of the present invention, a device isolation film is formed in a device isolation region of a semiconductor substrate, a gate oxide film and a gate are sequentially formed in an active region of the semiconductor substrate, and a sidewall of the gate is formed. In the method of manufacturing a semiconductor device having an oxide film spacer,
상기 구조의 전표면에 산화질화막을 형성하는 단계와,Forming an oxynitride film on the entire surface of the structure;
상기 산화질화막 상부에서 이온을 주입하여 소오스/드레인을 형성하는 단계와,Implanting ions on the oxynitride layer to form a source / drain;
상기 구조의 전 표면에 내화물금속층을 형성하는 단계와,Forming a refractory metal layer on the entire surface of the structure;
상기 내화물금속층과 산화질화막을 열처리하여 상기 게이트와 소오스/드레인의 상부면에 실리사이드를 형성하는 단계와,Heat-treating the refractory metal layer and the oxynitride layer to form silicide on the top surfaces of the gate and the source / drain;
산화질화막과 내화물금속층중 실리사이드로 형성되지 않은 부분을 식각하는 단계를 포함하는 것이다.Etching the portion of the oxynitride film and the refractory metal layer, which is not formed of silicide.
이하, 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대한 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
제3a도 내지 제3d도는 본 발명의 일 실시예에 따른 MOSFET제조 공정도이다.3A to 3D are MOSFET manufacturing process diagrams according to an embodiment of the present invention.
제3a도를 참조하면, 실리콘 반도체기판(1)의 소자분리영역에 소자분리막(2)을 형성하고, 반도체기판(1)의 액티브(active)영역에 게이트산화막(3)을 형성하고, 폴리실리콘층을 증착한 후, 식각하여 게이트(4)를 형성한다.Referring to FIG. 3A, an isolation layer 2 is formed in an isolation region of the silicon semiconductor substrate 1, a gate oxide layer 3 is formed in an active region of the semiconductor substrate 1, and polysilicon is formed. After the layer is deposited, it is etched to form the gate 4.
그 다음, 상기 게이트(4)의 측벽에 산화막스페이서(5)를 형성하고, 상기 게이트(4)와 산화막스페이서(5)를 마스크로 사용하여 비소(As) 또는 불화붕소(BF2) 이온을 3E15/㎠ 이상의 농도로 주입하여 n+또는 p+타입의 소오스/드레인(6)을 형성한다.Next, an oxide spacer 5 is formed on the sidewall of the gate 4, and arsenic (As) or boron fluoride (BF 2 ) ions 3E15 are formed using the gate 4 and the oxide spacer 5 as a mask. It is injected at a concentration of / cm 2 or more to form a source / drain 6 of n + or p + type.
제3b도를 참조하면, 상기 구조의 전표면에 RF-PECVD(Radio Frequency- Plasma Enhanced Chemical Vapor Deposition) 방법으로 10∼100Å 두께의 산화질화막(9)을 형성한다.Referring to FIG. 3b, an oxynitride film 9 having a thickness of 10 to 100 kHz is formed on the entire surface of the structure by RF-PECVD (Radio Frequency- Plasma Enhanced Chemical Vapor Deposition) method.
이때, 상기 산화질화막(9)은 아래의 표1과 같은 조건에서 증착한다.In this case, the oxynitride film 9 is deposited under the conditions shown in Table 1 below.
제3c도를 참조하면, 상기 구조의 전 표면에 0.2∼100 mTorr의 압력과 1∼20 KW의 RF 전력과, 25∼300℃의 기판온도에서 스퍼터링 방법으로 100∼1000Å 두께의 내화물금속층(7)을 형성한다.Referring to FIG. 3C, a refractory metal layer 7 having a thickness of 100 to 1000 kPa is formed on the entire surface of the structure by sputtering at a pressure of 0.2 to 100 mTorr, RF power of 1 to 20 KW, and substrate temperature of 25 to 300 ° C. To form.
이때, 상기 내화물금속으로는 몰라브덴, 탄탈, 텅스텐, 티타늄, 코발트, 니켈, 백금등이 있다.In this case, the refractory metals include molybdenum, tantalum, tungsten, titanium, cobalt, nickel, platinum, and the like.
제3d도는 상기 내화물금속층(7)과 산화질화막(9)을 열처리하여 상기 내화물금속과 반도체기판의 실리콘이 반응하므로써, 게이트(4)와 소오스/드레인(6)의 상부면에 실리사이드(8)를 형성한다.FIG. 3D shows that the silicide 8 is formed on the top surface of the gate 4 and the source / drain 6 by heat-treating the refractory metal layer 7 and the oxynitride film 9 to react the silicon of the refractory metal and the semiconductor substrate. Form.
이때, 상기 내화물금속층(7)과 산화질화막(9)을 열처리하는 방법으로는 급속열처리(Rapid Thermal Annealing)방법과, 퍼니스 열처리(Furnace Annealing)하는 방법이 있으며, 상기 급속열처리와, 퍼니스열처리를 조합하여 진행하는 방법이 있다.In this case, a method of heat treating the refractory metal layer 7 and the oxynitride film 9 may include a rapid thermal annealing method and a furnace annealing method. The rapid heat treatment and the furnace heat treatment may be combined. There is a way to proceed.
이때, 상기 산화질화막(9)은 도펀트가 상기 내화물금속층(7)쪽으로 확산되는 것을 방지하므로써, 내화물금속과 도펀트와의 반응을 방지한다.At this time, the oxynitride film 9 prevents the dopant from diffusing into the refractory metal layer 7, thereby preventing the reaction of the refractory metal with the dopant.
그 다음, 암모니아성 식각액을 이용하여 반응하지 않은 산화질화막(7)과 내화물금속(7)을 식각한다.Then, the oxynitride film 7 and the refractory metal 7 which have not reacted are etched using an ammonia etchant.
제4도는 본 발명의 실시예에 의한 실리사이드 구조의 모스전계 효과 트랜지스터의 실리사이드 표면에서 반도체기판쪽으로의 거리에 따른 붕소의 농도를 도시한 그래프도로서, c 그래프는 소오스/드레인 접합을 형성하기 위하여 붕소를 주입한 직후의 도펀트의 프로파일(profile)을 나타내고, d 그래프는 본 발명의 실리사이드 공정 직후의 도펀트의 프로파일을 나타낸다. 또, e 그래프는 산화질화막을 형성하는 공정을 생략하고, 실리사이드를 형성한 공정 직후의 도펀트의 프로파일을 나타낸다.4 is a graph showing the concentration of boron according to the distance from the silicide surface to the semiconductor substrate of the silicide structured Mohs field effect transistor according to an embodiment of the present invention, the c graph is a boron to form a source / drain junction The profile of the dopant immediately after the injection is shown, and the graph d shows the profile of the dopant immediately after the silicide process of the present invention. In addition, the e graph shows the profile of the dopant immediately after the step of forming the silicide, omitting the step of forming the oxynitride film.
제4도를 참조하면, d 그래프에 도시된 바와 같이 산화질화막을 형성하면, 내화물금속과 도펀트가 거의 반응하지 않으므로 실리사이드/실리콘 계면에서 도펀트의 농도 변화가 거의 없음을 알 수 있다.Referring to FIG. 4, it can be seen that when the oxynitride film is formed as shown in the graph d, since the refractory metal and the dopant hardly react, there is little change in the concentration of the dopant at the silicide / silicon interface.
제5a도 내지 제5d도는 본 발명의 이 실시예에 따른 MOSFET제조 공정도이다.5A to 5D show a MOSFET manufacturing process according to this embodiment of the present invention.
제5a도를 참조하면, 실리콘 반도체기판(1)의 소자분리영역에 소자분리막(2)을 형성하고, 반도체기판(1)의 액티브(active)영역에 게이트산화막(3)을 형성하고, 폴리실리콘을 증착한 후 식각하여 게이트(4)를 형성한다.Referring to FIG. 5A, an isolation layer 2 is formed in an isolation region of a silicon semiconductor substrate 1, a gate oxide layer 3 is formed in an active region of the semiconductor substrate 1, and polysilicon is formed. After the deposition is etched to form a gate (4).
그 다음, 상기 게이트(4)의 측벽에 산화막스페이서(5)를 형성한다.Next, an oxide film spacer 5 is formed on the sidewall of the gate 4.
제5b도를 참조하면, 상기 구조의 전표면에 RF-PECVD(Radio Frequency-Plasma Enhanced Chemical Vapor Deposition) 방법으로 10∼100Å 두께의 산화질화막(9)을 형성한다.Referring to FIG. 5B, an oxynitride film 9 having a thickness of 10 to 100 kHz is formed on the entire surface of the structure by RF-PECVD (Radio Frequency-Plasma Enhanced Chemical Vapor Deposition) method.
이때, 상기 산화질화막(9)은 아래의 표 1과 같은 조건에서 증착한다.In this case, the oxynitride film 9 is deposited under the conditions shown in Table 1 below.
제5c도를 참조하면, 상기 게이트(4)와 산화막스페이서(5)를 마스크로 사용하여 상기 산화질화막(7)의 상부에서 비소(As) 또는 불화붕소(BF) 이온을 3E15/㎠ 이상의 농도로 주입하여 n 또는 p 타입의 소오스/드레인(6)을 형성한다.Referring to FIG. 5C, arsenic (As) or boron fluoride (BF) ions are formed at a concentration of 3E15 / cm 2 or more in the upper portion of the oxynitride film 7 by using the gate 4 and the oxide film spacer 5 as a mask. Inject n Or p A source / drain 6 of type is formed.
이때, 불화붕소(BF) 또는 비소(As)는 산화질화막(7)을 통하여 반도체기판(1)에 주입되므로 얕은 소오스/드레인(6) 접합 형성이 가능하고, 이온주입에 의한 결함이 산화질화막(7) 내에만 존재하게 되어 소오스/드레인(6)내의 손상밀도가 감소하게 된다.At this time, since boron fluoride (BF) or arsenic (As) is implanted into the semiconductor substrate 1 through the oxynitride film 7, it is possible to form a shallow source / drain 6 junction. 7) the density of damage in the source / drain 6 is reduced by being present only within.
그 다음, 상기 구조의 전 표면에 0.2∼100 mTorr의 압력과 1∼20 KW의 RF 전력과, 25∼300℃의 기판온도에서 스퍼터링 방법으로 100∼1000Å 두께의 내화물금속층(7)을 형성한다.Then, a refractory metal layer 7 having a thickness of 100 to 1000 mW is formed on the entire surface of the structure by sputtering at a pressure of 0.2 to 100 mTorr, an RF power of 1 to 20 KW, and a substrate temperature of 25 to 300 ° C.
이때, 상기 내화물금속으로는 몰라브덴, 탄탈, 텅스텐, 티타늄, 코발트, 니켈, 백금등이 있다.In this case, the refractory metals include molybdenum, tantalum, tungsten, titanium, cobalt, nickel, platinum, and the like.
제5d도는 상기 내화물금속층(7)과 산화질화막(9)을 열처리하여 상기 내화물금속과 반도체기판의 실리콘이 반응하므로써, 게이트(4)와 소오스/드레인(6)의 상부면에 실리사이드(8)를 형성한다.FIG. 5D shows that the silicide 8 is formed on the top surface of the gate 4 and the source / drain 6 by heat-treating the refractory metal layer 7 and the oxynitride film 9 to react the silicon of the refractory metal and the semiconductor substrate. Form.
이때, 상기 내화물금속층(7)과 산화질화막(9)을 열처리하는 방법으로는 급속열처리(Rapid Thermal Annealing)방법과, 퍼니스 열처리(Furnace Annealing)하는 방법이 있으며, 상기 급속열처리와, 퍼니스열처리를 조합하여 진행하는 방법이 있다.In this case, a method of heat treating the refractory metal layer 7 and the oxynitride film 9 may include a rapid thermal annealing method and a furnace annealing method. The rapid heat treatment and the furnace heat treatment may be combined. There is a way to proceed.
이때, 상기 산화질화막(9)은 도펀트가 상기 내화물금속층(7)쪽으로 확산되는 것을 방지하므로써, 내화물금속과 도펀트와의 반응을 방지한다.At this time, the oxynitride film 9 prevents the dopant from diffusing into the refractory metal layer 7, thereby preventing the reaction of the refractory metal with the dopant.
그 다음, 암모니아성 식각액을 이용하여 반응하지 않은 산화질화막(7)과 내화물금속(7)을 식각한다.Then, the oxynitride film 7 and the refractory metal 7 which have not reacted are etched using an ammonia etchant.
상술한 바와 같이 본 발명의 MOSFET제조방법은 게이트와 소오스/드레인이 형성된 구조의 전 표면에 산화질화막을 형성하여 실리사이드를 형성하기 위한 열공정시 소오스/드레인영역과 게이트 영역의 도펀트가 실리사이드 내로 확산하는 것을 방지하므로써, 균일한 깊이의 접합을 형성하여 소자의 신뢰성을 향상하는 이점이 있다. 또, 실리사이드와 실리콘 계면의 도펀트 농도변화가 거의 없어 소오스/드레인의 접촉저항을 감소하는 이점이 있다.As described above, the MOSFET manufacturing method of the present invention prevents diffusion of the dopants of the source / drain region and the gate region into the silicide during the thermal process for forming the silicide by forming an oxynitride film on the entire surface of the gate and the source / drain structure. This prevents the formation of a junction of uniform depth, thereby improving the reliability of the device. In addition, there is almost no change in the dopant concentration between the silicide and the silicon interface, thereby reducing the contact resistance of the source / drain.
Claims (11)
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| KR1019950046978A KR100197982B1 (en) | 1995-12-06 | 1995-12-06 | Method of manufacturing mosfet |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950046978A KR100197982B1 (en) | 1995-12-06 | 1995-12-06 | Method of manufacturing mosfet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970053013A KR970053013A (en) | 1997-07-29 |
| KR100197982B1 true KR100197982B1 (en) | 1999-06-15 |
Family
ID=19437987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950046978A KR100197982B1 (en) | 1995-12-06 | 1995-12-06 | Method of manufacturing mosfet |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100197982B1 (en) |
-
1995
- 1995-12-06 KR KR1019950046978A patent/KR100197982B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970053013A (en) | 1997-07-29 |
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