KR100187601B1 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- KR100187601B1 KR100187601B1 KR1019950017339A KR19950017339A KR100187601B1 KR 100187601 B1 KR100187601 B1 KR 100187601B1 KR 1019950017339 A KR1019950017339 A KR 1019950017339A KR 19950017339 A KR19950017339 A KR 19950017339A KR 100187601 B1 KR100187601 B1 KR 100187601B1
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- diffusion barrier
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 104
- 230000004888 barrier function Effects 0.000 claims abstract description 90
- 239000003990 capacitor Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000013078 crystal Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 25
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 229910052697 platinum Inorganic materials 0.000 description 10
- 238000004544 sputter deposition Methods 0.000 description 10
- 238000000926 separation method Methods 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 6
- 229910001080 W alloy Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910001361 White metal Inorganic materials 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000003405 preventing effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000010969 white metal Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은, 높은 유전율을 가진 유전체막을 사용한 커패시터를 내장하는 반도체 장치 및 그 제조방법에 관한 것으로서, 신뢰성에 뛰어난 반도체장치와 그 제조방법을 제공하는 것을 목적으로 한 것이며, 그 구성에 있어서, 집적회로가 형성되어 있는 실리콘기판(1)과, 그 위에 형성된 제 1의 절연막(6)과, 제 1의 절연막위에 형성된 하부전극(7), 고유전율을 가진 유전체막(8) 및 상부전극(9)으로 이루어진 커패시터와, 커패시터를 덮고, 하부전극(7) 및 상부전극(9)에 각각 도달하는 콘택트구멍(13)을 가진 제 2의 절연막(11)과, 콘택트구멍(13)의 바닥부에서 하부전극(7) 및 상부전극(9)에 접촉하는 확산장벽층(17)과, 그위에 형성된 배선층(15)으로 이루어진 반도체장치에 있어서, 콘택트구멍(13)의 바닥부에 있는 확산장벽층(17)내에 입자형상결정으로 이루어진 층형상영역이 형성되어 있는 것을 특징으로 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a capacitor using a dielectric film having a high dielectric constant and a method for manufacturing the same, and an object of the present invention is to provide a semiconductor device excellent in reliability and a method for manufacturing the same. Is formed on the silicon substrate 1, the first insulating film 6 formed thereon, the lower electrode 7 formed on the first insulating film, the dielectric film 8 and the upper electrode 9 having high dielectric constant. A second insulating film 11 having a capacitor, a contact hole 13 covering the capacitor, and reaching the lower electrode 7 and the upper electrode 9, respectively, and a lower portion at the bottom of the contact hole 13; In the semiconductor device which consists of the diffusion barrier layer 17 which contacts the electrode 7 and the upper electrode 9, and the wiring layer 15 formed on it, the diffusion barrier layer 17 in the bottom part of the contact hole 13 is carried out. Layered structure with granular crystals Region will one being formed.
Description
제1도는 커패시터를 내장하는 본 발명의 종래의 반도체장치의 구조를 표시한 모식단면도.1 is a schematic cross-sectional view showing the structure of a conventional semiconductor device of the present invention incorporating a capacitor.
제2도는 확산장벽층의 두께와 콘택트구멍에 있어서 도통불량의 발생율과의 관계를 표시한 그래프.2 is a graph showing the relationship between the thickness of the diffusion barrier layer and the incidence of poor conduction in contact holes.
제3도 및 제4도는 커패시터와 배선층과의 콘택트구멍에 있어서의 확산장벽층의 결정상태를 표시한 모식단면도.3 and 4 are schematic cross-sectional views showing the crystal state of the diffusion barrier layer in the contact hole between the capacitor and the wiring layer.
제5도는 본 발명의 반도체장치에 있어서, 2층의 확산장벽층으로 이루어진 반도체장치의 구조를 표시한 모식단면도.5 is a schematic sectional view showing the structure of a semiconductor device comprising two diffusion barrier layers in the semiconductor device of the present invention.
제6도는 커패시터와 배선층과의 콘택트구멍에 있어서의 2층의 확산장벽층의 결정상태를 표시한 모식단면도.FIG. 6 is a schematic sectional view showing a crystal state of two diffusion barrier layers in contact holes between a capacitor and a wiring layer. FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 분리산화막1: silicon substrate 2: separation oxide film
3 : 확산층 4 : 게이트절연막3: diffusion layer 4: gate insulating film
5 : 게이트전극 6 : 제1의 절연막5 gate electrode 6 first insulating film
7 : 하부전극 8 : 강유전체막7: lower electrode 8: ferroelectric film
9 : 상부전극 11 : 제2의 절연막9: upper electrode 11: second insulating film
12, 13 : 콘택트구멍 14, 15 : 배선층12, 13 contact hole 14, 15 wiring layer
16 : 보호막 17 : 확산장벽층16: protective film 17: diffusion barrier layer
17a : 제1의 확산장벽층 17b : 제2의 확산장벽층17a: first diffusion barrier layer 17b: second diffusion barrier layer
본 발명은, 높은 유전율을 가진 유전체막을 사용한 커패시터를 내장하는 반도체 장치 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor device incorporating a capacitor using a dielectric film having a high dielectric constant and a method of manufacturing the same.
최근, 전자기기에 있어서의 정보처리의 고속화 및 저진압 동작화에 따라, 전자기기로부터 발하게 되는 전자복사에 의한 잡음의 방지가 중대한 과제로 되어있다.Background Art In recent years, as the information processing in electronic devices has been accelerated and the operation of low suppression has been made, the prevention of noise by electromagnetic radiation emitted from electronic devices has become a serious problem.
이 잡음을 저감하는 수단의 하나로서, 강유전체막 등의 고유전율을 가진 유전체막을 사용한 커패시터를 반도체집적회로에 짜넣는 기술이 주목되고 있다. 또, 강유전체막의 히스테리시스특성을 이용해서, 저전압동작 및 고속의 기록판독을 가능하게 하는 불휘발성메모리의 실용화연구가 열심히 행하여지고 있다.As a means of reducing this noise, the technique which incorporates the capacitor using the dielectric film which has high dielectric constant, such as a ferroelectric film, in a semiconductor integrated circuit is attracting attention. Further, studies on practical use of nonvolatile memories that enable low-voltage operation and high-speed recording reading by using the hysteresis characteristics of the ferroelectric film have been conducted.
이하, 강유전체막을 가진 커패시터를 내장한 종해의 반도체장치에 대해서, 도면을 참조하면서 설명한다. 제1도에 표시한 바와같이, 실리콘기판(1)의 위에 분리산화막(2)이 형성되고, 그 분리산화막(2)에 의해서 둘러싸인 영역에, 확산층(3)과 게이트절연막(4)과 게이트전극(5)으로 이루어지는 트렌지스터가 형성된다. 그리고, 이 트랜지스터 및 분리산화막(2)을 덮는 제2의 절연막이 형성된다.Hereinafter, a semiconductor device of a vertical sea incorporating a capacitor having a ferroelectric film will be described with reference to the drawings. As shown in FIG. 1, a separation oxide film 2 is formed on the silicon substrate 1, and the diffusion layer 3, the gate insulating film 4, and the gate electrode are formed in a region surrounded by the separation oxide film 2. As shown in FIG. A transistor consisting of (5) is formed. Then, a second insulating film covering the transistor and the separation oxide film 2 is formed.
그 제1의 절연막(6)의 위에, 하부전극(7)과 PZT등의 강유전체막(8)과 상부전극(9)으로 이루어지는 커패시터가 형성된다. 하부전극(7) 및 상부전극(9)에는, PZT등의 금속산화물에 대해서 화학적으로 안정적인 백금이 사용된다. 그리고, 이 커패시터를 덮도록, 제1의 절연막(6)의 위에 제2의 절연막(11)이 형성된다.On the first insulating film 6, a capacitor including a lower electrode 7, a ferroelectric film 8 such as PZT, and an upper electrode 9 is formed. For the lower electrode 7 and the upper electrode 9, platinum chemically stable to metal oxides such as PZT is used. Then, the second insulating film 11 is formed on the first insulating film 6 so as to cover the capacitor.
제1의 절연막(6) 및 제2의 절연막(11)에는, 확산층(3)에 도달하는 콘택트구멍(12)과, 하부전극(7) 및 상부전극(9)에 도달하는 콘택트구멍(13)이 각각 형성된다. 그리고, 콘택트구멍(12)을 통해서 확산층(3)에 전기적으로 접속된 알루미늄의 배선층(14)과, 콘택트구멍(13)을 통해서 하부전극(7) 및 상부전극(9)에 전기적으로 접속된 알루미늄의 배선층(15)이 각각 독립적으로 또한 선택적으로 형성된다. 단, 하부전극(7) 및 상부전극(9)과 배선층(15)이 직접 접촉하면, 나중에 열처리시에 알루미늄과 백금이 반응을 일으켜서 백금속에 Al2Pt가 나타나, 양자의 접속강소가 현저히 저하된다. 이것을 방지하기 위하여, 통상은 하부전극(7)과 상부전극(9)과 배선층(15)과의 사이에, 질화티탄으로 이루어진 확산장벽층(17)이 50nm∼150nm의 두께로 형성되어 있다.The first insulating film 6 and the second insulating film 11 have a contact hole 12 reaching the diffusion layer 3 and a contact hole 13 reaching the lower electrode 7 and the upper electrode 9. Are formed respectively. The aluminum wiring layer 14 electrically connected to the diffusion layer 3 through the contact hole 12 and the aluminum electrically connected to the lower electrode 7 and the upper electrode 9 through the contact hole 13. Wiring layers 15 are each independently and selectively formed. However, if the lower electrode 7 and the upper electrode 9 and the wiring layer 15 are in direct contact with each other, aluminum and platinum react with each other during the heat treatment later, so that Al 2 P t appears in the white metal, and the connection strength of both is significantly reduced. do. In order to prevent this, usually, a diffusion barrier layer 17 made of titanium nitride is formed to have a thickness of 50 nm to 150 nm between the lower electrode 7, the upper electrode 9, and the wiring layer 15.
배선층(14),(15)이 형성된 실리콘기판(1)은, 배선층(14)과 확산층(3)과의 계면을 오믹접촉으로 하기 위하여, 수소를 함유한 불활성가스분위기속에서 450℃이상의 비교적 고온으로 열처리된다. 그리고, 트랜지스터나 커패시터를 덮도록 실리콘기판(1)상의 전체면에, 질화실리콘등의 내습성에 뛰어난 재료의 보호막(16)이 형성된다.The silicon substrate 1 on which the wiring layers 14 and 15 are formed has a relatively high temperature of 450 ° C. or higher in an inert gas atmosphere containing hydrogen in order to make the interface between the wiring layer 14 and the diffusion layer 3 into ohmic contact. Heat treatment. Then, the protective film 16 made of a material excellent in moisture resistance such as silicon nitride is formed on the entire surface of the silicon substrate 1 so as to cover the transistor or the capacitor.
그러나, 이와같은 종래의 반도체장치는, 50nm∼150nm두께의 확산장벽층(17)을 형성하고 있는데도 불구하고, 콘택트구멍(13)에 있어서의 하부전극(7) 및 상부전극(9)과 배선층(15)과의 사이의 접속강도가 반드시 충분하지 않았다.However, in the conventional semiconductor device as described above, although the diffusion barrier layer 17 having a thickness of 50 nm to 150 nm is formed, the lower electrode 7, the upper electrode 9 and the wiring layer (in the contact hole 13) are formed. 15) The strength of connection between and was not necessarily sufficient.
이 때문에, 반도체장치의 다수의 콘택트구멍(13)중에는 도통불량을 일으키는 것이 발생하여, 반도체장치의 신뢰성이 충분히 확보되어 있다고는 말할 수 없었다.For this reason, conduction defects generate | occur | produce in the many contact hole 13 of a semiconductor device, and it cannot be said that reliability of a semiconductor device is fully secured.
본 발명은, 신뢰성에 뛰어난 반도체장치와 그 제조방법을 제공하는 것을 목적으로 한다.An object of the present invention is to provide a semiconductor device excellent in reliability and a manufacturing method thereof.
본 발명의 반도체장치는, 집적회로가 형성되어 있는 기판과, 이 기판위에 형성된 제1의 절연막과, 이 제1의 절연막위에 형성된 하부전극, 그 하부전극위에 형성된 고유전율을 가진 유전체막, 및 그 유전체막에 형성된 상부전극으로 이루어진 커패시터와, 이 커패시터을 덮고, 하부전극 및 상부전극에 각각 도달하는 콘택트구멍을 가진 제2의 절연막막, 적어도 이 콘택트구멍의 내벽을 덮고, 콘택트구멍의 바닥부에서 하부전극 및 상부전극에 접촉하는 확산장벽층과, 이 확산장벽층위에 형성된 배선층으로 이루어진 반도체장치에 있어서, 이 확산장벽층내에 입자형상결정으로 이루어진 층형상영역을 형성한 것이다.A semiconductor device of the present invention includes a substrate on which an integrated circuit is formed, a first insulating film formed on the substrate, a lower electrode formed on the first insulating film, a dielectric film having a high dielectric constant formed on the lower electrode, and a A second insulating film having a capacitor comprising an upper electrode formed in the dielectric film, and a second insulating film covering the capacitor and having a contact hole reaching the lower electrode and the upper electrode, at least covering the inner wall of the contact hole, and the lower portion at the bottom of the contact hole. In a semiconductor device comprising a diffusion barrier layer in contact with an electrode and an upper electrode, and a wiring layer formed on the diffusion barrier layer, a layered region made of grain crystals is formed in the diffusion barrier layer.
이 확산장벽층의 두께는, 200nm로부터 300nm까지의 범위가 바람직하다. 또, 이 확산장벽층을 제1의 층과 제2의 층과의 2층구조로 하고, 제2의 층을 입자 형상결정의 층으로 하는 것이 바람직하다.The thickness of this diffusion barrier layer is preferably in the range from 200 nm to 300 nm. Moreover, it is preferable to make this diffusion barrier layer into a two-layer structure of a 1st layer and a 2nd layer, and to make a 2nd layer into a layer of grain shape.
본 발명의 반도체장치의 제조방법은, 집적회로가 형성되어 있는 기판위에 제1의 절연막을 형성하는 공정과, 이 제1의 절연막위에 하부전극과 고유전율을 가진 유전체막과 상부전극으로 이루어진 커패시터를 형성하는 공정과, 이 커패시터를 덮는 제2의 절연막을 형성하는 공정과, 이 제2의 절연막에 하부전극 및 상부전극에 각각 도달하는 콘택트구멍을 형성하는 공정과, 적어도 콘택트구멍의 내벽을 덮고, 콘택트구멍의 바닥부에서 하부전극 및 상부전극에 접촉하는 확산장벽층을 형성하는 공정과, 이 확산장벽층위에 배선층을 형성하는 공정과, 열처리하는 공정으로 이루어지는 제조방법에 있어서, 이 열처리를 300℃에서부터 420℃까지의 온도범위에서 행하는 것이다.In the method of manufacturing a semiconductor device of the present invention, there is provided a method of forming a first insulating film on a substrate on which an integrated circuit is formed, and a capacitor comprising a lower electrode, a dielectric film having a high dielectric constant and an upper electrode on the first insulating film. Forming a second insulating film covering the capacitor, forming a contact hole reaching the lower electrode and the upper electrode, respectively, covering at least the inner wall of the contact hole; A process for forming a diffusion barrier layer in contact with a lower electrode and an upper electrode at the bottom of a contact hole, a step of forming a wiring layer on the diffusion barrier layer, and a heat treatment step, wherein the heat treatment is performed at 300 캜. It is performed in the temperature range from to 420 degreeC.
특히, 이 열처리는 300℃에서부터 380℃까지의 온도범위가 보다 바람직하다.또, 확산장벽층을 형성하는 공정은, 제1의 층을 형성하는 공정과 제2의 층을 형성하는 공정과의 2회로 나누어서 행하여지는 것이 바람직하다.In particular, the heat treatment is more preferably in a temperature range from 300 ° C. to 380 ° C. In addition, the step of forming the diffusion barrier layer includes two steps of forming the first layer and forming the second layer. It is preferable to carry out by dividing into circuits.
이하, 본 발명의 실시예데 대해서 첨부도면을 참조해서 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명자들은, 제1도에 표시한 구조의 반도체장치에 있어서, 확산장벽층의 두께 및 열처리온도를 여러 가지로 바꾼 샘플을, 이하에 설명하는 제조방법에 의해 제작하였다.The present inventors produced the sample which changed the thickness and heat processing temperature of the diffusion barrier layer variously in the semiconductor device of the structure shown in FIG. 1 by the manufacturing method demonstrated below.
먼저, 종래의 반도체형성기술에 의해, 실리콘기판(1)의 위에 분리산화막(2)을 형성하고, 그 분리산화막(2)에 의해서 둘러싸인 영역에, 확산층(3)과 게이트 절연막(4)과 게이트전극(5)으로 이루어진 트랜지스터를 형성한다. 그리고, 이 트랜지스터 및 분리산화막(2)을 덮는 제1의 절연막(6)을 통상의 CVD법에 의해 형성한다.First, a separation oxide film 2 is formed on the silicon substrate 1 by a conventional semiconductor forming technique, and the diffusion layer 3, the gate insulating film 4, and the gate are formed in a region surrounded by the separation oxide film 2. A transistor consisting of the electrode 5 is formed. Then, the first insulating film 6 covering the transistor and the separation oxide film 2 is formed by a normal CVD method.
다음에, 제1의 절연막(6)의 위에, 백금의 하부전극(7)과 티탄산스트론톰계의 강유전체막(8)과 백금의 상부전극(9)으로 이루어진 커패시터를 통상의 스퍼터링법에 의해 형성한다. 그리고, 이 커패시터를 덮도록, 제1의 절연막(6)의 위에 제2의 절연막(11)을 통상의 CVD법에 의해 형성한다.Next, a capacitor including a lower electrode 7 of platinum, a ferroelectric film 8 of strontium titanate and an upper electrode 9 of platinum is formed on the first insulating film 6 by a conventional sputtering method. do. Then, the second insulating film 11 is formed on the first insulating film 6 so as to cover the capacitor by the usual CVD method.
다음에, 제1의 절연막(6) 및 제2의 절연막(11)에, 확산층(3)에 도달하는 콘택트구멍(12)과, 하부전극(7) 및 상부전극(9)에 도달하는 콘택트구멍(13)을 통상의 에칭기술을 사용해서 각각 형성한다. 그리고 콘택트구멍(12)의 내벽을 덮고, 또한 콘택트구멍(12)의 바닥부에서 확산층(3)과 접촉하도록, 또 콘택트구멍(12)의 내벽을 덮고, 또한 콘택트구멍(13)의 바닥부에서 하부전극(7) 및 상부전극(9)과 접촉하도록, 티탄-텅스텐 합금의 확산장벽층(17)을 형성한다. 이 확산장벽층(17)의 형성은, 티탄-텅스텐 합금의 타겟을 사용하여, 10Torr의 아르곤가스속에서 스퍼터링하는 방법으로 행하였다.Next, contact holes 12 reaching the diffusion layer 3 and contact holes reaching the lower electrode 7 and the upper electrode 9 are formed in the first insulating film 6 and the second insulating film 11. Each of (13) is formed using a conventional etching technique. Then, the inner wall of the contact hole 12 is covered, and the bottom part of the contact hole 12 is in contact with the diffusion layer 3, and the inner wall of the contact hole 12 is covered. A diffusion barrier layer 17 of titanium-tungsten alloy is formed to contact the lower electrode 7 and the upper electrode 9. The diffusion barrier layer 17 is formed by using a titanium-tungsten alloy target. Sputtering was carried out in Torr argon gas.
다음에, 확산장벽층(17)위에 알루미늄의 배선층(14),(15)을 통상의 스퍼터링법에 의해, 독립 및 선택적으로 형성한다. 배선층(14),(15)이 형성된 실피콘기판(1)을, 배선층(14)과 확산층(3)과의 계면을 오믹접촉으로 하기위하여, 수소를 함유한 불화성가스속에서 열처리한다. 그리고, 트랜지스터나 커패시터를 덮도록 실피콘기판(1)위의 전체면에, 질화실리콘의 보호막(16)을 형성한다.Next, the wiring layers 14 and 15 of aluminum are formed on the diffusion barrier layer 17 independently and selectively by the usual sputtering method. The silicon cone substrate 1 on which the wiring layers 14 and 15 are formed is heat-treated in a hydrogen-containing fluorine gas in order to make the interface between the wiring layer 14 and the diffusion layer 3 into ohmic contact. Then, a silicon nitride protective film 16 is formed on the entire surface of the silicon substrate 1 so as to cover the transistor or the capacitor.
이와같은 제조방법에 의해, 확산장벽층(17)의 두께를 150nm에서 350nm까지의 범위에서 바꾸고, 또한 열처리온도를 200℃에서 450℃의 범위에서 바꾼 여러 가지의 샘플을 제작하였다. 단, 확산장벽층(17)의 두께가 200nm이상의 샘플에 대해서는, 두께가 150nm에 도달한 시점에서 일단 스퍼터링을 중단해서 진공화 및 아르곤가스 도입을 행하고, 그후 스퍼터링을 재개해서 소정의 두께로 하는 방법에 의해서 확산장벽층(17)을 형성하였다.By this manufacturing method, various samples were prepared in which the thickness of the diffusion barrier layer 17 was changed in the range of 150 nm to 350 nm, and the heat treatment temperature was changed in the range of 200 ° C to 450 ° C. However, when the thickness of the diffusion barrier layer 17 is 200 nm or more, the sputtering process is once stopped and vacuuming and argon gas introduction are performed once the thickness reaches 150 nm, and then sputtering is resumed to a predetermined thickness. The diffusion barrier layer 17 was formed by this.
이를 샘플에 대해서, 하부전극(7) 및 상부전극(9)과 배선층(15)이 접촉하는 콘택트구멍(13)의 바닥부를 현미경에 의해 관찰해서 백금과 알루미늄과의 반응의 유무를 조사하고, 콘택트구멍(13)에 있어서의 도통불량을 조사하였다. 그 결과를 제2도에 표시한다.On the sample, the bottom portion of the contact hole 13 in which the lower electrode 7 and the upper electrode 9 and the wiring layer 15 contact each other was observed by a microscope to investigate the reaction between platinum and aluminum, and The conduction defect in the hole 13 was investigated. The results are shown in FIG.
제2도에 있어서, 종축은 콘택트구멍(13)에 있어서의 도통불량의 발생율을 포새하고, 횡축은 티탄-텅스텐 합금으로 이루어지는 확산장벽층(17)의 막두께를 표시한다. 단, 도통불량의 발생율은, 각 샘플에 있어서, 직경 3㎛의 콘택트구멍(13) 약 60개에 대하여, 도통불량이 발생한 콘택트구멍의 수의 비율로 표시하고 있다.In FIG. 2, the vertical axis marks the incidence of poor conduction in the contact hole 13, and the horizontal axis indicates the film thickness of the diffusion barrier layer 17 made of titanium-tungsten alloy. However, the incidence of poor conduction is expressed by the ratio of the number of contact holes in which poor conduction occurred with respect to about 60 contact holes 13 having a diameter of 3 µm in each sample.
이 결과로부터 명백한 바와같이, 어느 열처리온도에 있어서도, 확산장벽층(17)의 막두께가 150nm로부터 증가되면 도통불양의 발생율은 감소하는 경향이 있다.As is apparent from this result, at any heat treatment temperature, when the film thickness of the diffusion barrier layer 17 is increased from 150 nm, the occurrence rate of conduction defect tends to decrease.
그리고, 막두께가 200nm에서 300nm의 범위인때에 그 발생율은 거의 최소가 된다. 그러나 막두께가 300nm를 초과하면 발생율은 증가로 전환된다. 따라서, 확산장벽층(17)의 막두께는 200nm에서 300nm의 범위가 바람직하다.When the film thickness is in the range of 200 nm to 300 nm, the incidence rate is almost minimum. However, when the film thickness exceeds 300 nm, the incidence rate turns into an increase. Therefore, the film thickness of the diffusion barrier layer 17 is preferably in the range of 200 nm to 300 nm.
열처리온도에 대한 도통불량발생율의 변화는, 어느 막두께에 있어서도, 열처리온도가 450℃에서부터 낮아지면 그 발생율은 감소하는 경향이 있다. 그리고, 열처리온도가 420℃의 경우, 막두께가 200nm에서 300nm의 범위에 있을때는 발생율이 2%이하로 되어, 작은 발생율을 표시한다.The change in the occurrence rate of conduction defect with respect to the heat treatment temperature tends to decrease when the heat treatment temperature is lowered from 450 占 폚 at any film thickness. When the heat treatment temperature is 420 ° C., when the film thickness is in the range of 200 nm to 300 nm, the generation rate is 2% or less, and a small generation rate is displayed.
또, 열처리온도가 380℃이하가 되면, 막두께가 150nm에서 300nm의 범위에서 있는 경우는, 발생율은 1%이하가 되어, 극히 작아진다. 특히, 막두께가 200nm에서 300nm의 범위에 있는 경우는 발생율이 0%로 되어, 도통은 전혀 발생하지 않는다. 한편, 막두께가 350nm가 되면, 내부응력에 의한 것으로 생각되는 균열이 확산장벽층(17)에 다수발생하고, 도통불량을 일으킨 콘택트구멍이 인지되었다.When the heat treatment temperature is 380 ° C. or less, when the film thickness is in the range of 150 nm to 300 nm, the generation rate is 1% or less, which is extremely small. In particular, when the film thickness is in the range of 200 nm to 300 nm, the occurrence rate is 0%, and no conduction occurs at all. On the other hand, when the film thickness reached 350 nm, a large number of cracks, which were thought to be caused by internal stress, occurred in the diffusion barrier layer 17, and a contact hole causing a poor conduction was recognized.
또한, 열처리온도가 300℃보다 낮아지면 배선층(14)과 확산층(3)과의 계면이 오믹접촉으로 되지 않기 때문에, 300℃이상에서 열처리할 필요가 있다.In addition, when the heat treatment temperature is lower than 300 ° C, the interface between the wiring layer 14 and the diffusion layer 3 does not come into ohmic contact. Therefore, it is necessary to perform heat treatment at 300 ° C or higher.
다음에, 콘택트구멍(13)에 있어서의 확산장벽층(17)의 결정상태를 관찰한 결과를 제3도 및 제4도에 표시한다. 제3도는, 확산장벽층(17)의 막두께가 150nm의 것을 450℃에서 열처리한 샘플에 있어서 접속불량이 인지된 콘택트구멍(13)의 모식단면도이며, 제4도는, 막두께가 250nm의 것을 380℃에서 열처리한 샘플의 콘택트구멍(13)의 모식단면도이다.Next, the result of observing the crystal state of the diffusion barrier layer 17 in the contact hole 13 is shown in FIG. 3 and FIG. FIG. 3 is a schematic sectional view of the contact hole 13 in which the connection defect is recognized in the sample heat-treated at 450 ° C. for the film thickness of the diffusion barrier layer 17, and FIG. 4 shows the film thickness of 250 nm. It is a schematic cross section of the contact hole 13 of the sample heat-processed at 380 degreeC.
제3도에 표시한 바와같이, 접속불량이 발생한 콘택트구멍(13)에 있어서의 확산장벽층(17)에서는, 상부전극(9)의 표면에 대해서 수직방향으로 성장된 기동형상 결정구조가 관찰되었다. 이 확산장벽층(17)에서는, 수직방향을 따른 결정입계가 많고, 수평방향으로 평행한 결정입계가 극히 적다. 이 때문에, 백금과 알루미늄과의 확산이 결정입계를 따라서 용이하게 일어나고, 접속불량이 야기하는 Al2Pt가 생생된 것이라고 생각된다.As shown in FIG. 3, in the diffusion barrier layer 17 in the contact hole 13 in which the connection failure occurred, the starting crystal structure grown in the direction perpendicular to the surface of the upper electrode 9 was observed. . In this diffusion barrier layer 17, there are many grain boundaries along the vertical direction and very few grain boundaries parallel to the horizontal direction. For this reason, it is thought that the diffusion of platinum and aluminum easily occurs along the grain boundaries, and Al 2 Pt, which causes poor connection, is produced.
한편, 제4도에 표시한 바와같이, 접속불량이 없는 콘택트구멍(13)에 있어서는 확산장벽층(17)에서는, 상부전극(9)의 표면근처에 기동형상결정구조가 관찰되지만, 배선층(15)의 표면근처에서는 결정배량이 없는 입자형상결정구조의 층형상영역이 형성되어 있는 것이 확인되었다. 이 확산장벽층(17)에서는, 입자형상결정구조의 층형상영역이 형성되어 있기 때문에, 수평방향으로 평행한 결정입계가 매우 많다. 따라서, 이 수평방향으로 평행한 결정입계가 백금과 알루미늄과의 확산을 방해하기 때문에, Al2Pt가 생성되기 어렵다고 생각된다.On the other hand, as shown in FIG. 4, in the contact hole 13 without poor connection, in the diffusion barrier layer 17, the start-up crystal structure is observed near the surface of the upper electrode 9, but the wiring layer 15 It was confirmed that a layered region of a grain-shaped crystal structure without crystal grains was formed in the vicinity of the surface. In the diffusion barrier layer 17, since the layered region of the grain crystal structure is formed, there are many grain boundaries parallel to the horizontal direction. Therefore, it is thought that Al 2 Pt is hardly generated because the grain boundaries parallel to the horizontal direction prevent the diffusion of platinum and aluminum.
이와같이, 확산장벽층(17)내에 입자형상결정구조의 층형상영역이 형성하므로써, 콘택트구멍(13)에 있어서 접속불량의 발생을 현저하게 억제할 수 있다. 그리고, 이 입자형상결정구조의 층형상영역을 얻기 위해서는, 확산장벽층(17)의 두께를 200∼300nm로 하는 것이 바람직하며, 또, 소정의 두께에 도달할때까지 연속적으로 스퍼터링하는 것이 아니고 단속적으로 스퍼터링하는 쪽이 바람직하다. 또, 300∼420℃의 온도범위에서 열처리하면 Al2Pt가 생성되기 어렵고, 특히 380℃이하의 열처리온도에서는 Al2Pt가 매우 생성되기 어렵다.Thus, by forming the layered region of the grain crystal structure in the diffusion barrier layer 17, it is possible to significantly suppress the occurrence of connection failure in the contact hole 13. In order to obtain the layered region of the grain crystal structure, the thickness of the diffusion barrier layer 17 is preferably set to 200 to 300 nm, and is not intermittently sputtered until a predetermined thickness is reached. Sputtering is more preferable. Further, if heat treatment in the temperature range of 300~420 ℃ Al 2 Pt is hard to be generated, in particular, the heat treatment temperature below 380 ℃ Al 2 Pt is very difficult to produce.
다음에, 2층의 확산장벽층을 형성한 경우에 대해서, 제5도 및 제6도를 참조하면서 설명한다.Next, a case where two diffusion barrier layers are formed will be described with reference to FIGS. 5 and 6.
먼저, 상기의 실시예와 마찬가지의 방법에 의해, 실리콘기판(1)위에 트랜지스터 및 커패시터를 형성하고, 또 콘택트구멍(12),(13)을 가진 제2의 절연막(11)을 형성한다.First, a transistor and a capacitor are formed on the silicon substrate 1, and the second insulating film 11 having the contact holes 12 and 13 is formed by the same method as in the above embodiment.
다음에, 콘택트구멍(12)의 내벽을 덮고, 또한 콘택트구멍(12)의 바닥부에서 확산층(3)과 접촉하도록, 또 콘택트구멍(12)의 내벽을 덮고, 또한 콘택트구멍(13)의 바닥부에서 하부전극(7) 및 상부전극(9)과 접촉하도록, 티탄-텅스텐 합금으로 이루어지는 두께 100nm의 제1의 확산장벽층(17a)을 아르곤가스속 스퍼터링법에 의해 형성한다. 그리고, 이 실리콘기판을 대기속으로 꺼낸후, 별도의 스퍼터링장치에 삽입하고, 제1의 확산장벽층(17a)위에 이것과 동일한 합금으로 이루어진 두께 150nm의 제2의 확산장벽층(17b)을 스퍼터링법에 이해 형성한다.Next, the inner wall of the contact hole 12 is covered, the bottom part of the contact hole 12 is brought into contact with the diffusion layer 3, and the inner wall of the contact hole 12 is covered, and the bottom of the contact hole 13 is also covered. The first diffusion barrier layer 17a having a thickness of 100 nm made of titanium-tungsten alloy is formed by argon gas sputtering so as to contact the lower electrode 7 and the upper electrode 9 at the portion. After the silicon substrate is taken out into the atmosphere, the silicon substrate is inserted into a separate sputtering apparatus, and the second diffusion barrier layer 17b having a thickness of 150 nm made of the same alloy is sputtered on the first diffusion barrier layer 17a. Form understanding in law.
다음에, 제2의 확산장벽층(17b)위에 알루미늄의 배선층(14),(15)을 통상의 스퍼터링법에 의해, 독립 및 선택적으로 형성한다. 배선층(14),(15)이 형성된 실피콘기판(1)을 배선층(14)과 확산층(3)과의 계면을 오믹접촉 하기 위하여, 수소를 함유한 불활성가스분위기속 350℃의 온도에서 열처리한다. 그리고, 트랜지스터나 커패시터를 덮도록 실리콘기판(1)위의 전체면에, 질화실리콘의 보호막(16)을 형성한다.Next, the wiring layers 14 and 15 of aluminum are formed on the second diffusion barrier layer 17b independently and selectively by the usual sputtering method. The silicon cone substrate 1 on which the wiring layers 14 and 15 are formed is heat-treated at a temperature of 350 ° C. in an inert gas atmosphere containing hydrogen in order to make ohmic contact between the wiring layer 14 and the diffusion layer 3. . Then, a silicon nitride protective film 16 is formed on the entire surface of the silicon substrate 1 so as to cover the transistor or the capacitor.
이와같이 해서 제작된 샘플에서는, 콘택트구멍(13)에 있어서의 도통불량의 발생은 인지되지 않았다. 이 샘플의 콘택트구멍(13)에 있어서의 확산장벽층(17a),(17b)의 결정상태의 관찰결과를 제6도에 표시한다. 상부전극(9)에 접촉하는 제1의 확산장벽층(17a)은 기동형상결정구조를 가지나, 베선층(15)과 접촉하는 제2의 확산장벽층(17b)은 입자형성결정구조로 되어 있다.In the sample produced in this way, generation | occurrence | production of the conduction defect in the contact hole 13 was not recognized. Fig. 6 shows the observation results of the crystal states of the diffusion barrier layers 17a and 17b in the contact holes 13 of this sample. The first diffusion barrier layer 17a in contact with the upper electrode 9 has a moving shape crystal structure, while the second diffusion barrier layer 17b in contact with the wire layer 15 has a grain formation crystal structure. .
이와같이, 확산장벽층을 2회의 공정으로 나누어서 형성하므로서, 입자형성결정구조를 가진 확산장벽층을 용이하게 얻을 수 있다. 또, 확산장벽층을 3회이상의 공정으로 나누어서 형성해도, 입자형성결정구조를 가진 확산장벽층을 용이하게 얻을 수 있다.Thus, by forming the diffusion barrier layer in two steps, it is possible to easily obtain the diffusion barrier layer having the grain forming crystal structure. Further, even when the diffusion barrier layer is formed in three or more steps, the diffusion barrier layer having a grain forming crystal structure can be easily obtained.
또한, 제 1 및 제 2 의 확산장벽층(17a),(17b)의 합계 막두께는 200∼300nm의 범위가 바람직하다. 이 합계 막두께가 200보다 얇으면 제2의 확산장벽층(17b)에 의한 백금 및 알루미늄의 확산방지효과가 작고, 300nm를 초과하면 확산장벽층(17a),(17b)에 균열이 발생하기 쉽게 된다.In addition, the total film thickness of the first and second diffusion barrier layers 17a and 17b is preferably in the range of 200 to 300 nm. When the total film thickness is thinner than 200, the diffusion preventing effect of platinum and aluminum by the second diffusion barrier layer 17b is small, and when the total thickness exceeds 300 nm, cracks are likely to occur in the diffusion barrier layers 17a and 17b. do.
또, 제1의 확산장벽층(17a)의 막두께 보다 제2의 확산장벽층(17b)의 막두께를 두껍게 하는 쪽이, 제2의 확산장벽층(17b)의 막두께가 확산장벽층(17a),(17b)의 합계 막두께의 1/2∼2/3의 범위에 있으면, 보다 적절하다. 예를 들면, 합계 막두께가 200∼300nm일때, 제2의 확산장벽층(17b)의 막두께는 100∼200nm인 것이 바람직하다.Further, the thickness of the second diffusion barrier layer 17b is greater than that of the first diffusion barrier layer 17a, so that the thickness of the second diffusion barrier layer 17b is the diffusion barrier layer ( If it exists in the range of 1/2 to 2/3 of the total film thickness of 17a) and (17b), it is more suitable. For example, when the total film thickness is 200 to 300 nm, the film thickness of the second diffusion barrier layer 17b is preferably 100 to 200 nm.
열처리온도는, 이 2층의 확산장벽층을 형성하였을 경우도, 420℃를 초과하면 Al2Pt가 생성되기 쉽게 되기 때문에, 300∼420℃의 온도범위가 적절하다.In the case where the two-layer diffusion barrier layer is formed, when the heat treatment temperature exceeds 420 ° C, since Al 2 Pt is easily generated, a temperature range of 300 to 420 ° C is appropriate.
특히 380℃이하의 경우는, Al2Pt가 매우 생성되기 어렵다.In particular, below 380 ℃ is, Al 2 P t is very difficult to produce.
본 발명은, 상기 실시예에 한정되는 것은 아니며, 여러 가지의 변형예가 가능한 것을 말할것도 없다. 예를들면, 바람직한 일실시예로서 확산장벽층의 재료로 티탄-텅스텐 합금을 사용한 예를 표시하였으나, 티탄-텅스텐 대신에 질화티탄-텅스텐 또는 질화티탄을 사용할 수도 있다. 또, 확산장벽층의 형성을 스퍼터링법을 사용한 예를 표시하였으나, 전자빔중착법을 사용해도 된다.This invention is not limited to the said Example, Needless to say that various modifications are possible. For example, an example in which a titanium-tungsten alloy is used as the material of the diffusion barrier layer as a preferred embodiment is shown. Instead of titanium-tungsten, titanium nitride-tungsten or titanium nitride may be used. Moreover, although the example which used the sputtering method was shown for formation of a diffusion barrier layer, you may use the electron beam deposition method.
상기 실시예에서는, 배선층의 재료로 알루미늄을 사용하였으나, 알루미늄을 주체로 하는 합금을 사용해도 된다. 또, 커패시터의 전극재료로서 백금을 사용하였으나, 백금을 주체로한 합금을 사용하는 것도 가능하다. 또, 커패시터의 유전체막으로 티탄산스트론튬계재료를 사용한 예를 표시하였으나, 티탄산바륨, PZT, PLZT등의 고유전압을 가진 금속산화물재료를 사용해도 된다.In the above embodiment, aluminum is used as the material of the wiring layer, but an alloy mainly composed of aluminum may be used. In addition, although platinum is used as the electrode material of the capacitor, it is also possible to use an alloy mainly composed of platinum. In addition, although an example in which a strontium titanate-based material is used as the dielectric film of the capacitor is shown, a metal oxide material having a specific voltage such as barium titanate, PZT, PLZT, or the like may be used.
따라서, 본 발명의 참정신 및 범위내에 존재하는 변형예는, 모두 다음의 특허청구의 범위에 포함되는 것이다.Accordingly, all modifications existing within the spirit and scope of the present invention are included in the following claims.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100505605B1 (en) * | 1998-06-15 | 2005-09-26 | 삼성전자주식회사 | Method for forming capacitor having metal-insulator-metal structure |
Families Citing this family (55)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2137928C (en) * | 1992-07-04 | 2002-01-29 | Christopher David Dobson | A method of treating a semiconductor wafer |
| US5858880A (en) * | 1994-05-14 | 1999-01-12 | Trikon Equipment Limited | Method of treating a semi-conductor wafer |
| JP3599199B2 (en) * | 1994-08-31 | 2004-12-08 | 富士通株式会社 | Method for manufacturing semiconductor device having multilayer wiring |
| EP0740347B1 (en) * | 1995-04-24 | 2002-08-28 | Infineon Technologies AG | Semiconductor memory structure, using a ferroelectric dielectric and method of formation |
| JP2867934B2 (en) * | 1996-01-04 | 1999-03-10 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| US5716875A (en) * | 1996-03-01 | 1998-02-10 | Motorola, Inc. | Method for making a ferroelectric device |
| US6815762B2 (en) * | 1997-05-30 | 2004-11-09 | Hitachi, Ltd. | Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines |
| JP2954877B2 (en) * | 1996-06-18 | 1999-09-27 | 松下電子工業株式会社 | Manufacturing method of capacitive element |
| SE520173C2 (en) * | 1997-04-29 | 2003-06-03 | Ericsson Telefon Ab L M | Process for manufacturing a capacitor in an integrated circuit |
| JPH1117124A (en) * | 1997-06-24 | 1999-01-22 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JP3456391B2 (en) * | 1997-07-03 | 2003-10-14 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| EP0893832A3 (en) | 1997-07-24 | 1999-11-03 | Matsushita Electronics Corporation | Semiconductor device including a capacitor device and method for fabricating the same |
| US5910880A (en) * | 1997-08-20 | 1999-06-08 | Micron Technology, Inc. | Semiconductor circuit components and capacitors |
| US6184551B1 (en) * | 1997-10-24 | 2001-02-06 | Samsung Electronics Co., Ltd | Method of forming integrated circuit capacitors having electrodes therein that comprise conductive plugs |
| US6569746B2 (en) | 1997-10-30 | 2003-05-27 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit capacitors having electrodes therein that comprise conductive plugs |
| JP3165093B2 (en) | 1997-11-13 | 2001-05-14 | 松下電子工業株式会社 | Semiconductor device and method of manufacturing the same |
| US6329681B1 (en) * | 1997-12-18 | 2001-12-11 | Yoshitaka Nakamura | Semiconductor integrated circuit device and method of manufacturing the same |
| US6320213B1 (en) * | 1997-12-19 | 2001-11-20 | Advanced Technology Materials, Inc. | Diffusion barriers between noble metal electrodes and metallization layers, and integrated circuit and semiconductor devices comprising same |
| KR100252854B1 (en) | 1997-12-26 | 2000-04-15 | 김영환 | Semiconductor device and manufacturing method thereof |
| KR100465854B1 (en) * | 1997-12-27 | 2005-05-20 | 주식회사 하이닉스반도체 | A method of forming the lower electrode barrier film of a high dielectric capacitor |
| US6162744A (en) * | 1998-02-28 | 2000-12-19 | Micron Technology, Inc. | Method of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layers |
| US6191443B1 (en) | 1998-02-28 | 2001-02-20 | Micron Technology, Inc. | Capacitors, methods of forming capacitors, and DRAM memory cells |
| US6229167B1 (en) * | 1998-03-24 | 2001-05-08 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US6156638A (en) | 1998-04-10 | 2000-12-05 | Micron Technology, Inc. | Integrated circuitry and method of restricting diffusion from one material to another |
| US6730559B2 (en) | 1998-04-10 | 2004-05-04 | Micron Technology, Inc. | Capacitors and methods of forming capacitors |
| US6165834A (en) * | 1998-05-07 | 2000-12-26 | Micron Technology, Inc. | Method of forming capacitors, method of processing dielectric layers, method of forming a DRAM cell |
| US6255186B1 (en) | 1998-05-21 | 2001-07-03 | Micron Technology, Inc. | Methods of forming integrated circuitry and capacitors having a capacitor electrode having a base and a pair of walls projecting upwardly therefrom |
| US6232131B1 (en) * | 1998-06-24 | 2001-05-15 | Matsushita Electronics Corporation | Method for manufacturing semiconductor device with ferroelectric capacitors including multiple annealing steps |
| US5918120A (en) * | 1998-07-24 | 1999-06-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines |
| JP3533968B2 (en) | 1998-12-22 | 2004-06-07 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| KR100280288B1 (en) * | 1999-02-04 | 2001-01-15 | 윤종용 | Method for fabricating capacitor of semiconcuctor integrated circuit |
| KR100349642B1 (en) * | 1999-06-28 | 2002-08-22 | 주식회사 하이닉스반도체 | Ferroelectric random access memory device and method for forming the same |
| JP3353833B2 (en) * | 1999-07-09 | 2002-12-03 | 日本電気株式会社 | Semiconductor device and method of manufacturing the same |
| KR100326253B1 (en) * | 1999-12-28 | 2002-03-08 | 박종섭 | Method for forming capacitor in semiconductor device |
| US7005695B1 (en) | 2000-02-23 | 2006-02-28 | Micron Technology, Inc. | Integrated circuitry including a capacitor with an amorphous and a crystalline high K capacitor dielectric region |
| JP3449333B2 (en) | 2000-03-27 | 2003-09-22 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| JP3480416B2 (en) | 2000-03-27 | 2003-12-22 | セイコーエプソン株式会社 | Semiconductor device |
| JP2001284526A (en) * | 2000-03-28 | 2001-10-12 | Nec Yamagata Ltd | Mim capacitor for semiconductor integrated circuit |
| JP3450262B2 (en) * | 2000-03-29 | 2003-09-22 | Ｎｅｃエレクトロニクス株式会社 | Circuit manufacturing method and circuit device |
| JP4390367B2 (en) * | 2000-06-07 | 2009-12-24 | Ｎｅｃエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| US6750113B2 (en) * | 2001-01-17 | 2004-06-15 | International Business Machines Corporation | Metal-insulator-metal capacitor in copper |
| KR100410716B1 (en) * | 2001-03-07 | 2003-12-18 | 주식회사 하이닉스반도체 | FeRAM capable of connecting bottom electrode to storage node and method for forming the same |
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| JP2003204043A (en) * | 2001-10-24 | 2003-07-18 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
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| JP2005116756A (en) * | 2003-10-07 | 2005-04-28 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
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| DE102007035834A1 (en) * | 2007-07-31 | 2009-02-05 | Advanced Micro Devices, Inc., Sunnyvale | Semiconductor device with locally increased electromigration resistance in a connection structure |
| US8883592B2 (en) * | 2011-08-05 | 2014-11-11 | Silicon Storage Technology, Inc. | Non-volatile memory cell having a high K dielectric and metal gate |
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| CN104746006B (en) * | 2013-12-31 | 2017-06-06 | 北京北方微电子基地设备工艺研究中心有限责任公司 | The magnetron sputtering preparation process of the TiW films of adjustable TiW membrane stresses |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4141022A (en) * | 1977-09-12 | 1979-02-20 | Signetics Corporation | Refractory metal contacts for IGFETS |
| US5266829A (en) * | 1986-05-09 | 1993-11-30 | Actel Corporation | Electrically-programmable low-impedance anti-fuse element |
| US5005102A (en) * | 1989-06-20 | 1991-04-02 | Ramtron Corporation | Multilayer electrodes for integrated circuit capacitors |
| JPH0493065A (en) * | 1990-08-09 | 1992-03-25 | Seiko Epson Corp | Structure of semiconductor device |
| JP3185220B2 (en) * | 1990-09-28 | 2001-07-09 | セイコーエプソン株式会社 | Semiconductor device |
| EP0513894B1 (en) * | 1991-05-08 | 1996-08-28 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device comprising a capacitor with a ferroelectric dielectric, and semiconductor device comprising such a capacitor |
| US5191510A (en) * | 1992-04-29 | 1993-03-02 | Ramtron International Corporation | Use of palladium as an adhesion layer and as an electrode in ferroelectric memory devices |
| JP2762851B2 (en) * | 1992-07-27 | 1998-06-04 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP3319869B2 (en) * | 1993-06-24 | 2002-09-03 | 三菱電機株式会社 | Semiconductor storage device and method of manufacturing the same |
| DE69433244T2 (en) * | 1993-08-05 | 2004-07-29 | Matsushita Electric Industrial Co., Ltd., Kadoma | Manufacturing method for semiconductor device with capacitor of high dielectric constant |
| US5443688A (en) * | 1993-12-02 | 1995-08-22 | Raytheon Company | Method of manufacturing a ferroelectric device using a plasma etching process |
| JP2875733B2 (en) * | 1994-02-15 | 1999-03-31 | 松下電子工業株式会社 | Method for manufacturing semiconductor device |
-
1994
- 1994-06-28 JP JP6146265A patent/JP3045928B2/en not_active Expired - Fee Related
-
1995
- 1995-06-01 DE DE69522514T patent/DE69522514T2/en not_active Expired - Fee Related
- 1995-06-01 EP EP95108423A patent/EP0690507B1/en not_active Expired - Lifetime
- 1995-06-20 US US08/492,913 patent/US5627391A/en not_active Expired - Fee Related
- 1995-06-24 KR KR1019950017339A patent/KR100187601B1/en not_active IP Right Cessation
- 1995-06-28 CN CN95107541A patent/CN1076875C/en not_active Expired - Fee Related
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1997
- 1997-02-19 US US08/803,144 patent/US5837591A/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100505605B1 (en) * | 1998-06-15 | 2005-09-26 | 삼성전자주식회사 | Method for forming capacitor having metal-insulator-metal structure |
Also Published As
| Publication number | Publication date |
|---|---|
| DE69522514T2 (en) | 2002-04-25 |
| US5627391A (en) | 1997-05-06 |
| KR960002804A (en) | 1996-01-26 |
| JPH0817759A (en) | 1996-01-19 |
| EP0690507A1 (en) | 1996-01-03 |
| JP3045928B2 (en) | 2000-05-29 |
| CN1128406A (en) | 1996-08-07 |
| DE69522514D1 (en) | 2001-10-11 |
| CN1076875C (en) | 2001-12-26 |
| US5837591A (en) | 1998-11-17 |
| EP0690507B1 (en) | 2001-09-05 |
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