KR0172247B1 - Thin film planation method using cmp - Google Patents
Thin film planation method using cmp Download PDFInfo
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- KR0172247B1 KR0172247B1 KR1019950066071A KR19950066071A KR0172247B1 KR 0172247 B1 KR0172247 B1 KR 0172247B1 KR 1019950066071 A KR1019950066071 A KR 1019950066071A KR 19950066071 A KR19950066071 A KR 19950066071A KR 0172247 B1 KR0172247 B1 KR 0172247B1
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000010409 thin film Substances 0.000 title claims abstract description 14
- 238000005498 polishing Methods 0.000 claims abstract description 56
- 239000002002 slurry Substances 0.000 abstract description 16
- 238000005530 etching Methods 0.000 abstract description 5
- 238000000427 thin-film deposition Methods 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract description 3
- 238000007517 polishing process Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 11
- 230000005489 elastic deformation Effects 0.000 description 6
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000006837 decompression Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000009828 non-uniform distribution Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000779 smoke Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/005—Control means for lapping machines or devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
본 발명은 씨엠피를 이용한 박막 평탄화 방법에 관한 것으로, 본 발명에 의한 평탄화 방법은, 폴리싱헤드의 압력을 제1범위로 가하여 웨이퍼를 회전시키는 제1단계와, 상기 제1단계 후 상기 폴리싱헤드의 압력을 상기 제1범위와 다른 압력으로 가변시키는 제2단계와, 상기 제2단계 후 상기 폴리싱헤드의 압력을 다시 상기 제1범위로 가변시키는 제3단계로 이루어지는 것과 같이 연마공정중에 폴리싱헤드의 압력을 반복적으로 증감시키면서 CMP공정을 진행하여 일측에 과식각되는 디싱(sidhing) 현상 등을 감소시켰으므로, 공정 후 평탄성이 증가되어 포트공정이 용이해지고, CMP공정을 보강하기 위해 박막증착, 식각등과 같은 공정의 추가나, 새로운 패드나 슬러리를 개발할 필요없이 기존의 CMP 장비 및 소모품을 그대로 적용할 수 있어 공정단가가 절감되고, 연마의 균일성 및 재현성이 향상되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.The present invention relates to a thin film planarization method using CMP, and the planarization method according to the present invention includes a first step of rotating a wafer by applying a pressure of a polishing head to a first range, and after the first step, A pressure of the polishing head during the polishing process, comprising a second step of varying the pressure to a pressure different from the first range, and a third step of varying the pressure of the polishing head back to the first range after the second step. Repeatedly increasing and decreasing the CMP process to reduce the phenomenon of overetching on one side, so that the flatness is increased after the process, making the pot process easier, and the thin film deposition, etching, etc. to reinforce the CMP process. Existing CMP equipment and consumables can be applied without the need to add the same process or develop new pads or slurries. Town in the uniformity and reproducibility is improved thereby improving the reliability of the process yield and device operation.
Description
제1도는 씨엠피 장비를 설명하기 위한 개략도.1 is a schematic diagram for explaining the CMP equipment.
제2도는 패드의 탄성변형을 설명하기 위한 개략도.2 is a schematic diagram for explaining the elastic deformation of the pad.
제3도는 회전하는 패드에서 웨이퍼로 유입되는 슬러리의 흐름도.3 is a flow chart of a slurry entering a wafer from a rotating pad.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 슬러리 2 : 폴리싱패드1 slurry 2 polishing pad
3 : 웨이퍼 3 : 연마패드3: wafer 3: polishing pad
5 : 회전테이블5: rotating table
본 발명은 화학-기계적 연마장치(Chemical Mechanical Planarizer)를 사용하는 화학-기계적 연마(Chemical Mechanical Polishing:이하 CMP라 칭함)를 이용하는 박막 평탄화 방법에 관한 것으로, 특히 박막의 평탄화와 균일성을 향상시키도록 하는 CMP를 이용한 박막 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film planarization method using chemical mechanical polishing (CMP) using a chemical mechanical planarizer, and in particular, to improve flatness and uniformity of a thin film. It relates to a thin film planarization method using CMP.
집적도가 낮은 반도체소자는 단차가 작아 각 도전층들의 패턴닝이나 평탄화에 별다른 문제점이 없었으나, 소자가 고집적화되어 각층들간의 단차 및 적층되는 막의 수가 증가되면 소자의 제조 공정에서 나칭이나 단선 등의 불량들이 발생하게 되며, 이를 방지하기 위하여 적층막들의 상부를 평탄화하는 평탄화 공정이 공정수율 및 소자의 신뢰성에 중요한 영향을 미치게 된다.The low integration semiconductor device has little problem in patterning or planarization of each conductive layer due to its small step. However, when the device is highly integrated and the number of steps and stacked films between the layers increases, defects such as naming and disconnection occur in the manufacturing process of the device. In order to prevent this, the planarization process of planarizing the top of the stacked layers has an important effect on the process yield and the reliability of the device.
현재 1M DRAM 이상의 소자에서는 다량의 불순물을 함유하여 유동성이 우수하고 화학기상증착(chemical vapor deposition;이하 CVD라 칭함) 방법으로 형성되어 단차피복성이 우수한 비.피.에스.지(Boro Phospho Silicate Glass;이하 BPSG라 칭함)나 테오스(Tetra etchyl orthor silicate; 이하 TEOS라 칭함) 산화막 등을 평탄화막으로 널리 사용되고 있다. 그러나 상기의 평탄화막들은 우수한 유동성에도 불구하고 평탄화의 정도에 한계가 있으며, 불순물이 다량으로 포함되어 있어 또 다른 문제점을 갖고 있다.Currently, 1M DRAM or more devices contain a large amount of impurities, and are formed by chemical vapor deposition (hereinafter referred to as CVD) method, so that they have excellent step coverage. Boro Phospho Silicate Glass ; Hereinafter referred to as BPSG) and Teos (Tetra etchyl orthor silicate; TEOS) oxide films and the like are widely used as planarization films. However, the above planarization films have a limit in the degree of planarization in spite of their excellent fluidity, and have another problem because they contain a large amount of impurities.
또한 256M DRAM 이상의 초고집적 소자에서는 평탄화막의 표면을 기계적으로 갈아내는 CMP 방법이 연구되고 있다.In addition, CMP methods for mechanically grinding the surface of a planarization film have been studied in ultra-high density devices of 256M DRAM or more.
상기 CMP공정은 박막적층으로 인해 발생하는 단차를 완화시켜 이후 포토공정에 필요한 DOF(초점심도)마진을 확보하기 위해 도입된 평탄화공정이다.The CMP process is a planarization process introduced in order to alleviate the step caused by the thin film stack and to secure the DOF (focal depth) required for the photo process.
제1도는 CMP 장비의 구성을 도시하고 있다. 제1도에서 도면부호 1은 현탁액으로서의 슬러리(slurry)를 나타낸다. 그리고 도면부호 2는 웨이퍼(3)를 회전시키는 폴리싱헤드이다. 그리고 도면부호 4는 연마표로서의 연마패드이며, 도면부호 5는 회전테이블이다.1 shows the configuration of CMP equipment. Reference numeral 1 in FIG. 1 denotes a slurry as a suspension. Reference numeral 2 denotes a polishing head for rotating the wafer 3. Reference numeral 4 denotes a polishing pad as a polishing table, and reference numeral 5 denotes a rotary table.
제1도에서 폴리싱헤드(2)는 특정 회전수를 가지면서 웨이퍼(3)를 연마패드(4)를 통하여 연마하는 작업을 수행하게 된다.In FIG. 1, the polishing head 2 performs a polishing operation of the wafer 3 through the polishing pad 4 at a specific rotational speed.
그러나 제1도와 같은 작업공정하에서는 다음과 같은 문제점이 발생한다. 즉, 도면 제2도에서 도시된 바와 같이, 연마작업중에 웨이퍼(3)의 표면의 패턴형상에 따라 연마패드(4)가 탄성변형을 일으킴으로써 연마대상인 블록한 스텝들 뿐만 아니라 연마되지 않아야 할 오목한 부분까지 일부 연마되어 결과적으로 원하는 만큼 단차를 낮추지 못하는 한계가 존재한다.However, the following problems occur under the working process as shown in FIG. That is, as shown in FIG. 2, during the polishing operation, the polishing pad 4 causes elastic deformation according to the pattern shape of the surface of the wafer 3 so that not only the blocked steps that are to be polished but also the recesses that should not be polished There is a limitation that partly polished up to a part and consequently cannot lower the step as desired.
연마포로서의 연마패드(4)의 탄성변형은 연마포를 제작하는 재료가 폴리우레탄 등의 탄성변형체이어서 새로운 재질을 공급하지 않는 한 개선이 어렵게 된다.The elastic deformation of the polishing pad 4 as the polishing cloth is difficult to improve unless the material for making the polishing cloth is an elastic deformation body such as polyurethane, so that no new material is supplied.
이러한 CMP 자체의 문제점과는 별도로, 반도체소자의 평탄성의 향상을 위하여 새로운 식각억제용 박막증착 및 식각공정 등을 부가하거나 포토레지스터를 식각베리어로 사용하는 등 다양한 방법들이 소개되고 있다. 그러나 CMP 공정이 기존의 평탄화공정인 BPSG, SOG 등이 필요로 하는 박막증착이나 열처리 등의 공정수를 줄이기 위해 도입되었다는 점에 비추어볼 때 공정이 부가되는 방법은 기본적으로 바람직하지 못하다.Apart from the problems of the CMP itself, various methods have been introduced, such as adding a new etching inhibiting thin film deposition and etching process or using a photoresist as an etching barrier to improve flatness of semiconductor devices. However, in view of the fact that the CMP process was introduced to reduce the number of processes such as thin film deposition and heat treatment required by the conventional planarization processes such as BPSG and SOG, the method of adding the process is basically undesirable.
상기와 같은 종래 기술에 따른 CMP를 이용한 박막 평탄화 방법에서는 연마패드(4)가 부착된 회전테이블(5)이 회전하고 웨이퍼(3)를 부착한 폴리싱헤드(2)가 역시 회전하면서 웨이퍼(3)를 연마패드(4)면에 밀착시켜 연마시키는데 이 과정에서 연마패드(4)의 중앙부분에 공급되는 슬러리(1)가 웨이퍼(3) 연마면에도 골고루 분포되도록 하는 장치가 없어, 웨이퍼(3) 연마면의 패턴형상에 따라서 슬러리(1)의 웨이퍼(3) 표면분포가 달라질 수 있어 연마의 균일성 및 재현성을 저하시켜 공정수율 및 소자 동작의 신뢰성을 떨어뜨리는 문제점이 있다.In the thin film planarization method using the CMP according to the related art, the rotating table 5 with the polishing pad 4 rotates and the polishing head 2 with the wafer 3 rotates also rotates the wafer 3. Is adhered to the polishing pad 4 surface and polished. In this process, there is no device for the slurry 1 supplied to the center portion of the polishing pad 4 to be evenly distributed on the polishing surface of the wafer 3, so that the wafer 3 According to the pattern of the polishing surface, the surface distribution of the wafer 3 of the slurry 1 may be changed, thereby lowering the uniformity and reproducibility of polishing, thereby degrading process yield and reliability of device operation.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 CMP 공정의 한계를 새로운 재료의 도입이나 공정의 추가없이 있는 그대로의 장비로 극복하여 연마의 균일성 및 재현성을 향상시켜 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 CMP를 이용한 박막 평탄화방법을 제공함에 있다.The present invention is to solve the above problems, the object of the present invention is to overcome the limitations of the CMP process with the equipment as it is without the introduction of new materials or the addition of a process to improve the uniformity and reproducibility of the polishing process yield And it provides a thin film planarization method using a CMP that can improve the reliability of device operation.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 CMP를이용한 박막평탄화 방법의 특징은, 연마공정중에 폴리싱헤드의 압력을 반복적으로 증감시켜 평탄도와 균일성을 동시에 향상시킴에 있다.A feature of the thin film flattening method using the CMP according to the present invention for achieving the above object is to improve the flatness and uniformity at the same time by repeatedly increasing and decreasing the pressure of the polishing head during the polishing process.
이하, 본 발명에 따른 CMP를 이용한 박막 평탄화방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a thin film planarization method using CMP according to the present invention will be described in detail with reference to the accompanying drawings.
일반적으로 CMP공정에서는 폴리싱헤드의 압력, 폴리싱헤드의 회전수, 연마테이블 회전수, 헤드의 배면압력(back pressure), 슬러리 공급량 등의 변수들이 있는데 그 중 가장 중요한 변수는 폴리싱헤드의 압력이다. 이 폴리싱헤드의 압력을 낮게 해주어야 연마패드의 탄성변형이 감소하여 평탄화 성능이 개선되는 것으로 알려져 있다. 반면 웨이퍼 내에서의 연마균일성을 개선하기 위해서는 폴리싱헤드의 압력을 증가시켜야 한다. 하지만 기존의 CMP공정은 사전에 선택한 한가지 압력에서만 공정을 진행하므로 평탄도와 균일성을 동시에 좋게 하기가 불가능하다.In general, in the CMP process, there are variables such as the pressure of the polishing head, the number of revolutions of the polishing head, the number of revolutions of the polishing table, the back pressure of the head, the slurry feed amount, and the most important variable is the pressure of the polishing head. When the pressure of the polishing head is lowered, it is known that the elastic deformation of the polishing pad is reduced to improve the flattening performance. On the other hand, to improve the polishing uniformity in the wafer, the pressure of the polishing head must be increased. However, the existing CMP process is performed only at one pressure selected in advance, so it is impossible to improve flatness and uniformity at the same time.
본 발명을 이러한 점을 고려하여 연막공정중에 폴리싱헤드의 압력을 반복적으로 증감시켜 평탄도와 균일성을 동시에 향상시킬 수가 있게 된다.In view of this point of the present invention, the pressure of the polishing head may be repeatedly increased or decreased during the smoke screening process to improve flatness and uniformity at the same time.
제1도 내지 제3도를 연관시켜 설명하면 다음과 같다.The following description will be made with reference to FIGS. 1 to 3.
적용가능한 박막은 주로 평탄도를 요하는 다결정실리콘 배선 또는 금속배선의 층간절연막으로서, 예를 들어 저압 CVD(Low Pressure CVD;이하 LPCVD라 칭함), 플라즈마유도 CVD(Plasma Enhanced CVD;이하 PE-CVD라 칭함), 상압 CVD(Atmospare Pressure;이하 AP-CVD라 칭함) 등의 방법으로 증착하여 TEOS나 SiH4등의 원료 가스를 사용한 산화막이나 불순물이 함유되거나 함유되지 않는(doped or undoped) 실리케이트 그라스(silicate glass), 또는 에스. 오지(Spin On Glass;이하 SOG라 칭함) 등이 포함된다. 이들 대상 산화막에 맞추어 연마시작전에 선정한 조건으로 헤드의 회전수, 테이블 회전수, 슬러리 공급량을 설정한다.Applicable thin films are mainly interlayer insulating films of polycrystalline silicon wiring or metal wiring requiring flatness, for example, low pressure CVD (hereinafter referred to as LPCVD) and plasma enhanced CVD (hereinafter referred to as PE-CVD). And oxide films or doped or undoped silicate glasses using source gas such as TEOS or SiH 4 by deposition by means of atmospheric pressure CVD (Atmospare Pressure (hereinafter referred to as AP-CVD)). glass, or s. Spin On Glass (hereinafter referred to as SOG) and the like. The rotation speed of the head, the rotation speed of the table, and the supply amount of slurry are set in accordance with the conditions selected before the start of polishing in accordance with these target oxide films.
폴리싱헤드의 압력은 CMP 장치에 설치된 소프트웨어상 조작이나 수동조작으로 다음과 같이 조절한다.The pressure of the polishing head is adjusted as follows by software operation or manual operation installed in the CMP apparatus.
먼저, 폴리싱헤드(2)가 0∼10psi의 압력범위에서 작동하게 하며, 연마하고자 하는 웨이퍼(3)가 연마패드(4)에 접촉한 시점에서 5∼30초간은 폴리싱헤드의 압력이 7∼10psi가 되게 한다. 이는 연마초기에 균일성을 확보하기 위해서이다.First, the polishing head 2 operates in a pressure range of 0 to 10 psi, and the pressure of the polishing head is 7 to 10 psi for 5 to 30 seconds when the wafer 3 to be polished is in contact with the polishing pad 4. To become. This is to ensure uniformity at the beginning of polishing.
그 다음 1∼4psi 정도의 낮은 압력과 6∼9psi 정도의 높은 압력 순으로 번갈아 가면서 연마하되, 각 압력을 가하는 시간은 5∼30초간 단위로 하고 시간비율은 3:1∼1:3 정도가 되도록 한다.Then, grind in the order of low pressure of 1 ~ 4psi and high pressure of 6 ~ 9psi, but apply each pressure for 5 ~ 30 seconds and make time ratio of 3: 1 ~ 1: 3. do.
구체적인 공정을 예를 들면, 연마하고자 하는 두께아 6000Å, 연마속도가 7psi에서 50Å/sec, 3psi에서 20Å/sec일 경우, 시간비율 1:1을 선택하면, 초기 30초간 7psi에서 1500Å, 이후 3psi에서 20초간에 400Å, 7psi에서 20초간 1000Å씩하여 각각 3psi 3회로 약 1200Å, 7psi 3회로 약 3000Å 정도가 제거되어 대략 나머지 4200Å이 끝난다.For example, if the thickness to be polished is 6000Å, the polishing rate is 50Å / sec at 7psi, and 20, / sec at 3psi, if time ratio 1: 1 is selected, 1500Å at 7psi for the first 30 seconds and then at 3psi 20 s at 400 Å, 7 psi at 20 s for 20 s, 3 psi 3 circuits of about 1200 Å and 7 psi 3 circuits of about 3000 제거 are removed, leaving approximately 4200 Å.
가압 및 감압 도중에 연마되는 양도 고려하여 시간을 책정한다. 위와 같이 하면 공정시간 중 일부 시간동안에는 연마패드(4)가 받는 압력이 낮아져서 패드(4)의 변형이 감소하고, 따라서 볼록한 부분만 집중적으로 연마되어 평탄화가 가능하고, 헤드압력이 높은 시간동안에는 연마균일성이 향상된다.The amount of time to be polished during pressurization and decompression is also taken into account. In this case, the pressure applied to the polishing pad 4 is reduced during some time of the process time, so that the deformation of the pad 4 is reduced. Therefore, only the convex portion is polished intensively and flattening is possible. Sex is improved.
여기서 가압속도는 초당 2∼3psi 정도로 빠르게, 감압속도는 초당 1∼2psi 정도로 느리게 조절한다.Here, the pressurization rate is adjusted to about 2 to 3 psi per second and the decompression rate is adjusted to about 1 to 2 psi per second.
한편 높은 압력과 낮은 압력 사이에는 0psi가 되는 시점이 있도록 한다. 이는 0psi의 순간에 웨이퍼(3)가 접촉하는 패드(4)면에 슬러리(10)가 균일하게 공급되도록 하기 위함이다. 여기서 웨이퍼(3)가 패드(4)에 접촉되어 있는 동안에는 슬러리(1)가 웨이퍼 전면에 일시에 접촉되는 것이 아니라, 제3도에 도시된 바와 같이 웨이퍼(3)의 둘레 중 일부만을 통해서 웨이퍼(3)에 유입될 수 있어 실제 접촉면 내부에서 슬러리(1)의 유동은 완전히 균일하다고 볼 수 없어 불균일한 연마의 가능성이 있기 때문이다.On the other hand, there should be a point of 0 psi between high and low pressure. This is for the slurry 10 to be uniformly supplied to the pad 4 surface which the wafer 3 contacts at the instant of 0psi. Here, while the wafer 3 is in contact with the pad 4, the slurry 1 is not in contact with the front surface of the wafer at a time, but only through a portion of the circumference of the wafer 3 as shown in FIG. 3. This is because the flow of the slurry 1 inside the actual contact surface may not be considered completely uniform because it may flow into 3), and there is a possibility of uneven polishing.
폴리싱헤드(2)의 압력이 0이 되면 패드(4)의 변형은 없어지고 웨이퍼(3)와 패드(4)의 표면장력만이 남는데 이때 슬러리(1)를 충분히 함유한 패드면이 웨이퍼(3) 아래로 오고, 다시 가압할 때 이 슬러리(1)가 일시에 웨이퍼(3) 표면에 접촉된다. 따라서 슬러리(1)의 불균일한 분포에 의한 불균일 연마현상을 억제할 수 있다.When the pressure of the polishing head 2 reaches zero, the deformation of the pad 4 is eliminated and only the surface tension of the wafer 3 and the pad 4 remains. At this time, the pad surface sufficiently containing the slurry 1 is the wafer 3. The slurry 1 comes into contact with the surface of the wafer 3 at a time when it comes down and pressurizes again. Therefore, the nonuniform polishing phenomenon by the nonuniform distribution of the slurry 1 can be suppressed.
상기의 본 발명은 배선간 산화막의 평탄화 뿐만 아니라 금속배선 자체의 평탄화, 즉 W-플러그, W-비아 콘택후 평탄화, Cu의 데마씬(damascene)법 등에도 적용할 수 있다.The present invention is applicable not only to the planarization of the oxide film between the wirings, but also to the planarization of the metal wiring itself, that is, the planarization after the W-plug, the W-via contact, the damascene method of Cu, and the like.
또한 트렌치 구조의 소자분리산화막을 형성할 때 트렌치를 CVD 산화막으로 메꾸고 나서 평탄화하는 공정에도 사용할 수 있다.In addition, when forming a device isolation oxide film having a trench structure, the trench can be used in a process of filling the trench with a CVD oxide film and then planarizing it.
그리고 감압 후 헤드를 들어올려 웨이퍼를 연마패드 표면으로부터 완전히 떼었다가 다시 접촉시켜 가압하는 동작을 반복하여 실시할 수도 있다.After the pressure reduction, the operation may be repeated by lifting the head to completely remove the wafer from the surface of the polishing pad and contacting it again.
이상에서 설명한 바와 같이, 본 발명에 따른 CMP를 이용한 박막 평탄화방법은 패드의 압력을 주기적으로 변화시키면서 CMP 공정을 진행하여 패드의 탄성변형 때문에 CMP 공정에서 필연적으로 발생되는 일측에 과식각되는 디싱(dishing) 현상 등을 감소시켰으므로, 공정후 평탄성이 증가되어 포트공정이 용이해지고, CMP 공정을 보강하기 위해 박막증착, 식각 등의 공정을 새로 추가시킬 필요가 없으며, 평탄도 향상을 위해 새로운 패드를 제작하거나 슬러리를 개발할 필요없이 기존의 CMP 장비 및 소모품을 그대로 적용할 수 있으므로 공정단가를 절감할 수 있고, 연마의 균일성 및 재현성을 향상시켜 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the thin film flattening method using the CMP according to the present invention is subjected to a CMP process while periodically changing the pressure of the pad, so that the dish is overetched on one side that is inevitably generated in the CMP process due to the elastic deformation of the pad. ) As the phenomenon is reduced, the flatness is increased after the process, which makes the pot process easier, and there is no need to add a thin film deposition or etching process to reinforce the CMP process, and a new pad is manufactured to improve the flatness. Existing CMP equipment and consumables can be applied as it is without the need to develop a slurry or slurry, and process cost can be reduced, and the uniformity and reproducibility of polishing can be improved to improve process yield and device operation reliability. .
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