KR0171979B1 - Gate electrode forming method of semiconductor device - Google Patents
Gate electrode forming method of semiconductor device Download PDFInfo
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- KR0171979B1 KR0171979B1 KR1019950025417A KR19950025417A KR0171979B1 KR 0171979 B1 KR0171979 B1 KR 0171979B1 KR 1019950025417 A KR1019950025417 A KR 1019950025417A KR 19950025417 A KR19950025417 A KR 19950025417A KR 0171979 B1 KR0171979 B1 KR 0171979B1
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- Prior art keywords
- gate electrode
- etching
- polysilicon
- forming
- gate
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 54
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 13
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 6
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 235000021110 pickles Nutrition 0.000 claims 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 13
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000001052 transient effect Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000000460 chlorine Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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- Chemical Kinetics & Catalysis (AREA)
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- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 소자의 제조 방법.Method of manufacturing a semiconductor device.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
폴리사이드 구조의 게이트 전극 형성수행시에 우선 텅스텐 실리사이드를 종말점 식각하고, 과도식각을 실시하게 되는데, 상기 과도 식각을 실시하는 동안에 손실되면 안되는 게이트 전극용 폴리실리콘의 일부도 식각되므로써 게이트 전극용 폴리 실리콘의 종말점 식각을 어렵게 할 뿐만 아니라 게이트 산화막 및 반도체 기판의 일부도 식각하게 하는 문제가 발생함.When performing the gate electrode formation of the polyside structure, tungsten silicide is first etched and the end etching is performed, and a part of the polysilicon for the gate electrode which should not be lost during the etching is also etched, so that the polysilicon for the gate electrode is etched. Not only makes the etching of the end point difficult, but also causes etching of the gate oxide and part of the semiconductor substrate.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
금속 실리사이드와 게이트 전극용 폴리실리콘의 식각 선택비를 1:1로 조절하여 동시에 식각하고, 과도 식각 수행시에 게이트 전극용 폴리실리콘과 게이트 산화막의 식각 선택비를 1:1/50으로 조절하여 게이트 산화막의 손실을 최대한 억제시킬 수 있는 반도체 소자의 게이트 전극 형성 방법을 제공하고자 함.The etching selectivity of the metal silicide and the polysilicon for the gate electrode is controlled by 1: 1 and simultaneously, and the etching selectivity of the gate silicon polysilicon and the gate oxide is adjusted to 1: 1/50 during the transient etching. An object of the present invention is to provide a method of forming a gate electrode of a semiconductor device capable of suppressing loss of an oxide film as much as possible.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자의 제조, 특히 반도체 소자의 게이트 전극 형성에 이용됨.Used in the manufacture of semiconductor devices, in particular in the formation of gate electrodes of semiconductor devices.
Description
제1a도 내지 제1b도는 종래 기술에 따라 제조된 반도체 소자의 게이트 전극을 도시한 단면도.1A to 1B are cross-sectional views showing gate electrodes of semiconductor devices manufactured according to the prior art.
제2a도 내지 제2b도는 본 발명의 한 실시예에 따라 제조된 게이트 전극을 도시한 단면도.2A-2B are cross-sectional views illustrating gate electrodes fabricated in accordance with one embodiment of the present invention.
제3a도 내지 제3b도는 본 발명의 다른 실시예에 따라 제조된 게이트 전극을 도시한 단면도.3a to 3b are cross-sectional views showing a gate electrode manufactured according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21,31 : 반도체 기판 22,32 : 소자 분리막21,31: semiconductor substrate 22,32: device isolation film
23,33 : 게이트 산화막 24,34 : 게이트 전극용 폴리실리콘23,33: gate oxide film 24,34: polysilicon for gate electrode
25,35 : 텅스텐실리사이드 26,37 : 포토레지스트 패턴25,35 tungsten silicide 26,37 photoresist pattern
36 : 반사 방지막 24',34' : 게이트 전극36: antireflection film 24 ', 34': gate electrode
본 발명은 일반적으로 반도체 소자의 제조 방법에 관한 것으로서, 특히 전기적 특성이 양호한 금속실리사이드와 게이트 전극용 폴리실리콘으로 이루어진 폴리사이드(Polycide)구조를 갖는 반도체 소자의 게이트 전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate electrode of a semiconductor device having a polycide structure composed of metal silicide having good electrical characteristics and polysilicon for a gate electrode.
종래의 게이트 전극 형성 방법을 살펴보면, 먼저 제1a도에 도시한 바와 같이, 소자분리막(12)이 형성된 반도체 기판(11)상에 약 50Å 내지 100Å의 두께로 게이트 산화막(13)을 형성하고, 그위에 약 500Å 내지 1,000Å의 두께로 게이트 전극용 폴리실리콘(14)을 증착하고, 다시 그 위에 약 800Å 내지 1,200Å의 두께로 폴리사이드인 텅스텐 실리사이드(WSi2)(15)을 형성한후 게이트 전극을 형성하기 위한 소정의 포토레지스트 패턴(16)을 형성한다. 다음에, 제1b도에 도시한 바와 같이 상기 포토레지스트 패턴(16)을 식각 베리어로 이용하여 염소(Cl2) 및 브롬화수소(HBr) 분위기의 플라즈마(Plasma) 식각 공정을 이용하여 상기 텅스텐 실리사이드(15), 게이트 전극용 폴리실리콘(14)을 차례로 식각하므로써 게이트 전극(14')을 형성하고, 상기 포토레지스트 패턴(16)을 제거하게 된다. 이때, 상기 식각공정 수행시에 텅스텐 실리사이드(15), 게이트 전극용 폴리실리콘(14), 게이트 산화막(13)의 식각 선택비는 0.8:1:1/30정도가 된다. 다음에는 상기 식각 공정을 구체적으로 설명하면, 우선 텅스텐 실리사이드(15)를 종말점(End of point)식각하고, 다음에 상기 텅스텐 실리사이드(15)로 인한 파티클(Paticle)발생을 억제하도록 과도식각을 실시하게 되는데, 상기 과도 식각을 실시하는 동안에 손실되면 안되는 게이트 전극용 폴리실리콘(14)의 일부도 식각되어 게이트 전극의 폴리실리콘막(14)이 약 100Å 내지 300Å정도의 두께로 얇게 잔류하게 된다. 상기와 같은 게이트 전극용 폴리실리콘(14)의 손실은 게이트 전극용 폴리실리콘의 종말점 식각을 어렵게 할 뿐만 아니라 게이트 전극용 폴리실리콘(14)의 식각 수행시 게이트 산화막(13) 및 반도체 기판(11)의 일부까지 식각하게 되는 문제점을 발생시킨다.Referring to the conventional method of forming the gate electrode, as shown in FIG. After depositing polysilicon 14 for the gate electrode at a thickness of about 500 kPa to 1,000 kPa thereon, and again forming a tungsten silicide (WSi 2 ) 15 as a polyside at a thickness of about 800 kPa to 1,200 kPa thereon, the gate electrode Predetermined photoresist pattern 16 for forming a film is formed. Next, as shown in FIG. 1B, the tungsten silicide (S) is formed by using a plasma etching process in a chlorine (Cl 2 ) and hydrogen bromide (HBr) atmosphere using the photoresist pattern 16 as an etching barrier. 15) The gate electrode 14 'is formed by sequentially etching the gate silicon polysilicon 14, and the photoresist pattern 16 is removed. In this case, the etching selectivity of the tungsten silicide 15, the polysilicon 14 for the gate electrode 14, and the gate oxide layer 13 may be about 0.8: 1: 1/30 when the etching process is performed. Next, the etching process will be described in detail. First, the tungsten silicide 15 is etched to an end point, and then the etching is performed to suppress the generation of particles due to the tungsten silicide 15. A portion of the polysilicon 14 for gate electrodes, which should not be lost during the transient etching, is also etched so that the polysilicon film 14 of the gate electrode remains thin in a thickness of about 100 kPa to about 300 kPa. The loss of the polysilicon 14 for the gate electrode as described above not only makes it difficult to etch the end point of the polysilicon for the gate electrode, but also the gate oxide film 13 and the semiconductor substrate 11 during the etching of the polysilicon 14 for the gate electrode. It causes the problem of etching up to a part of.
따라서, 이러한 문제점을 해결하기 위하여 안출된 본 발명은, 금속 실리사이드와 게이트 전극용 폴리실리콘의 식각 선택비를 1:1로 조절하여 동시에 식각하고, 과도 식각 수행시에 게이트 전극용 폴리실리콘과 게이트 산화막의 식각 선택비를 1:1/50으로 조절하여 게이트 산화막의 손실을 최대한 억제시킬 수 있는 반도체 소자의 게이트 전극 형성 방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention devised to solve this problem, by controlling the etch selectivity ratio of the metal silicide and the polysilicon for the gate electrode to 1: 1 to simultaneously etch, polysilicon and gate oxide film for the gate electrode when performing the excessive etching It is an object of the present invention to provide a method for forming a gate electrode of a semiconductor device capable of maximally suppressing a loss of a gate oxide film by adjusting an etch selectivity of 1 to 50/50.
본 발명의 한 실시예에 따른 반도체 소자의 게이트 전극 형성 방법은, 소자분리막이 형성된 반도체 기판상에 게이트 산화막, 게이트 전극용 폴리실리콘, 금속 실리사이드를 차례로 형성하는 단계와, 게이트 전극을 형성하기 위한 소정의 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 베리어로 이용하여 소정의 공정 조건하에서 염소 가스 분위기의 플라즈마 식각 공정을 실시하여 상기 금속 실리사이드와 상기 게이트 전극용 폴리실리콘을 동시에 식각하는 제1식각공정을 실시하는 단계와, 소정의 공정 조건하에서 파티클 발생을 억제하도록 브롬화수소 분위기의 과도식각을 실시하는 제2식각 공정을 실시하는 단계 및 상기 포토레지스트 패턴을 제거하는 단계를 포함하는 것을 특징으로 한다.According to an embodiment of the present disclosure, a method of forming a gate electrode of a semiconductor device may include forming a gate oxide film, a polysilicon for a gate electrode, and a metal silicide on a semiconductor substrate on which an isolation layer is formed, and forming a gate electrode. Forming a photoresist pattern, and performing a plasma etching process in a chlorine gas atmosphere under a predetermined process condition using the photoresist pattern as an etching barrier to simultaneously etch the metal silicide and the polysilicon for the gate electrode. Performing an etching process, performing a second etching process for performing excessive etching of a hydrogen bromide atmosphere under a predetermined process condition, and removing the photoresist pattern. It is done.
본 발명의 다른 실시예에 따른 반도체 소자의 게이트 전극 형성 방법은, 소자분리막이 형성된 반도체 기판 상에 게이트 산화막, 게이트 전극용 폴리실리콘, 금속 실리사이드, 반사방지막을 차례로 형성하는 단계와, 게이트 전극을 형성하기 위한 소정의 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 베리어로 이용하여 소정의 공정 조건하에서 염소 가스 분위기의 플라즈마 식각 공정을 실시하여 상기 반사 방지막 및 상기 금속 실리사이드와 상기 게이트 전극용 폴리실리콘을 동시에 식각하는 제3식각공정을 실시하는 단계와, 파티클 발생을 억제하기 위한 과도식각을 실시하는 제4식각공정을 실시하는 단계 및, 상기 포토레지스트 패턴과 상기 반사 방지막을 차례로 제거하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, a method of forming a gate electrode of a semiconductor device includes sequentially forming a gate oxide film, a polysilicon for a gate electrode, a metal silicide, and an antireflection film on a semiconductor substrate on which a device isolation film is formed, and forming a gate electrode. Forming a predetermined photoresist pattern, and performing a plasma etching process in a chlorine gas atmosphere under a predetermined process condition by using the photoresist pattern as an etching barrier for the anti-reflection film, the metal silicide, and the gate electrode. Performing a third etching process for simultaneously etching polysilicon; performing a fourth etching process for performing excessive etching to suppress particle generation; and sequentially removing the photoresist pattern and the anti-reflective film Characterized in that it comprises a.
이제 본 발명의 첨부된 도면인 제2a도 내지 제2b도 및 제3a도 내지 제3b도를 참조하여 보다 상세하게 설명하게 된다. 본 발명의 한 실시예에 따른 반도체 소자의 게이트 전극 형성 방법을 살펴보면, 먼저 제2a도에 도시한 바와 같이 소자분리막(22)이 형성된 반도체 기판(21)상에 약 50Å 내지 100Å의 두께로 게이트 산화막(23)을 형성하고, 그위에 약 500Å 내지 1,000Å의 두께로 게이트 전극용 폴리실리콘(24)을 증착하고, 다시 그위에 약 800Å 내지 1,200Å의 두께로 텅스텐 실리사이드(25)를 형성한후 게이트 전극을 형성하기 위한 소정의 포토레지스트 패턴(26)을 형성한다. 다음에, 제2b도에 도시한 바와 같이 상기 포토레지스트 패턴(26)을 식각 베리어로 이용하여 염소 가스 분위기의 플라즈마 식각 공정을 실시하여 상기 텅스텐 실리사이드(25)와 게이트 전극용 폴리실리콘(24)의 식각 선택비가 1:1이 되도록 동시에 식각한다. 이때, 상기 식각공정 조건들로서 압력은 약 2 내지 10mTorr이고, 전력은 약 80 내지 300와트(W)이고, 염소 가스는 약 30cm3/분 내지 50cm3/분의 주입량으로 주입된다. 다음에는, 상기 텅스텐 실리사이드(25)로 인한 파티클 억제를 위하여 과도식각을 실시하여 게이트 전극(24')을 형성하고, 상기 포토레지스트 패턴(26)을 제거하게 되는데, 특히 게이트 산화막(23)의 손실을 최소로 하기 위하여 상기 게이트 전극용 폴리실리콘과 게이트 산화막의 식각 선택비를 약 1:1/50정도로 조절한다. 이때, 상기 과도식각 공정 조건들로서 압력은 약 2 내지 10mTorr이고, 전력은 약 50내지 300W이고, 브롬화수소 가스는 약 100cm3/분 내지 200cm3/분의 주입량으로 주입된다.Reference will now be made in detail to the accompanying drawings of the present invention, FIGS. 2A-2B and 3A-3B. Referring to the method of forming the gate electrode of the semiconductor device according to the embodiment of the present invention, first, as shown in FIG. (23) to form a gate electrode polysilicon (24) having a thickness of about 500 kPa to 1,000 kPa thereon, and again forming a tungsten silicide (25) to a thickness of about 800 kPa to 1,200 kPa thereon A predetermined photoresist pattern 26 for forming an electrode is formed. Next, as shown in FIG. 2B, a plasma etching process in a chlorine gas atmosphere is performed using the photoresist pattern 26 as an etching barrier, so that the tungsten silicide 25 and the polysilicon 24 for the gate electrode 24 are formed. Etch simultaneously so that the etching selectivity is 1: 1. At this time, as the etching conditions, the pressure is about 2 to 10 mTorr, the power is about 80 to 300 watts (W), and the chlorine gas is injected at an injection amount of about 30 cm 3 / min to 50 cm 3 / min. Next, in order to suppress particles due to the tungsten silicide 25, an overetch is performed to form the gate electrode 24 ′, and the photoresist pattern 26 is removed. In particular, a loss of the gate oxide layer 23 is achieved. In order to minimize the etch selectivity of the gate silicon polysilicon and the gate oxide film is adjusted to about 1: 1/50. At this time, as the transient etching conditions, the pressure is about 2 to 10mTorr, the power is about 50 to 300W, hydrogen bromide gas is injected at an injection amount of about 100cm 3 / min to 200cm 3 / min.
본 발명의 다른 실시예에 따른 반도체 소자의 게이트 전극 형성 방법을 살펴보면, 먼저 제3a도에 도시한 바와 같이 소자분리막(32)이 형성된 반도체 기판(31)상에 약 50Å 내지 100Å의 두께로 게이트 산화막(33)를 형성하고, 그위에 약 500Å 내지 1,000Å의 두께로 게이트 전극용 폴리실리콘(34)을 증착하고, 다시 그위에 약 800Å 내지 1,200Å의 두께로 텅스텐 실리사이드(35)을 형성하고, 그위에 약 200Å 내지 400Å의 두께로 반사 방지막(36)을 증착한 후 게이트 전극을 형성하기 위한 소정의 포토레지스트 패턴(37)을 형성한다. 다음에, 제3b도에 도시한 바와 같이 상기 포토레지스트 패턴(37)을 식각 베이어로 이용하여 염소 가스 분위기의 플라즈마 식각 공정을 실시하여 상기 반사 방지막(Anti reflective Coating)(36), 상기 텅스텐 실리사이드(34), 상기 게이트 전극용 폴리실리콘(34)의 식각 선택비가 1:1:1이 되도록 동시에 식각한다. 이때, 상기 식각 공정 조건들로서 압력은 약 2 내지 10mTorr이고, 전력은 약 80 내지 300와트(W)이고, 염소 가스는 약 30cm3 /분 내지 50cm3/분의 주입량으로 주입된다. 다음에는, 상기 텅스텐 실리사이드(35)로 인한 파티클 발생 억제를 위하여 과도식각을 실시하여 게이트 전극(34')을 형성하고, 상기 포토레지스트 패턴(37)과 상기 반사 방지막(36)을 제거하게 되는데, 특히 게이트 산화막(33)의 손실을 최소로 하기 위하여 상기 게이트 전극용 폴리실리콘(34)과 게이트 산화막(33)의 식각 선택비를 약 1:1/50정도로 조절한다. 이때, 상기 과도식각 공정 조건들로서 압력은 약 2 내지 10mTorr이고, 전력은 약 50 내지 300W이고, 브롬화수소 가스는 약 100cm3/분 내지 200cm3/분의 주입량으로 주입된다.Referring to the method of forming the gate electrode of the semiconductor device according to another embodiment of the present invention, first, as shown in FIG. (33) is formed thereon, and the polysilicon 34 for the gate electrode is deposited thereon at a thickness of about 500 kPa to 1,000 kPa, and thereon a tungsten silicide 35 is formed at a thickness of about 800 kPa to 1,200 kPa. After the anti-reflection film 36 is deposited to a thickness of about 200 GPa to 400 GPa, a predetermined photoresist pattern 37 for forming a gate electrode is formed. Next, as shown in FIG. 3B, a plasma etching process in a chlorine gas atmosphere is performed using the photoresist pattern 37 as an etching bay, thereby forming the anti reflective coating 36 and the tungsten silicide ( 34) and simultaneously etching so that the etching selectivity of the gate electrode polysilicon 34 is 1: 1: 1. In this case, as the etching process conditions, the pressure is about 2 to 10 mTorr, the power is about 80 to 300 watts (W), and the chlorine gas is injected at an injection amount of about 30 cm 3 / min to 50 cm 3 / min. Next, in order to suppress particle generation due to the tungsten silicide 35, transient etching is performed to form the gate electrode 34 ′, and the photoresist pattern 37 and the anti-reflection film 36 are removed. In particular, in order to minimize the loss of the gate oxide layer 33, the etching selectivity of the gate silicon polysilicon 34 and the gate oxide layer 33 is adjusted to about 1: 1/50. In this case, as the transient etching process conditions, the pressure is about 2 to 10 mTorr, the power is about 50 to 300 W, and the hydrogen bromide gas is injected at an injection amount of about 100 cm 3 / min to 200 cm 3 / min.
이와같이 구성된 본 발명에 따른 반도체 소자의 게이트 전극 형성 방법을 이용하므로써, 게이트 산화막의 손실을 최대한 억제하면서 게이트 전극을 형성할 수 있어 전기적 특성이 양호한 반도체 소자를 제조할 수 있을 뿐만 아니라 제조 수율향상에도 기여할 수 있다는 장점이 있다.By using the gate electrode formation method of the semiconductor device according to the present invention configured as described above, the gate electrode can be formed while suppressing the loss of the gate oxide film as much as possible, thereby not only manufacturing a semiconductor device having good electrical characteristics but also contributing to the improvement of manufacturing yield. There is an advantage that it can.
Claims (10)
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