KR0167668B1 - Method for fabricating thin film transistor - Google Patents

Method for fabricating thin film transistor Download PDF

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KR0167668B1
KR0167668B1 KR1019950037739A KR19950037739A KR0167668B1 KR 0167668 B1 KR0167668 B1 KR 0167668B1 KR 1019950037739 A KR1019950037739 A KR 1019950037739A KR 19950037739 A KR19950037739 A KR 19950037739A KR 0167668 B1 KR0167668 B1 KR 0167668B1
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forming
insulating film
gate electrode
film
region
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KR970023880A (en
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최국선
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김주용
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Thin Film Transistor (AREA)
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Abstract

본 발명은 셀 면적은 증가시키지 않으면서 트렌지스터의 유효 채널 길이를 증대시킴으로써 누설전류를 감소시키는 박막트렌지스터 제조방법에 관한 것으로, 본 발명은 반도체 기판에 제 1 절연막을 형성하고, 게이트전극 영역 이외지역의 상기 제 1 절연막 상부에 제 2 절연막을 형성하는 제1단계; 제1단계에 의한 구조의 전체 상부에 게이트전극 형성용 전도막을 형성하는 제2단계; 게이트전극 연역 이외의 상시 게이트전극 형성용 전도막을 식각하여 상기 제2 절연막을 노출시키는 제3단계; 및 상기 제1단계 및 제3단계에 위한 구조의 전체 상부에 게이트절연막 및 채널용 전도막을 형성하는 제4단계를 포함하여 이루어지는 것을 특징으로한다.The present invention relates to a method of manufacturing a thin film transistor which reduces leakage current by increasing the effective channel length of the transistor without increasing the cell area. The present invention provides a first insulating film on a semiconductor substrate, Forming a second insulating film on the first insulating film; A second step of forming a conductive film for forming a gate electrode over the entire structure of the first step; A third step of exposing the second insulating film by etching a conductive film for forming a gate electrode other than a gate electrode deduction; And a fourth step of forming a gate insulating film and a channel conductive film over the entire structure of the structures for the first and third steps.

Description

박막트렌지스터 제조방법Thin Film Transistor Manufacturing Method

제1도는 종래방법에 따른 박막트렌지스터의 단면도.1 is a cross-sectional view of a thin film transistor according to a conventional method.

제2a도 내지 제2c도는 본 발명의 일실시예에 따른 박막트렌지스터 제조과정을 나타내는 단면도.2a to 2c are cross-sectional views showing a thin film transistor manufacturing process according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings

21: 실리콘 기관 22: 절연막21: silicon organ 22: insulating film

23 : 산화막 24, 26 : 감광막패턴23: oxide film 24, 26: photosensitive film pattern

25 : 게이트 전극 형성용 폴리시리콘막25: polysilicon film for gate electrode formation

27 : 게이트산화막 28 : 채널용 폴리실리콘막27 gate oxide film 28 polysilicon film for channel

L : 게이트전극의 길이 L' : 채널의 길이L: length of gate electrode L ': length of channel

h : 겐이트전극 내의 단차발생 높이h: height of step difference in the gant electrode

본 발명은 박막트렌지스터 제조방법에 관한 것으로, 특히 트렌지스터의 유효 채널 길이를 증대시키기 위한 방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor, and more particularly to a method for increasing the effective channel length of the transistor.

일반적으로 4메가(M)급 이상의 스태틱램 셀에서는 박막트렌지스터를 이용해 셀을 구성하고 있다. 박막트렌지스터를 이용할 경우 높은 온/오프 전류비에 따라 셀의 안정도(stability)는 개선되나 폴리실리콘막을 채널로 이용함으로써 누설전류가 커지고, 또한 직접도가 높아질수록 셀면적이 감소되고 이에 따라 채널 길이가 짧아져 누설전류가 증가하게되는 단점이 있다.In general, a 4 mega (M) or more static ram cell uses a thin film transistor to form a cell. In case of using thin film transistor, the stability of cell is improved according to the high on / off current ratio, but the leakage current increases by using polysilicon film as the channel, and the cell area decreases as the directivity increases, thus the channel length is increased. There is a disadvantage in that the leakage current is shortened.

제1도는 종래방법에 따른 트렌지스터 형성후의 셀 단면도로서, 도면에서 미설명부호 1은 실리콘기판, 2는 산화막, 3은 게이트 폴리실리콘막, 4는 게이트산화막, 5는 채널폴리실리콘막, 6은 소스, 7은 드레인을 각각 나타낸다.1 is a cross-sectional view of a cell after transistor formation according to a conventional method, in which, reference numeral 1 denotes a silicon substrate, 2 an oxide film, 3 a gate polysilicon film, 4 a gate oxide film, 5 a channel polysilicon film, and 6 a source. And 7 represent a drain, respectively.

도시된 바와같이 박막트렌지스터의 채널 길이는 게이트 폴리실리콘막의 길이(L)에 의해 결정된다.As shown, the channel length of the thin film transistor is determined by the length L of the gate polysilicon film.

따라서, 집적도가 높은 박막트렌지스터를 제작할 경우 셀 면적 감소로 인해 불가피하게 게이트 폴리실리콘막의 길이 (L)가 줄어들게 되는데, 이 경우 채널 길이까지 줄어드는 누설전류가 증가하는 문제가 발생하게 된다.Therefore, when fabricating a high-density thin film transistor, the length (L) of the gate polysilicon film is inevitably reduced due to a decrease in cell area. In this case, the leakage current that decreases to the channel length increases.

상기와 같은 종래기술의 문제점을 해결하기 위하여 안출된 본 발명은 셀 면적은 증가시키지 않으면서 트렌지스터의 유효 채널 길이를 증대시킴으로써 누설전류를 감소시키는 박막트렌지스터 제조방법을 제공하는데 그 목적이 있다.The present invention devised to solve the problems of the prior art as described above is to provide a thin film transistor manufacturing method for reducing the leakage current by increasing the effective channel length of the transistor without increasing the cell area.

상기 목적을 달성하기 위하여 본 발명은 반도체기판에 제 1 절연막을 형성하고, 게이트전극 영역 이외지역의 상기 제 1 절연막 상부에 제 2 절연막을 형성하는 제1단계; 제1단계에 의한 구조의 전체 상부에 게이트전극 형성용 전도막을 형성하는 제2단계; 게이트전극 영역 이외의 상기 게이트전극 형성용 전도막을 식각하여 상기 제 2 절연막을 노출시키는 제3단계 및 상기 제1단계 및 제3단계에 의한 구조의 전체 상부에 게이트절연막 및 채널용 전도막을 형성하는 제4단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a semiconductor device comprising: a first step of forming a first insulating film on a semiconductor substrate and forming a second insulating film over the first insulating film in a region other than the gate electrode region; A second step of forming a conductive film for forming a gate electrode over the entire structure of the first step; Etching the conductive film for forming the gate electrode other than the gate electrode area to expose the second insulating film, and forming a gate insulating film and a channel conductive film over the entire structure of the first and third steps. Characterized in that it comprises four steps.

이하, 첨부된 도면 제2a도 내지 제2c도를 참조하여 본 발명의 실시예를 상술한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings 2A to 2C.

제2a도 내지 제2c도는 본 발명의 일실시예에 따른 박막트렌지스터 제조과정을 나타내는 단면도로서, 먼저, 제2a도에 도시된 바와같이 실리콘기판(21) 상에 이후 형성될 박막트렌지스터와의 절연을 위한 절연막(22)을 증착하고, 산화막(23)을 예정된 게이트전극의 두께만큼 증착한다. 이때의 산화막(23)은 게이트전극 영역 이외지역에서는 단차를 높게 형성하기 위함이다.2A to 2C are cross-sectional views illustrating a process of manufacturing a thin film transistor according to an embodiment of the present invention. First, as shown in FIG. 2A, insulation of a thin film transistor to be subsequently formed on a silicon substrate 21 is illustrated. Insulating film 22 is deposited, and oxide film 23 is deposited by a predetermined thickness of the gate electrode. At this time, the oxide film 23 is intended to form a high step outside the gate electrode region.

계속해서, 상기 산화막(23) 위에 네가티브형 감광막을 도포한 다음, 게이트전극 형성용 마스크를 사용한 리소그래피 공정을 통해 게이트전극 영역을 노출시키는 감광막패턴(24)을 형성한다.Subsequently, a negative photosensitive film is coated on the oxide film 23, and then a photosensitive film pattern 24 for exposing the gate electrode region is formed through a lithography process using a mask for forming a gate electrode.

다음으로, 제2b도에서 상기 감광패턴(24)을 식각마스크로 사용하여 하부의 상기 산화막(23)을 식감함으로써 게이트전극 영역의 상기 절연막(22)을 노출시킨 다음, 상기 감광막패턴(24)을 제거한다.Next, in FIG. 2B, the oxide layer 23 is etched by using the photoresist pattern 24 as an etching mask to expose the insulating layer 22 in the gate electrode region, and then the photoresist pattern 24 is exposed. Remove

계속해서, 상기 구조 전체 상부에 게이트전극 형성용 폴리실리콘막(25)을 증착하고, 포지티브형 감광막을 도포한 다음, 게이트전극 형성용 마스크를 사용한 리소그래피 공정을 통해 게이트전극 영역 이외의 상기 폴리실리콘막(25)을 노출시키는 감광막패턴(26)을 형성한다.Subsequently, a polysilicon film 25 for forming a gate electrode is deposited on the entire structure, a positive photosensitive film is applied, and then the polysilicon film other than the gate electrode region is subjected to a lithography process using a mask for forming a gate electrode. The photosensitive film pattern 26 which exposes (25) is formed.

이어서, 제2c도에 도시된 바와같이 상기 감광막패턴(26)을 식각 마스크로 사용하여 하부의 상기 폴리실리콘막(25)을 식각함으로써 상기 산화막(23)을 노출시킨 다음, 상기 감광막패턴(24)을 제거한다.Subsequently, as shown in FIG. 2C, the oxide layer 23 is exposed by etching the polysilicon layer 25 below using the photoresist pattern 26 as an etching mask, and then the photoresist pattern 24 is exposed. Remove it.

끝으로, 상기 산화막(23) 및 폴리실리콘막(25) 상부에 게이트산화막(27) 및 채널용 폴리실리콘막(28)을 증착한다. 이때, 게이트 폴리실리콘막 내에 단차가 크게 형성됨에 따라, 상부에 형성되는 상기 게이트산화막(27) 및 채널용 폴리실리콘막(28)에도 단차가 형성되게되고, 따라서, 채널의 길이가 게이트 전극 내의 단차발생 높이(h)의 2배만큼 증대됨을 알수 있다. 도면에서 L은 게이트전극의 길이를, L'는 채널의 길이를, h는 게이트전극 내의 단차발생 높이를 나타낸다.Finally, the gate oxide layer 27 and the channel polysilicon layer 28 are deposited on the oxide layer 23 and the polysilicon layer 25. At this time, as the step is largely formed in the gate polysilicon film, the step is also formed in the gate oxide film 27 and the channel polysilicon film 28 formed thereon, so that the length of the channel is increased in the gate electrode. It can be seen that it is increased by twice the height of occurrence (h). In the drawing, L represents the length of the gate electrode, L 'represents the length of the channel, and h represents the height of the step difference in the gate electrode.

이후의 공정은 일반적으로 박막트렌지스터 형성공정으로써, 소스/드레인 형성용 마스크를 사용한 불순물 주입공정으로 소스/드레인 영역을 형성한 다음, 채널 형성용 마스크로 채널 이외 지역의 상기 폴리실리콘막을 식각해 낸 후 절연막 증착 및 금속배선 공정을 진행한다.The subsequent process is generally a thin film transistor forming process, which forms a source / drain region by an impurity implantation process using a source / drain formation mask, and then etches the polysilicon film in a region other than the channel using a mask for channel formation. Insulation film deposition and metallization process are performed.

상기와같이 이루어지는 본 발명은 셀 면적을 증대시키지 않고서도 채널의 길이를 증대시킴으로써 누설전류를 감소시킬 수 있으며, 이에 따라 스태틱램의 소비전력을 감소시킴으로써 저전력 소비용 스태틱램 제작이 가능하다.The present invention made as described above can reduce the leakage current by increasing the length of the channel without increasing the cell area, thereby making the static ram for low power consumption by reducing the power consumption of the static ram.

Claims (5)

반도체기판에 제 1 절연막을 형성하고, 게이트전극 영역 이외지역의 상기 제 1 절연막 상부에 제 2 절연막을 형성하는 제1단계; 제1단계에 의한 구조의 전체 상부에 게이트전극 형성용 전도막을 형성하는 제2단계; 게이트 영역 이외의 상기 게이트 전극 형성용 전도막을 식각하여 상기 제 2 절연막을 노출시키는 제 3 단계; 및 상기 제1단계 및 제3단계에 의한 구조의 전체 상부에 게이트 절연막 및 채널용 전도막을 형성하는 제4단계를 포함하여 이루어지는 것을 특징으로 하는 박막트렌지스터 제조방법.Forming a first insulating film on the semiconductor substrate, and forming a second insulating film over the first insulating film in a region other than the gate electrode region; A second step of forming a conductive film for forming a gate electrode over the entire structure of the first step; Etching the conductive film for forming the gate electrode other than the gate region to expose the second insulating film; And a fourth step of forming a gate insulating film and a channel conductive film on the entire structure of the first and third structures. 제1항에 있어서, 상기 제1단계의 제 2 절연막은 게이트전극 영역 이외지역에서의 단차를 높게 형성하기 위함인 것을 특징으로 하는 박막트렌지스터 제조방법.The method of claim 1, wherein the second insulating film of the first step is to form a high step in a region other than the gate electrode region. 제2항에 있어서, 상기 제1단계는 반도체기판에 제 1 절연막을 형성하고, 상기 제 1 절연막 상부에 제 2 절연막을 형성하되, 예정된 게이트전극의 두께만큼 형성하는 단계; 상기 제 2 절연막 위에 네가티브형 감광막을 도포한 다음, 게이트전극 형성용 마스크를 사용한 리소그래피 공정을 통해 게이트 전국 영역을 노출시키는 제 1 감광막패턴을 형성하는 단계; 및 상기 제 1 감광막패턴을 식각마스크로 사용하여 하부의 상기 제 2 절연막을 식각함으로써 게이트전극 영역의 상기 제 1 절연막을 노출시킨 다음, 상기 제 1 감광막패턴을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 박막트렌지스터 제조방법.3. The method of claim 2, wherein the first step comprises: forming a first insulating film on the semiconductor substrate, and forming a second insulating film on the first insulating film, wherein the second insulating film is formed to have a predetermined thickness of the gate electrode; Applying a negative photosensitive film on the second insulating film, and then forming a first photosensitive film pattern exposing a gate whole region through a lithography process using a gate electrode forming mask; And etching the lower second insulating film using the first photoresist pattern as an etch mask to expose the first insulating film in the gate electrode region, and then remove the first photoresist pattern. Thin film transistor manufacturing method. 제3항에 있어서, 상기 제 2 절연막은 산화막을 포함하여 이루어지는 것을 특징으로 하는 박막트렌지스터 제조방법.The method of claim 3, wherein the second insulating film comprises an oxide film. 제3항에 있어서, 상기 제3단계는 상기 게이트전극 형성용 전도막 상부에 포지티브형 감광막을 도포한 다음, 게이트전극 형성용 마스크를 사용한 리소그래프 공정을 통해 게이트 전극 영역 이외의 상기 전도막을 노출시키는 제 2 감광막패턴을 형성하는 단계; 상기 제 2 감광막패턴을 식각마스크로 사용하여 하부의 상기 게이트 전극 형성용 전도막을 식각함으로써 상기 제 2 절연막을 노출시킨 다음, 상기 제 2 감광막패턴을 제거하는 단계를 포함하여 이루어지는 것을 특징을 하는 박막트렌지스터 제조방법.4. The method of claim 3, wherein the third step includes applying a positive photosensitive film on the conductive film for forming the gate electrode, and then exposing the conductive film other than the gate electrode region through a lithography process using a mask for forming the gate electrode. Forming a second photoresist pattern; Exposing the second insulating film by etching the lower conductive film for forming the gate electrode using the second photoresist pattern as an etching mask, and then removing the second photoresist pattern. Manufacturing method.
KR1019950037739A 1995-10-27 1995-10-27 Method for fabricating thin film transistor KR0167668B1 (en)

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