KR0155847B1 - Method of forming interconnection of semiconductor device - Google Patents

Method of forming interconnection of semiconductor device Download PDF

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Publication number
KR0155847B1
KR0155847B1 KR1019950020643A KR19950020643A KR0155847B1 KR 0155847 B1 KR0155847 B1 KR 0155847B1 KR 1019950020643 A KR1019950020643 A KR 1019950020643A KR 19950020643 A KR19950020643 A KR 19950020643A KR 0155847 B1 KR0155847 B1 KR 0155847B1
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South Korea
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layer
wiring
insulating layer
forming
semiconductor device
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KR1019950020643A
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Korean (ko)
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KR970008488A (en
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김창규
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김광호
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

반도체소자의 배선형성방법이 개시되어 있다. 반도체기판 상에 절연층과 캡핑층을 형성하는 단계, 상기 캡핑층 및 상기 절연층을 식각하여 금속배선이 형성될 부분의 상기 절연막을 패터닝하는 단계, 상기 기판 전면에 매몰층 및 배선층을 적층하는 단계, 상기 배선층상에 키홀(key hole)이 없는 양호한 배선을 형성하기 위해 보호층을 적층시키는 단계, 및 상기 보호층, 배선층, 매몰층, 하부캐핑층을 상기 절연층이 노출될 때까지 화학-기계적 폴리싱(CMP) 하는 단계를 구비하는 것을 특징으로 하는 반도체소자 배선 형성방법을 제공한다. 본 발명에 의하면, 배선층 형성후 SOG를 피복시킴으로서, 후속 CMP 공정시에 발생되는 배선층의 키홀(key hole) 발생현상등을 방지하여 신뢰성 있는 금속배선을 형성할 수 있다.A wiring forming method of a semiconductor device is disclosed. Forming an insulating layer and a capping layer on a semiconductor substrate, etching the capping layer and the insulating layer, patterning the insulating layer on a portion where a metal wiring is to be formed, and depositing a buried layer and a wiring layer on the entire surface of the substrate Stacking a protective layer to form good wiring free of key holes on the wiring layer, and chemically-mechanical-mechanically until the insulating layer exposes the protective layer, the wiring layer, the buried layer, and the lower capping layer. Provided is a method of forming a semiconductor device wiring, comprising the step of polishing (CMP). According to the present invention, by coating the SOG after the formation of the wiring layer, it is possible to prevent the occurrence of key holes in the wiring layer generated in the subsequent CMP process and to form reliable metal wiring.

Description

반도체소자 배선형성방법Semiconductor Device Wiring Formation Method

제1도 내지 제3도는 종래의 배선형성 방법을 도시한 공정순서도.1 to 3 are process flowcharts showing a conventional wiring forming method.

제4도 내지 제6도는 본 발명에 의한 배선형성 방법을 도시한 공정순서도.4 to 6 are process flowcharts showing a wiring forming method according to the present invention.

본 발명은 고집적 반도체소자의 배선 형성방법에 관한 것으로, 특히 화학-기계적 폴리싱(Chemical Mechanical Polishing: 이하 CMP라 칭함)을 이용한 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method of a highly integrated semiconductor device, and more particularly, to a wiring forming method using chemical mechanical polishing (hereinafter, referred to as CMP).

일반적으로, CMP는 반도체 소자 제조 과정에 있어서 웨이퍼 표면을 평탄화 시켜 금속 플러그를 형성하기 위한 방법으로 배선 공정에서 널리 사용되고 있다. 구체적으로, 금속 배선 폴리싱(Metalic polishing) 공정은 패턴이 형성된 절연막상에 도전막을 형성하고, 상기 도전막을 폴리싱하는 공정으로 이루어진다. 통상적인 폴리싱 공정은 폴리싱 패드와 연마제를 이용한 기계적 성분과 슬러리(slurry) 용액내 화학적 성분에 의해서 기판상의 표출 부위를 식각한다.In general, CMP is widely used in the wiring process as a method for forming a metal plug by planarizing a wafer surface in a semiconductor device manufacturing process. Specifically, the metallographic polishing process includes a process of forming a conductive film on an insulating film on which a pattern is formed and polishing the conductive film. Conventional polishing processes etch exposed areas on the substrate by mechanical components using polishing pads and abrasives and chemical components in slurry solutions.

제1도 내지 제3도는 종래의 폴리싱 배선형성 방법을 도시한 공정 순서도이다.1 to 3 are process flowcharts showing a conventional polishing wiring forming method.

제1도는 반도체 기판(10)상에 절연층, 예컨대 BPSG(BoroPhospho Silicate Glass: 이하 BPSG라 칭함) 또는 USG(Undoped Silicate Glass)등의 산화층을 사용하여 절연층(12)을 형성한 다음, 상기 절연층상에 SiN을 도포하여 캡핑층(14)을 형성한다. 이어서, 통상의 사진식각 공정을 사용하여 금속배선이 형성될 부분의 상기 절연층(12)을 패터닝한 공정을 나타낸다.FIG. 1 illustrates an insulating layer 12 formed on the semiconductor substrate 10 by using an oxide layer such as BoroPhospho Silicate Glass (BPPSG) or Undoped Silicate Glass (USG). SiN is applied on the layer to form the capping layer 14. Next, the process of patterning the said insulating layer 12 of the part in which metal wiring is to be formed using a normal photolithography process is shown.

제2도는 상기 결과물인 기판 전면에, 예컨대 티타늄(Ti), 티타늄질화물(TiN), 혹은 티타늄과 티타늄질화물의 조합중 어느하나를 증착하여 매몰층(Buried layer:16)을 형성한 다음, 도전막, 에컨대 텅스텐(W:18)등의 내화금속을 증착하여 배선층(18)을 형성한 공정을 나타낸다. 상기 배선층인 금속층은 스페이스 다운(space down:U) 영역에서 V자형의 골(keyhole:20)이 형성된다. 특히, 도전층으로 텅스텐을 사용할 경우 텅스텐층은 종방향(column)구조로 성장되기 때문에 스페이스 다운영역에서 취약한 구조를 보여 주고 있다.2 shows a buried layer (16) formed by depositing any one of titanium (Ti), titanium nitride (TiN), or a combination of titanium and titanium nitride on the resulting substrate, and then a conductive film. The process of forming the wiring layer 18 by depositing refractory metals, such as tungsten (W: 18), for example is shown. In the metal layer, which is the wiring layer, a V-shaped valley 20 is formed in a space down area. In particular, when tungsten is used as the conductive layer, the tungsten layer grows in a columnar structure, and thus shows a weak structure in the space down region.

제3도는 상기와 같이 형성된 배선층을 상기 절연층(12)이 노출될 때까지 상기 배선층(18) 및 매몰층(16)을 폴리싱한 공정을 나타낸다.3 shows a process of polishing the wiring layer 18 and the buried layer 16 until the insulating layer 12 is exposed to the wiring layer formed as described above.

상기와 같이 형성된 막을 폴리싱하면 스페이스 다운영역에 화학적침투가 용이하기 때문에 제3도와 같이 배선 중간 부분(20a)이 손상(attack)을 받는다.Polishing the film formed as described above facilitates chemical penetration into the space down region, so that the intermediate portion 20a of the wiring is damaged as shown in FIG. 3.

따라서, 본 발명의 목적은 배선층을 폴리싱할 때 배선 중간 부분이 손상을 받아 스페이스 다운 영역에서의 키홀(keyhole)현상과 같은 문제점이 발생하지 않는 신뢰성 있는 반도체소자 배선 형성방법을 제공하는 것이다.Accordingly, it is an object of the present invention to provide a reliable method for forming a semiconductor device wiring in which the middle portion of the wiring is damaged when polishing the wiring layer so that problems such as keyhole phenomenon in the space down region do not occur.

상기 목적을 달성하기위하여 본 발명은, 반도체기판 상에 절연층을 형성하는 단계; 상기 절연층을 식각하여 금속배선이 형성될 부분의 상기 절연막을 패터닝하는 단계; 상기 기판 전면에 매몰층 및 배선층을 적층하는 단계; 상기 배선층상에 보호막을 적층시키는 단계; 및 상기 보호막, 배선층 및 매몰층을 상기 절연층이 노출될 때까지 화학-기계적 폴리싱(Chemical Mechanical Polishing; 이하, CMP라 칭함)하는 단계를 구비하는 것을 특징으로 하는 반도체소자 배선 형성방법을 제공한다.In order to achieve the above object, the present invention, forming an insulating layer on a semiconductor substrate; Etching the insulating layer to pattern the insulating layer on a portion where a metal wiring is to be formed; Stacking a buried layer and a wiring layer on the entire surface of the substrate; Stacking a protective film on the wiring layer; And chemical-mechanical polishing (hereinafter, referred to as CMP) until the insulating layer is exposed to the passivation layer, the wiring layer, and the buried layer.

상기 배선층은 금속으로 형성하고, 상기 금속은 텅스텐(W), 몰리브데늄(Mo), 티타늄질화물(TiN), 알루미늄(Al), 구리(Cu)의 군에서 어느하나를 선택하는 것이 바람직하다.The wiring layer is formed of a metal, and the metal is preferably selected from tungsten (W), molybdenum (Mo), titanium nitride (TiN), aluminum (Al), and copper (Cu).

상기 절연층 형성 단계에는 절연층위에 캡핑층을 동시에 형성하고, 상기 패터닝 단계에는 상기 절연층과 동시에 캡핑층을 식각하고, 상기 폴리싱단계에는 캡핑층도 동시에 폴리싱하는 방법이 바람직하다.In the insulating layer forming step, a capping layer is simultaneously formed on the insulating layer, in the patterning step, the capping layer is etched simultaneously with the insulating layer, and in the polishing step, the capping layer is preferably polished simultaneously.

본 발명에 의하면, 배선층 표면을 키홀(keyhole)이 형성될 영역에 두꺼운 보호막을 피복시킴으로서, 후속 CMP 공정시에 발생되는 배선층의 키홀(key hole) 발생현상등을 방지하여 신뢰성 있는 금속배선을 형성할 수 있다.According to the present invention, by coating a thick protective film on an area where keyholes are to be formed on the surface of the wiring layer, it is possible to prevent the occurrence of keyholes in the wiring layer generated during the subsequent CMP process and to form reliable metal wiring. Can be.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하고자 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제4도 내지 제6도는 본 발명에 의한 배선형성 방법을 도시한 공정순서도이다.4 to 6 are process flowcharts showing the wiring forming method according to the present invention.

제4도는 반도체 기판(50)상에 절연층, 예컨대 BPSG등의 산화층을 사용하여 절연층(52)을 형성한 다음, 상기 절연층상에 질화막(SiN)을 도포하여 캡핑층(54)을 형성한다. 이어서, 통상의 사진식각 공정을 사용하여 금속배선이 형성될 부분의 상기 절연층(52)을 패터닝한다. 상기 캡핑층은 생략해도 무방하나 패터닝공정에는 사용하는 것이 바람직하다.FIG. 4 forms an insulating layer 52 on the semiconductor substrate 50 by using an insulating layer such as an oxide layer such as BPSG, and then forms a capping layer 54 by applying a nitride film (SiN) on the insulating layer. . Subsequently, the insulating layer 52 of the portion where the metal wiring is to be formed is patterned using a conventional photolithography process. The capping layer may be omitted, but it is preferable to use the capping layer.

상기 캡핑층의 두께는 10~3000Å까지 배선의 폭에 따라서 변화시킬 수 있으며, 상기 SiN 대신에 SiO2, Si3N4, BN, SiBN, Al2O3등이 사용될 수 있다. 한편 상기 캡핑층은 PECVD, LPCVD, 및 스퍼터 방법등을 사용하여 형성한다.The thickness of the capping layer can be changed depending on the width of the wiring to 10 ~ 3000Å, SiO 2 , Si 3 N 4 , BN, SiBN, Al 2 O 3 or the like can be used instead of the SiN. Meanwhile, the capping layer is formed using PECVD, LPCVD, and sputtering methods.

제5도는 배선층(58) 및 보호층(62)을 형성하는 공정을 도시한 것이다.5 shows a process of forming the wiring layer 58 and the protective layer 62.

상기 결과물인 기판 전면에, 티타늄(Ti) 300Å과 티타늄질화물(TiN) 600Å을 증착하여 매몰층(56)을 형성한 다음, 도전성 금속(Conductive Metal)으로 텅스텐(W)을 10000Å증착하여 배선층(58)을 형성한다. 상기 배선층인 금속층은 하방이 침하된 부분인 스페이스 다운(space down:U) 영역에서 V자형의 골(60)이 형성된다. 특히, 도전층으로 텅스텐을 사용할 경우 텅스텐층은 종방향(column)구조로 성장되기 때문에 스페이스 다운영역에서 취약한 구조를 보여 주고 있다.300 Å of titanium (Ti) and 600 티타늄 of titanium nitride (TiN) were deposited on the entire surface of the resultant substrate to form a buried layer 56, and then 10000 Å of tungsten (W) was deposited using a conductive metal to form a wiring layer 58. ). In the metal layer serving as the wiring layer, a V-shaped valley 60 is formed in a space down (U) region where the lower portion is settled. In particular, when tungsten is used as the conductive layer, the tungsten layer grows in a columnar structure, and thus shows a weak structure in the space down region.

상기 매몰층(56)은 통상적인 경우와 마찬가지로 실리콘기판과 배선층과의 접촉저항 개선 및 기판 실리콘의 확산을 방지하기 위하여 형성하고, 상기 티타늄(Ti) 대신 티타늄질화물(TiN), 티타늄텅스텐(TiW), 몰리브데늄(Mo), 크롬(Cr) 또는 상기 물질들을 결합하여 형성할 수 있다.The buried layer 56 is formed to improve the contact resistance between the silicon substrate and the wiring layer and prevent diffusion of the substrate silicon, as in the conventional case, and instead of the titanium (Ti), titanium nitride (TiN) and titanium tungsten (TiW). , Molybdenum (Mo), chromium (Cr) or may be formed by combining the above materials.

배선층이 형성된 상기 기판 전면에 폴리싱중 형성되어질 배선의 키홀(key hole) 형성을 방지할 수 있는 보호막, 예컨대 SOG(Spin On Glass), 산화물, 질화물(SiN), 티타늄질화물(TiN) 및 티타늄(Ti)중 어느 하나를 도포하여 보호층(62)을 형성한다. 이와같이 매몰 금속(Buried Metal)과 전도성(Conductive) 금속층을 형성한 후 상대적으로 스페이스 다운영역에서 안정 억제(passivation) 효과가 큰 물질을 증착하면 폴리싱동안 슬러리에 의한 손상(Attack)을 막을 수 있다.A protective film capable of preventing the formation of key holes of the wiring to be formed during polishing on the entire surface of the substrate on which the wiring layer is formed, such as spin on glass (SOG), oxides, nitrides (SiN), titanium nitrides (TiN), and titanium (Ti). ) Is applied to form the protective layer 62. As such, after depositing a buried metal and a conductive metal layer, depositing a material having a large passivation effect in a space down region can prevent attack by slurry during polishing.

상기 배선층(58)은 텅스텐(W), 몰리브데늄(Mo), 티타늄질화물(TiN), 알루미늄(Al), 구리(Cu)등의 금속을 사용하여 형성할 수 있다. 또한, 상기 배선층(58)은 PECVD등의 CVD 방법과 스퍼터등의 PVD 방법을 사용하여 증착할 수 있으나, 단차도포성이 우수한 CVD 방법을 사용하는 것이 바람직하다.The wiring layer 58 may be formed using a metal such as tungsten (W), molybdenum (Mo), titanium nitride (TiN), aluminum (Al), copper (Cu), or the like. In addition, the wiring layer 58 may be deposited using a CVD method such as PECVD and a PVD method such as sputtering, but it is preferable to use a CVD method having excellent step coverage.

제6도는 CMP 공정후 키홀이 제거된 모습을 도시한 것이다.6 shows the keyhole removed after the CMP process.

본 발명에서는 금속막과 절연막을 증착한 후 금속 폴리싱(Metal polishing)을 진행하였다. 통상적인 CMP 방법을 이용하여 상기 절연층(52)이 노출될 때까지 상기 배선층(58), 매몰층(56) 및 캡핑층(54)을 폴리싱한다. 금속막 폴리싱 공정은 일반적으로 슬러리내 산화제를 이용한 산화 반응과 연마제를 이용한 물리적 반응으로 금속막을 식각한다. 따라서, 산화막(oxide)에 비하여 10배이상의 폴리싱비(polishing rate)로 식각한다.In the present invention, a metal film and an insulating film are deposited and then metal polishing is performed. The wiring layer 58, the buried layer 56, and the capping layer 54 are polished until the insulating layer 52 is exposed using a conventional CMP method. The metal film polishing process generally etches a metal film by an oxidation reaction using an oxidizing agent in a slurry and a physical reaction using an abrasive. Therefore, etching is performed at a polishing rate of 10 times or more as compared to oxide.

본 발명에 의하면, 배선층 표면을 키홀(keyhole)이 형성될 영역에 보다 두꺼운 절연물 예컨대, SOG등으로 피복시킴으로서, 후속 CMP 공정시에 발생되는 배선층의 키홀(key hole) 발생현상등을 방지하여 신뢰성 있는 금속배선을 형성할 수 있다.According to the present invention, by covering the surface of the wiring layer with a thicker insulator such as SOG in the area where the keyhole is to be formed, it is possible to prevent key hole occurrence of the wiring layer generated during the subsequent CMP process and to reliably Metal wiring can be formed.

본 발명은 상기 실시예에만 한정되지 않으며, 많은 변형이 본 발명이 속한 기술적 사상내에서 당 분야에서 통상의 지식을 가진 자에 의해 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea to which the present invention pertains.

Claims (5)

반도체기판 상에 절연층을 형성하는 단계; 상기 절연층을 식각하여 금속배선이 형성될 부분의 상기 절연막을 패터닝하는 단계; 상기 기판 전면에 매몰층 및 배선층을 적층하는 단계; 상기 배선층상에 보호층을 적층시키는 단계; 및 상기 보호층, 배선층 및 매몰층을 상기 절연층이 노출될 때까지 화학-기계적 폴리싱(CMP) 하는 단계를 구비하는 것을 특징으로 하는 반도체소자 배선 형성방법.Forming an insulating layer on the semiconductor substrate; Etching the insulating layer to pattern the insulating layer on a portion where a metal wiring is to be formed; Stacking a buried layer and a wiring layer on the entire surface of the substrate; Stacking a protective layer on the wiring layer; And chemical-mechanical polishing (CMP) the protective layer, the wiring layer, and the buried layer until the insulating layer is exposed. 제1항에 있어서, 상기 절연층 형성 단계에는 절연층위에 캡핑층을 동시에 형성하고, 상기 패터닝 단계에는 상기 절연층과 동시에 캡핑층을 식각하고, 상기 폴리싱단계에는 캡핑층도 동시에 폴리싱하는 것을 특징으로 하는 반도체 소자 배선 방법.The method of claim 1, wherein the capping layer is formed on the insulating layer at the same time, the capping layer is etched at the same time as the insulating layer, and the capping layer is simultaneously polished at the polishing step. Semiconductor element wiring method. 제1항에 있어서, 상기 배선층은 텅스텝(W), 몰리브데늄(Mo), 티타늄질화물(TiN), 알루미늄(Al), 구리(Cu)의 군에서 선택된 어느하나인 것을 특징으로 하는 반도체소자 배선 형성방법.The semiconductor device of claim 1, wherein the wiring layer is any one selected from a group consisting of tungstep (W), molybdenum (Mo), titanium nitride (TiN), aluminum (Al), and copper (Cu). Wiring formation method. 제1항에 있어서, 상기 매몰층은 티타늄(Ti), 티타늄질화물(TiN), 티타늄텅스텐(TiW), 몰리브데늄(Mo), 크롬(Cr) 및 상기 물질이 적층된 결합물질중 어느 하나인 것을 특징으로 하는 반도체 소자 배선 형성방법.The method of claim 1, wherein the buried layer is any one of titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), molybdenum (Mo), chromium (Cr) and a bonding material in which the material is laminated. A method of forming a semiconductor device wiring, characterized in that. 제1항에 있어서, 상기 보호층은 SOG, 산화물, 포토레지스트(P.R.), 질화물(SiN), 티타늄질화물(TiN) 및 티타늄(Ti) 중 어느하나인 것을 특징으로 하는 반도체 소자 배선 형성 방법.The method of claim 1, wherein the protective layer is any one of SOG, oxide, photoresist (P.R.), nitride (SiN), titanium nitride (TiN), and titanium (Ti).
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KR100494121B1 (en) * 1997-07-08 2005-08-31 주식회사 하이닉스반도체 Flattening method of semiconductor device
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100398033B1 (en) * 1996-12-28 2003-12-24 주식회사 하이닉스반도체 Method for removing key-hole of semiconductor device

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