KR0146652B1 - Fabrication method of self-aligned hbt by forming dummy emitter electrode and polyimide sidewall - Google Patents

Fabrication method of self-aligned hbt by forming dummy emitter electrode and polyimide sidewall

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KR0146652B1
KR0146652B1 KR1019940036373A KR19940036373A KR0146652B1 KR 0146652 B1 KR0146652 B1 KR 0146652B1 KR 1019940036373 A KR1019940036373 A KR 1019940036373A KR 19940036373 A KR19940036373 A KR 19940036373A KR 0146652 B1 KR0146652 B1 KR 0146652B1
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emitter
layer
polyimide
electrode
base
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KR1019940036373A
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Korean (ko)
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KR960026917A (en
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박성호
최성우
박문평
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양승택
재단법인한국전자통신연구소
조백제
한국전기통신공사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

3-5족 화합물 반도체를 이용하는 이종접합 바이폴라 트렌지스터(Heterojunction Bipolar Transistor : HBT)를 제작함에 있어서, HBT 소자 고유의 고속특성을 극대화하기 위하여 임시 에미터 전극과 폴리이미드 측벽을 이용한 에미터-베이스 간의 자기정렬 제작방법을 고안함으로써, 기존의 HBT 소자 제작공정을 개선하였다.In the fabrication of heterojunction bipolar transistors (HBTs) using group 3-5 compound semiconductors, magnetism between the temporary emitter electrode and the emitter-base using polyimide sidewalls to maximize the high-speed characteristics inherent to HBT devices. By devising an alignment fabrication method, an existing HBT device fabrication process is improved.

Description

임시 에미터 전극과 폴리이미드 측벽막을 이용한 자기정렬형 이종접합 바이폴라 트렌지스터의 제작방법Fabrication method of self-aligned heterojunction bipolar transistor using temporary emitter electrode and polyimide sidewall film

제1도의 (a)∼(i)는 본 발명의 제조공정을 나타낸 단면도.(A)-(i) is sectional drawing which showed the manufacturing process of this invention.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1:완충층(Buffer Layer) 2:부컬렉터층(Subcollector Layer)1: Buffer Layer 2: Subcollector Layer

3:컬렉터층(Collector Layer) 4:베이스층(Base Layer)3: Collector Layer 4: Base Layer

5:에미터층(Emitter Layer) 6:에미터 캡층(Emitter Cap Layer)5: Emitter Layer 6: Emitter Cap Layer

7:실리콘 질화막(SiN Film)7: Silicon Nitride Film (SiN Film)

8:임시 에미터 금속전극(Dummy Emitter Metal Electrode)8: Dummy Emitter Metal Electrode

9:폴리이미드 유전막(Polyimide Dielectric Film)9: Polyimide Dielectric Film

10:폴리이미드 측벽막(Polyimide Sidewall Film)10: Polyimide Sidewall Film

11:에미터 금속전극(Emitter Metal Electrode)11: Emitter Metal Electrode

12:베이스 금속전극(Base Metal Electrode)12: Base Metal Electrode

13:컬렉터 금속전극(Collector Metal Electrode)13: Collector Metal Electrode

14:소자분리 메사(Isolation Mesa)14: Isolation Mesa

15:금속간 절연막(Inter-Dielectric Film)15: Inter-Dielectric Film

16:패드 금속전극(Pad Metal Electrode)16: Pad Metal Electrode

본 발명은 3-5족의 화합물 반도체를 이용하는 이종접합 바이폴라 트렌지스터(Heterojunction Bipolar Transistor : HBT)를 제작방법에 관한 것으로서, 공정상의 특수한 제조방법을 사용하여, 베이스 전극을 에미터에 대하여 자기정렬이 가능하도록 함으로써 소자의 고속특성을 개선할 수 있도록 한 이종접합 바이폴라 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of fabricating a heterojunction bipolar transistor (HBT) using a compound semiconductor of a group 3-5, and is capable of self-aligning a base electrode with respect to an emitter using a special manufacturing method in the process. The present invention relates to a method for manufacturing a heterojunction bipolar transistor that can improve the high speed characteristics of a device.

HBT 소자는 실리콘 바이폴라 트랜지스터에 비하여 에미터 밴드갭이 큼으로 해서 에미터 주입효율이 향상되고, 아울러 소자를 고농도 베이스와 저농도의 에미터로 설계하는 것이 가능하기 때문에 베이스 저항의 저하와 에미터-베이스 용량의 감소를 유발하여 결과적으로는 우수한 고주파 특성이 달성될 수 있다.HBT devices have a larger emitter bandgap than silicon bipolar transistors, resulting in improved emitter injection efficiency and lower base resistance and emitter-base design. A reduction in capacity can be brought about and consequently good high frequency characteristics can be achieved.

이러한 장점으로 인해 HBT 소자는 10Gbps급 이상의 전송속도를 갖는 광통신 시스템 전자회로 등 집적회로에 광범위하게 응용되고 있다.Due to these advantages, HBT devices are widely applied to integrated circuits such as optical communication system electronic circuits having a transmission speed of 10Gbps or more.

그러나 이와 같은 HBT 고유의 고속특성을 발휘하기 위해서는 기생저항이나 기생용량과 같은 각종 기생효과의 발생을 억제해야 하는데, 기생효과의 주된 원인은 외부 베이스 영역에서의 표면재결합 전류, 혹은 기생저항의 필요없는 생성이다.However, in order to exhibit high speed characteristics inherent to HBT, it is necessary to suppress the occurrence of various parasitic effects such as parasitic resistance and parasitic capacitance. The main cause of parasitic effect is that there is no need for surface recombination current or external parasitic resistance in the outer base region. Produce.

따라서 자기정렬 공정을 통하여 베이스 전극을 에미터 영역에 최대한 접근시킴으로써 기생효과를 가능한 한 사전에 차단하여 소자 특성을 극대화하는 것이 중요하다.Therefore, it is important to maximize the device characteristics by blocking the parasitic effect as far as possible by bringing the base electrode close to the emitter region through the self-aligning process.

일본의 NTT사와 NEC사를 중심으로 실리콘 산화막(SiO2)이나 실리콘 질화막(SiN)을 전면에 도포하여 반응성 이온식각(RIE) 방법에 의해 에미터 옆면에 유전체 측벽을 만들고, 이를 이용하여 에미터와 베이스 전극의 자기정렬을 형성하는 방법이 성행하고 있다.A silicon oxide film (SiO 2 ) or a silicon nitride film (SiN) is applied to the entire surface of Japan's NTT and NEC companies to make dielectric sidewalls on the side of the emitter by reactive ion etching (RIE). Background Art A method of forming self-alignment of base electrodes is prevalent.

이러한 연구배경속에 본 발명에서는 HBT 소자 제작시 기존의 자기정렬 제조방법을 사용하지 않고, 실리콘 질화막에 의한 임시(Dummy) 에미터 전극과 폴리이미드 측벽을 활용하여 베이스 전극을 에미터에 자기정렬시킴으로써 통상의 방법보다 공정의 신뢰성과 재현성을 개선하여 HBT 소자 특성을 극대화하도록 고안하였다.In the background of this research, the present invention does not use a conventional self-aligning method for fabricating an HBT device, but uses a dummy emitter electrode and a polyimide sidewall by silicon nitride to self-align the base electrode to the emitter. It is designed to maximize the characteristics of HBT devices by improving the reliability and reproducibility of the process.

본 발명을 첨부 도면에 의거하여 상세히 기술하면 다음과 같다.The present invention will be described in detail with reference to the accompanying drawings as follows.

제1도는 본 발명에 의한 HBT 소자에서의 에미터-베이스 자기정렬 제조공정을 나타내는 단면도이다.1 is a cross-sectional view showing an emitter-base self-alignment manufacturing process in an HBT device according to the present invention.

제1도의 (a)를 참고하여, 통상적인 HBT 구조와 같이 반절연성 화합물 반도체(S.I. GaAs) 기판(20) 위에 완충층(1), 부컬렉터층(2), 컬렉터층(3), 베이스층(4), 에미터층(5), 마지막으로 에미터 캡층(6)을 차례로 성장시키고, 그 다음에 임시 에미터로 활용하기 위한 SiN막(7)을 웨이퍼 전면에 증착한다.Referring to (a) of FIG. 1, the buffer layer 1, the sub-collector layer 2, the collector layer 3, and the base layer are disposed on the semi-insulating compound semiconductor (SI GaAs) substrate 20, as in the conventional HBT structure. 4), the emitter layer 5 and finally the emitter cap layer 6 are grown in turn, and then a SiN film 7 for use as a temporary emitter is deposited on the entire surface of the wafer.

이후, 제1도 (b)와 같이, 건식식각(dry etching) 방법에 의해 SiN(8)을 수직하게 형성하고, 또한 제1도 (c)에서 도시된 바와 같이 에미터 캡층(6) 및 에미터층(5)의 일부를 식각한다.Thereafter, as shown in FIG. 1 (b), the SiN 8 is formed vertically by a dry etching method, and also the emitter cap layer 6 and the emi as shown in FIG. A part of the foundation layer 5 is etched.

이렇게 남겨진 에미터 잔류층은 건식식각시 발생한 격자손상과 외부 베이스 영역의 노출에 의한 표면 재결합을 방지하기 위한 역할을 하며, 기존에 사용되는 방법과 유사하다.The remaining emitter layer serves to prevent surface recombination caused by lattice damage and exposure of the outer base region during dry etching, and is similar to the conventional method.

이어서 제1도 (d)와 같이, 폴리이미드(10)를 전면에 도포하고 경화 열처리(imidization)를 한 후, 산소 플라즈마를 이용하여 반응성 이온 식각 방법에 의해 방향성 식각을 하면 제1도 (e)와 같이 임시 에미터의 옆면에 폴리이미드 측벽(10)이 얻어진다.Subsequently, as shown in FIG. 1 (d), the polyimide 10 is applied to the entire surface and subjected to a hardening heat treatment, followed by directional etching by reactive ion etching using oxygen plasma. The polyimide sidewall 10 is obtained on the side of the temporary emitter as shown.

또한, 바로 잔류 에미터층(5)을 제거하여, (f)도에서 처럼 앞에서 건식식각에 의해 손상된 층을 없애고 베이스 전극이 형성될 베이스 표면을 노출시킨다.In addition, the residual emitter layer 5 is immediately removed to remove the layer damaged by the dry etching as previously shown in (f) and to expose the base surface on which the base electrode is to be formed.

여기서, 희석된 불산용액으로써 임시 에미터(8)를 식각해내고, 에미터 금속전극(11)과 베이스 금속전극(12)을 동시에 증착하면 제1도 (g)와 같이 폴리이미드와 임시 에미터층에 의한 단차로 인해 베이스 금속전극(12)이 에미터 영역으로부터 분리되어 형성됨으로써 자기정렬이 가능해진다.Here, when the temporary emitter 8 is etched with diluted hydrofluoric acid solution and the emitter metal electrode 11 and the base metal electrode 12 are simultaneously deposited, the polyimide and the temporary emitter layer as shown in FIG. Due to the step difference, the base metal electrode 12 is formed separately from the emitter region, thereby enabling self-alignment.

그리고 통상적인 방법대로 제1도 (h)와 같이 컬렉터 금속전극(13)과 소자분리를 위한 메사(14)를 형성한다.As shown in FIG. 1 (h), the collector metal electrode 13 and the mesa 14 for device isolation are formed in a conventional manner.

이 때 중요한 것은 에미터와 베이스 전극 증착시 자기정렬이 용이하도록 임시 에미터 전극의 두께보다 얇게 하기 때문에 에미터, 베이스, 컬렉터 상에 최종 전극을 형성할 때 단락의 우려가 있으므로, (i)도처럼 금속간 절연막(15)을 증착하기 전에 기존의 폴리이미드 측벽(10)을 사전에 제거하여 패드 금속전극(16)의 단차피복(step coverage)이 잘 되도록 한다.At this time, it is important to make the final electrode on the emitter, the base, and the collector shorter than the thickness of the temporary emitter electrode to facilitate self-alignment when depositing the emitter and the base electrode. Prior to depositing the RM interlayer insulating film 15, the existing polyimide sidewall 10 is removed in advance so that the step coverage of the pad metal electrode 16 is good.

Claims (1)

반절연성 화합물 반도체 기판 위에 완충층(1), 부컬렉터층(2), 컬렉터층(3), 베이스층(4), 에미터층(5) 및 에미터 캡층(6)을 순차로 성장시킨 웨이퍼 위에 이종접합 구조의 바이폴라 트랜지스터(HBT)를 제작하는 방법에 있어서, 상기 웨이퍼 전면에 임시 에미터로 활용하기 위한 실리콘 질화막(7)을 증착한 후 그 실리콘 질화막(7)을 건식식각 방법에 의해 수직한 형상을 갖도록 식각하여 임시 에미터 전극(8)을 형성하는 제1공정과; 노출된 상기 에미터 캡층(6) 및 상기 에미터층(5) 일부를 식각하는 제2공정과; 상기 식각이 끝난 전면에 폴리이미드를 도포하고 그 폴리이미드를 산소 플라즈마를 이용한 반응성 이온 식각방법에 의해 방향성 식각을 하여 상기 식각되어 남은 에미터층(5) 및 임시 에미터 전극(8)의 측면에 폴리이미드 측벽막(10)을 형성하고, 잔류 에미터층(5)을 제거하여 베이스 표면을 노출시키는 제3공정과, 상기 임시 에미터 전극(8)을 식각해서 선택적으로 제거하고 에미터 전극(11)과 베이스 전극(12)을 동시에 증착하여서 폴리이미드 측벽막에 의한 단차를 이용하여 베이스 전극의 에미터에 대한 자기정렬이 가능하도록 하는 제4공정과; 및 에미터, 베이스 및 컬렉터 전극과 소자분리 메사의 형성이 완료된 후 상기 형성된 폴리이미드 측벽막(10)을 선택적으로 폴리이미드 제거제를 사용하여 제거하여서, 이후의 패드 전극형성시 금속배선의 단락이 생기지 않도록 하는 제5공정을 포함하는 것을 특징으로 하는 이종접합 바이폴라 트랜지스터의 제작방법.Heterogeneous on a wafer in which a buffer layer 1, a subcollector layer 2, a collector layer 3, a base layer 4, an emitter layer 5 and an emitter cap layer 6 are sequentially grown on a semi-insulating compound semiconductor substrate In the method of manufacturing a bipolar transistor (HBT) having a junction structure, after depositing a silicon nitride film 7 for use as a temporary emitter on the entire surface of the wafer, the silicon nitride film 7 is vertically formed by a dry etching method. Etching to form a temporary emitter electrode 8; Etching the exposed emitter cap layer (6) and part of the emitter layer (5); The polyimide is applied to the entire surface of the etched surface, and the polyimide is directionally etched by a reactive ion etching method using an oxygen plasma, so that the polyimide is formed on the sides of the etched remaining emitter layer 5 and the temporary emitter electrode 8. A third step of forming the mid sidewall film 10, removing the residual emitter layer 5 to expose the base surface, and selectively removing the temporary emitter electrode 8 by etching the emitter electrode 11. And a fourth step of depositing the base electrode 12 at the same time to enable self-alignment of the emitters of the base electrode by using the step by the polyimide sidewall film; After the formation of the emitter, the base and the collector electrode and the device isolation mesa is completed, the formed polyimide sidewall film 10 is selectively removed using a polyimide remover, so that a short circuit of the metal wiring may not occur during the subsequent pad electrode formation. And a fifth step of preventing the heterojunction bipolar transistor.
KR1019940036373A 1994-12-23 1994-12-23 Fabrication method of self-aligned hbt by forming dummy emitter electrode and polyimide sidewall KR0146652B1 (en)

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