KR0140444B1 - Manufacture of bipolar device - Google Patents
Manufacture of bipolar deviceInfo
- Publication number
- KR0140444B1 KR0140444B1 KR1019940017446A KR19940017446A KR0140444B1 KR 0140444 B1 KR0140444 B1 KR 0140444B1 KR 1019940017446 A KR1019940017446 A KR 1019940017446A KR 19940017446 A KR19940017446 A KR 19940017446A KR 0140444 B1 KR0140444 B1 KR 0140444B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- layer
- substrate
- etching
- insulator
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 239000012212 insulator Substances 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 238000000206 photolithography Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 229910052796 boron Inorganic materials 0.000 claims description 2
- -1 boron ions Chemical class 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 239000012811 non-conductive material Substances 0.000 claims 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
본 발명은 매몰층과 매몰층의 사이에 산화막을 사용하러 격리시킴으로서 소자면적을 감소시키고 회로의 동작속도를 증가하도록 하는 바이폴라 소자의 제조방법에 관한 것이다.The present invention relates to a method for fabricating a bipolar device that reduces the device area and increases the operating speed of the circuit by isolating an oxide film between the buried layer and the buried layer.
본 발명은 바이폴라 소자의 제조방법에 있어서, (1)반도체기판위에 제1장벽산화막과 제1질화막을 차례로 증착하고 격리영역을 형성할 부위의 제1질화막, 제1장벽산화막을 사진식각공정으로 차례로 식각한후 기판을 소정의 깊이로 식각하여 기판의 오픈부위를 형성하는 단계와, (2)채널스톱층을 형성할 불순물이온을 주입하고 기판의 오픈 부위에 격리층을 형성하는 단계와, (3)매몰층 영역을 사진식각공정으로 노출시켜 매몰층을 형성하는 단계와, (4)기판 전면에 에피층을 형성하고, 에피층 위에 제2장벽산화막과 제2질화막을 증착하는 단계와, (5)제1절연체 상부의 제2질화막과 제2장벽산화막을 일부 식각하는 단계와, (6)이온주입한 후, 산화시켜 제1절연체의 상부에 제2산화막을 형성하는 단계를 포함하는 바이폴라 소자 제조방법이다.In the method of manufacturing a bipolar device, (1) a first barrier oxide film and a first nitride film are sequentially deposited on a semiconductor substrate, and the first nitride film and the first barrier oxide film at a portion where an isolation region is to be formed are sequentially formed by a photolithography process. Etching and then etching the substrate to a predetermined depth to form an open portion of the substrate, (2) implanting impurity ions to form the channel stop layer and forming an isolation layer in the open portion of the substrate, (3 Exposing the buried layer region by a photolithography process to form a buried layer, (4) forming an epitaxial layer on the entire surface of the substrate, and depositing a second barrier oxide film and a second nitride film on the epitaxial layer, (5 Manufacturing a bipolar device comprising partially etching the second nitride film and the second barrier oxide film on the first insulator, and (6) ion implantation followed by oxidation to form a second oxide film on the first insulator. Way.
Description
제1도는 종래의 기술에 의하여 제조한 소자의 단면도이고,1 is a cross-sectional view of a device manufactured by the prior art,
제2도는 본 발명의 기술의 주요공정도이다.2 is a main process diagram of the technique of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 21:반도체기판 12, 22:매몰층11, 21: semiconductor substrate 12, 22: buried layer
13:격리층 14, 24:에피층13: Insulating layer 14, 24: Epi layer
15:장벽산화막 16:질화막15: barrier oxide film 16: nitride film
17, 23:필드산화막 27-1:제1장벽산화막17, 23: field oxide film 27-1: first barrier oxide film
27-2:제1절화막 3-1, 23-2, 23-3, 23-4:제1절연체27-2: First cut film 3-1, 23-2, 23-3, 23-4: First insulator
25:제2장벽산화막 26:제2질화막25: second barrier oxide film 26: second nitride film
본 발명은 바이폴라 트랜지스터의 제조방법에 관한 것으로서, 특히, 선택적산화공정을 이용하여 매몰층 간을 격리시켜서 소자면적의 감소 및 동작속도를 향상시키는 바이폴라 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor, and more particularly, to a method for fabricating a bipolar device by separating an buried layer using a selective oxidation process to reduce device area and improve operation speed.
바이폴라 소자는 액티브영역 하부에 불순물로 도핑딘 불순물영역인 매몰층을 형성하게 되는데, 종래에는 다수개의 매몰층의 사이에 매몰층과 반대형의 불순물로 도핑된 영역을 형성하여 매몰층을 격리하는 방법을 사용하여 왔다.The bipolar device forms a buried layer, which is an impurity doped with an impurity, under the active region. Conventionally, a method of isolating a buried layer by forming a doped region with an impurity opposite to the buried layer between a plurality of buried layers. Has been used.
제1도는 종래의 방법에 의한 바이폴라 소자 매몰층의 격리구조를 도시한 것이다.1 shows an isolation structure of a bipolar element buried layer by a conventional method.
도면을 참조하여 바이폴라 소자의 제조공정 중에서 액티브영역을 격리하는 필드산화막을 형성하는 단계까지의 공정을 설명하면 다음과 같다.Referring to the drawings, a process up to the step of forming the field oxide film that isolates the active region from the bipolar device manufacturing process will be described.
먼저 초기산화공정으로 반도체기판(11)상에 산화막을 형성한다.First, an oxide film is formed on the semiconductor substrate 11 by an initial oxidation process.
다음 포토레지스트를 이용하여 포토레지스트패턴을 만들어서 이 패턴을 사용하여 매몰층을 형성할 부위의 산화막을 제거한다.Next, a photoresist pattern is formed using the photoresist, and the oxide film at the site where the buried layer is to be formed is removed using this pattern.
다음 Sb2O3를 증착하고 불순물을 확산시켜서 반도체기판 내에 N형으로 도핑된 매몰층(Buride Layer, 12)을 형성한다.Next, Sb 2 O 3 is deposited and impurities are diffused to form an N-type doped buried layer 12 in the semiconductor substrate.
산화막을 다시 증착하고, N형의 매몰층을 격리하기 위한 P형의 불순물영역을 형성할 부위를 포토레지스트를 이용하여 패턴을 형성하고 패턴을 이용하여 산화막을 식각하여 산화막마스크를 형성한다.The oxide film is deposited again, and a pattern is formed using a photoresist to form a P-type impurity region for isolating the N-type buried layer, and the oxide film is etched using the pattern to form an oxide film mask.
다음 산화막으로 형성한 이온주입마스크를 이용하여 매몰층과 반대형의 불순물이온을 주입하여 격리층(13)을 형성한다.Next, the isolation layer 13 is formed by implanting impurity ions opposite to the buried layer using an ion implantation mask formed of an oxide film.
다음 기판 상에 형성한 모든 산화막을 제거한다.Next, all the oxide films formed on the substrate are removed.
이 단계까지의 공정을 완료한 후의 기판에는 바이폴라 소자의 N형 매몰층이 형성되고 N형 매몰층과 또다른 N형 매몰층을 격리하는 P형 격리층이 기판 내에 형성된다.After completion of the process up to this step, an N-type buried layer of a bipolar element is formed, and a P-type isolation layer is formed in the substrate to isolate the N-type buried layer from another N-type buried layer.
이러한 구조 위에 에피층(14)을 성장시키고 다시 산화공정을 진행하여서 장벽산화막(15)을 질화막(16)을 증착한다.The epitaxial layer 14 is grown on the structure and the oxidation process is performed again to deposit the barrier oxide film 15 on the nitride film 16.
소자영역과 주변의 다른 소자영역과의 격리영역을 포토레지스트로 정의하고 격리영역 상의 질화막 및 산화막을 식각하여 마스크패턴을 형성한다.The isolation region between the device region and other peripheral device regions is defined as a photoresist, and the nitride film and the oxide film on the isolation region are etched to form a mask pattern.
다음 이온을 주입하여 불순물층을 형성하고 필드산화공정으로 필드산화막(17)을 만든다.Next, ions are implanted to form an impurity layer, and a field oxide film 17 is formed by a field oxidation process.
위에서 설명한 종래의 기술에서는 매몰층과 격리층 사이에 간격을 두어야 하므로 소자면적이 증가하였다.In the conventional technique described above, the area of the device is increased because a space is required between the buried layer and the isolation layer.
또한 콜렉터-기판의 기생 캐패시턴스(Parasitic Capacitance)를 증가시켜서 히로의 동작속도(Speed Performance)를 저하시켰다.In addition, the parasitic capacitance of the collector-substrate was increased to decrease the speed performance of the Hiro.
본 발명은 매몰층과 매몰층의 사이에 산화막을 사용하여 격리시킴으로서 소자면적을 감소시키고 회로의 동작속도를 증가하도록 하는 바이폴라 소자의 제조방법을 제공하는데에 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a bipolar device which reduces the device area and increases the operation speed of a circuit by isolating an oxide film between the buried layer and the buried layer.
본 발명은 바이폴라 소자의 제조방법에 있어서, (1)반도체기판위에 제1장벽산화막과 제1질화막을 차례로 증착하고 격리영역을 형성할 부위의 제1질화막, 제1장벽산화막을 사진식각공정으로 차례로 식각한후 기판을 소정의 깊이로 식각하여 기판의 오픈부위를 형성하는 단계와, (2)채널스톱층을 형성할 불순물이온을 주입하고 기판의 오픈 부위에 격리층을 형성하는 단계와, (3)매몰층 영역을 사진식각공정으로 노출시켜 매몰층을 형성하는 단계와, (4)기판 전면에 에피층을 형성하고, 에피층 위에 제2장벽산화막과 제2질화막을 증착하는 단계와, (5)제1절연체 상부의 제2질화막과 제2장벽산화막을 일부 식각하는 단계와, (6)이온주입한 후, 산화시켜 제1절연체의 상부에 제2산화막을 형성하는 단계를 포함하는 바이폴라 소자 제조방법이다.In the method of manufacturing a bipolar device, (1) a first barrier oxide film and a first nitride film are sequentially deposited on a semiconductor substrate, and the first nitride film and the first barrier oxide film at a portion where an isolation region is to be formed are sequentially formed by a photolithography process. Etching and then etching the substrate to a predetermined depth to form an open portion of the substrate, (2) implanting impurity ions to form the channel stop layer and forming an isolation layer in the open portion of the substrate, (3 Exposing the buried layer region by a photolithography process to form a buried layer, (4) forming an epitaxial layer on the entire surface of the substrate, and depositing a second barrier oxide film and a second nitride film on the epitaxial layer, (5 Manufacturing a bipolar device comprising partially etching the second nitride film and the second barrier oxide film on the first insulator, and (6) ion implantation followed by oxidation to form a second oxide film on the first insulator. Way.
제2도의 (a)내지 (h)은 본 발명의 주요공정도를 도시한 것이다.(A)-(h) of FIG. 2 show the main process diagram of this invention.
첨부한 도면을 참조하여 본 발명의 일실시예를 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
제2도의 (a)와 같이 반도체기판(21)위에 제1장벽산화막(27-1)을 증착하고 다시 그 위에 제1질화막(27-2)을 증착한다.As shown in FIG. 2A, the first barrier oxide layer 27-1 is deposited on the semiconductor substrate 21, and the first nitride layer 27-2 is deposited thereon.
제2도의 (b)와 같이 격리영역을 형성할 부위의 제1질화막(27-2)및 제1장벽산화막(27-1)을 사진식각공정으로 차례로 식각한 다음, 기판 KOH를 사용하여 사진식각고정으로 소정깊이 만큼 식각한다.As shown in (b) of FIG. 2, the first nitride layer 27-2 and the first barrier oxide layer 27-1 of the portion to form the isolation region are sequentially etched by a photolithography process, and then photoetched using a substrate KOH. It is fixed and etched by a predetermined depth.
기판이 식각되는 깊이는 이후의 공정에서 만들어질 매몰층을 기준으로 하여서 1/3(매몰층의 깊이)정도의 깊이로 식각한다.The depth at which the substrate is etched is etched to a depth of about 1/3 (depth of the buried layer) based on the buried layer to be made in a later process.
이어서 절연전계를 향상시키기 위한 채널스톱층을 형성하기 위하여 보론이온을 주입한다.Subsequently, boron ions are implanted to form a channel stop layer for improving the insulation field.
다음 제2도의 (c)와 같이 선택전산화(LOCOS)공정을 실시하여서 격리영역의 기판을 산화시켜 제1절연체(23-1)를 형성한다. 이때 제1절연체 형성부위의 기판은 이전 공정에서 소정의 깊이로 식각하여 단차가 형성디어 있으므로, 제1절연체(23-1)형성 후에는 제1절연체의 높이와 기판의 전체 높이를 비슷하게 조절할 수 있다.Next, as shown in (c) of FIG. 2, a selective computerization (LOCOS) process is performed to oxidize the substrate in the isolation region to form the first insulator 23-1. At this time, since the substrate of the first insulator forming portion is etched to a predetermined depth in a previous process, a step is formed. Thus, after the formation of the first insulator 23-1, the height of the first insulator and the overall height of the substrate may be similarly adjusted. .
제2도의 (d)와 같이, 포토레지스트를 이용한 사진식각 및 이온주입 공정으로 매몰층(22)을 형성하고, 제1질화막 및 제1장벽산화막을 식각하여 제거함으로서 매몰층을 노출시킨다. 식각고정에서는 제1절연체(23-2)를 구성하는 글래스의 일부를 함께 제거한다.As shown in FIG. 2D, the buried layer 22 is formed by a photolithography and ion implantation process using a photoresist, and the buried layer is exposed by etching and removing the first nitride film and the first barrier oxide film. In the etching fixing, a part of the glass constituting the first insulator 23-2 is removed together.
제2도의 (e)와 같이 일반적인 에피택셜(Epitaxial)공정으로 기판 전면에 이피층(24)을 형성한다.As shown in FIG. 2E, the epitaxial layer 24 is formed on the entire surface of the substrate by a general epitaxial process.
이어 제2도의 (f)와 같이 에피층 위에 제2장벽산화막(25)과 제2질화막(26)을 증착한다.Subsequently, a second barrier oxide film 25 and a second nitride film 26 are deposited on the epitaxial layer as shown in FIG.
제2도의 (g)와 같이 질화막과 산화막을 다시 제절연체(23-4) 상부에만 선택적으로 제거하고 제1절연체 상부의 에피층을 식각한다.As shown in (g) of FIG. 2, the nitride film and the oxide film are selectively removed again only on the top of the insulator 23-4, and the epi layer on the top of the first insulator is etched.
그리고 제1절연막 상의 필드산화막을 형성할 부위에 사진공정으로 정의하여 채널스톱층(도면에서는 생략함)형성을 위한 이온주입공정을 한다.In addition, an ion implantation process for forming a channel stop layer (not shown in the drawing) is performed by defining a photo process at a portion where a field oxide film is to be formed on the first insulating layer.
이후 제2도의 (h)와 같이 산회시켜서 제1절연체의 상부에 필드산화막(23)을 형성시켜 제1절연체(23-4)와 연결한다. 이러한 필드산화막의 최종두께는 에피층의 두께 이상으로 조절한다.Subsequently, as shown in FIG. 2H, the field oxide film 23 is formed on the first insulator and connected to the first insulator 23-4. The final thickness of the field oxide film is adjusted to be greater than or equal to the thickness of the epi layer.
이와 같은 공정으로 매몰층과 매몰층의 격리영역의 형성을 완료한다.In this manner, the formation of the buried layer and the isolation region of the buried layer is completed.
그리고 필드산화막을 형성할 부위의 에피층을 식각한 뒤에 산화시킴으로서 공정 후의 에피층과 필드산화막의 높이가 같게 된다.The epi layer after the process is etched and oxidized so that the heights of the epi layer and the field oxide film after the process are the same.
본 발명의 효과는 다음과 같다.The effects of the present invention are as follows.
매몰층과 격리층의 간격을 고려하지 않아도 되므로 소자면적을 줄일 수 있다.Since the gap between the buried layer and the isolation layer does not have to be taken into consideration, the device area can be reduced.
제1산화막 형성 후, 매몰층의 포토레지스트, 식각공정의 제거공정에서 산화막을 평탄화함으로서 실리콘의 식각시 문제가 되는 새부리현상(Bird's Beak)을 해결할 수 있다.After the formation of the first oxide film, the oxide film may be planarized in the removal process of the photoresist and etching process of the buried layer, thereby solving the bird's beak problem that may be a problem when etching the silicon.
콜렉터-기판의 증착으로 인한 기생캐패시턴스를 최소화 할 수 있다.Parasitic capacitance due to the deposition of collector-substrate can be minimized.
제1절연체와 필드산화막이 세프얼라인되는 효과가 있다.There is an effect that the first insulator and the field oxide film are aligned.
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