KR0139569B1 - Method of forming metal wiring in semiconductor device - Google Patents
Method of forming metal wiring in semiconductor deviceInfo
- Publication number
- KR0139569B1 KR0139569B1 KR1019940037667A KR19940037667A KR0139569B1 KR 0139569 B1 KR0139569 B1 KR 0139569B1 KR 1019940037667 A KR1019940037667 A KR 1019940037667A KR 19940037667 A KR19940037667 A KR 19940037667A KR 0139569 B1 KR0139569 B1 KR 0139569B1
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- Prior art keywords
- forming
- film
- metal
- metal wiring
- transition metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속배선 형성방법에 있어서; 금속배선이 접속될 하부전도층과 금속배선 사이의 층간 제1절연막상에 상기 층간 제1절연막과 식각선택비를 갖는 제2절연막을 형성하는 단계; 금속배선 접촉창을 형성하여 상기 하부전도층을 노출시키는 단계; 전체 구조 상부에 상기 접촉창을 완전히 매립할 수 있는 두께로 전이금속막을 형성하는 단계; 상기 전이금속막을 블랭키트 에치백하여 제2절연막을 노출시키는 동시에 접촉창 내부에 전이금속-플러그를 형성하는 단계; 상기 제2절연막을 제거하는 단계; 전체구조의 상부에 다시 상기 전이금속-플러그 들뜸 방지막과 금속막을 차례로 형성하는 단계; 금속배선 마스크를 사용하여 상기 금속막과 전이금속-플러그 들뜸 방지막을 패터닝 하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법에 관한 것으로, 전이금속-플러그의 들뜸현상을 완벽하게 방지하여 금속배선의 접속불량을 방지함으로써 소자의 전기적 특성, 신뢰성, 제조 수율을 향상시키는 효과를 가져온다.The present invention provides a method for forming metal wiring of a semiconductor device; Forming a second insulating film having an etch selectivity with the interlayer first insulating film on the first interlayer insulating film between the lower conductive layer and the metal wiring to which the metal wiring is to be connected; Forming a metal wiring contact window to expose the lower conductive layer; Forming a transition metal film in a thickness capable of completely filling the contact window on the entire structure; Blank-etching the transition metal layer to expose a second insulating layer and simultaneously forming a transition metal plug inside the contact window; Removing the second insulating layer; Sequentially forming the transition metal-plug lifting prevention layer and the metal layer on top of the entire structure; The method for forming a metal wiring of a semiconductor device comprising the step of patterning the metal film and the transition metal-plug lifting prevention film using a metal wiring mask, to completely prevent the lifting phenomenon of the transition metal-plug By preventing the poor connection of the metal wiring, the effect of improving the electrical characteristics, reliability, manufacturing yield of the device.
Description
제 1a 도 및 제 1b 도는 종래의 금속배선 형성 공정도.1A and 1B show a conventional metallization process.
제 2a 도 내지 제 2D 도는 본 발명의 일실시예에 따른 금속배선 형성 공정도.2a to 2d is a metal wiring formation process according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11: 실리콘 기판 12: 필드산화막11: silicon substrate 12: field oxide film
13: 고농도 불순물 이온주입영역 14: 산화막13: high concentration impurity ion implantation region 14: oxide film
15: 질화막 16: 콘택홀15: nitride layer 16: contact hole
17, 20: Ti/TiN막 18: 텅스텐막17, 20: Ti / TiN film 18: tungsten film
19: 텅스턴-플러그 21: Al 합금막19: tungsten-plug 21: Al alloy film
본 발명은 반도체 소자 제조 공정중 금속배선 형성밥법에 관한 것으로, 특히 금속콘택을 위한 접촉 내부에 매립된 고융점 전이금속막의 들뜸(peeling) 현상을 방지하는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings during a semiconductor device manufacturing process, and more particularly, to a method for forming metal wirings for semiconductor devices to prevent the phenomenon of lifting of a high melting point transition metal film embedded in a contact for a metal contact.
반도체 소자용 금속배선을 형성함에 있어, 소자의 고집적화로 인하여 어스펙트 비(aspact ratio, 접촉창 깊이/접촉창 크기)의 증가에 따라 통상의 Al 합금막으로는 금속배선의 단선, 콘택저항의 증가, 전자이동(electromigration)등의 신뢰성 문제를 일으키게 되기 때문에, 콘택 홀 또는 비아홀과 같은 접촉창 내부에 플러그를 형성한 후, Al 합금막을 형성하는 방법을 사용하고 있다.In forming the metal wirings for semiconductor devices, due to the high integration of the devices, with the increase of the aspect ratio (contact window depth / contact window size), in general Al alloy films, the disconnection of metal wirings and the increase in contact resistance are increased. In order to cause reliability problems such as electromigration, a method of forming an Al alloy film after forming a plug inside a contact window such as a contact hole or a via hole is used.
제 1a 도 및 제 1b 도는 상기 설명과 같은 종래의 금속배선 형성 공정도로서, 먼저 제 1a 도는 실리콘기판(1)상에 필드산화막(2) 및 불순물 이온주입영역(3)을 형성한 다음에, 전체구조의 상부에 절연용산화막(4)을 형성하고 소정의 콘택홀(5)을 형성한 상태의 단면도이고, 제 1b 도는 상기 콘택홀 내부에 텅스텐-플러그(6)을 형성하고 금속배선(7)을 형성한 상태의 단면도이다.1A and 1B are conventional process diagrams for forming a metal wiring as described above. First, in FIG. 1A, a field oxide film 2 and an impurity ion implantation region 3 are formed on a silicon substrate 1. 1B is a cross-sectional view of the insulating oxide film 4 formed on the upper portion of the structure and a predetermined contact hole 5 formed therein, and FIG. 1B illustrates a tungsten plug 6 formed inside the contact hole and a metal wiring 7. It is sectional drawing of the state formed.
이때, 실리콘기판(1)과 텅스텐-플러그(6)간의 밀착성이 낮기때문에 Ti막 또는 TiN막의 장벽금속을 텅스텐막 증착전에 형성하여 해결 하기도 한다.At this time, since the adhesion between the silicon substrate 1 and the tungsten-plug 6 is low, the barrier metal of the Ti film or the TiN film may be formed before the tungsten film is deposited.
그러나, 상기와 같은 종래의 방법으로는 텅스텐막의 증착두께가 0.6μm 이상의 두꺼운 막으로 형성될때, 그 효과를 기대하기 어렵게 된다.However, in the conventional method as described above, when the deposition thickness of the tungsten film is formed into a thick film of 0.6 mu m or more, it is difficult to expect the effect.
왜냐하면, 증착되는 과정에서 결정자체가 왜곡되어져서 비뚤어지므로 들뜸(peeling) 현상이 유발되기 때문이다.This is because the crystal itself is distorted and skewed during the deposition process, causing a peeling phenomenon.
또한, 텅스텐-플러그를 형성하기 위하여 텅스텐막의 증착후에 블랭키드 텅스텐-에치백(W-Etchback)을 실시하는데, 이때 과도식각에 의해 절연용 산화막과 텅스텐-플러그 사이에 틈이 발생하여 들뜸(peeling) 현상을 가속화시키게 되어, 소자의 접속불량을 일츠키는 치명적인 문제점이 있었다.In addition, a blanked tungsten-etchback (W-Etchback) is carried out after the deposition of the tungsten film to form the tungsten plug, and a gap is generated between the oxide film for insulation and the tungsten plug due to transient etching. ) Accelerated the phenomenon, there was a fatal problem of the connection failure of the device.
따라서, 본 발명은 플러그의 들뜸현상을 방지하여 소자의 신뢰성을 향상시키는 반도체 소자의 금속배선 형성방법을 제공함을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device that prevents the lifting of the plug to improve the reliability of the device.
상기 목적을 달성하기 위하여 안출된 본 발면은 반도체 소자의 금속배선 형성방법에 있어서;The present invention devised to achieve the above object is a method for forming a metal wiring of the semiconductor device;
금속배선이 접속될 하부전도층과 금속배선 사이의 층간 제1절연막상에 상기 층간 제1절연막과 식각선택비를 갖는 제2절연막을 형성하는 단계; 금속 배선 접촉창을 형성하여 상기 하부전도층을 노출시키는 단계; 전체 구조 상부에 상기 접촉창을 완전히 매립할 수 있는 두께로 전이금속막을 형성하는 단계; 상기 전이금속막을 블랭키트에 에치백하여 제2절연막을 노출시키는 동시에 접촉창 내부에 전이금속-플러그를 형성하는 단계; 상기 제2절연막을 제거하는 단계; 전체구조의 상부에 다시 상기 전이금속-플러그 들뜸 방지막과 금속막을 차례로 형성하는 단계; 금속배선 마스크를 사용하여 상기 금속막과 전이금속 플러그 들뜸 방지막을 패터닝 하는 단계를 포함하는 것을 특징으로 한다.Forming a second insulating film having an etch selectivity with the interlayer first insulating film on the first interlayer insulating film between the lower conductive layer and the metal wiring to which the metal wiring is to be connected; Forming a metal wiring contact window to expose the lower conductive layer; Forming a transition metal film in a thickness capable of completely filling the contact window on the entire structure; Etching the transition metal film into a blank kit to expose a second insulating film and simultaneously forming a transition metal plug inside a contact window; Removing the second insulating layer; Sequentially forming the transition metal-plug lifting prevention layer and the metal layer on top of the entire structure; And patterning the metal film and the transition metal plug lifting prevention film using a metal wiring mask.
이하, 첨부된 도면 제 2a 도 내지 제 2D 도를 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings 2A to 2D.
먼저, 제 2a 도는 실리콘기판(11)상에 소정패턴의 필드산화막(12)을 형성하고 고농도 불순물 이온주입영역(13)을 형성한 다음에, 전체 구조의 상부에 절연용 산화막(14)과, 상기 산화막(14)과 다른 식각 선택비를 갖는 절연막인 질화막(15)을 증착하고 사진식각법으로 콘택홀(16)을 형성하여 상기 고농도 불순물 이온주입영역(13)을 노출시킨 상태의 단면도 이다.First, the field oxide film 12 having a predetermined pattern is formed on the silicon substrate 11 and the high concentration impurity ion implantation region 13 is formed. Then, the insulating oxide film 14 is formed on the entire structure. The nitride film 15, which is an insulating film having an etching selectivity different from that of the oxide film 14, is deposited, and the contact hole 16 is formed by photolithography to expose the high concentration impurity ion implantation region 13.
이때, 상기 질화막(15)의 두께는 약 500∼1000Å 정도로 LPCVD 방식으로 형성한다.At this time, the nitride film 15 has a thickness of about 500 to 1000 mW by the LPCVD method.
이어서, 제 2b 도에 도시된 바와같이 전체구조 상부에 장벽금속용 Ti/TiN막(17)을 형성한 다음에, 전체구조 상부에 상기 접촉창을 완전히 매립할 수 있는 두께인 6000Å 이상으로 텅스텐막(18)을 WF6, SiH4, H2가스의 조합으로 형성하고 텅스텐막(18)의 실리사이드화가 되지않는 온도범위(통상 500℃ 내외)에서 열처리한다.Subsequently, as shown in FIG. 2B, a Ti / TiN film 17 for barrier metal is formed on the entire structure, and then a tungsten film having a thickness of 6000 GPa or more, which is a thickness capable of completely filling the contact window, over the entire structure. (18) is formed of a combination of WF 6 , SiH 4 , and H 2 gas and heat-treated in a temperature range (typically around 500 ° C.) in which the tungsten film 18 is not suicided.
계속해서, 제 2c 도와 같이 SF2와 O2가스를 사용하여 텅스텐막(18)과 Ti/TiN막(17)을 블랭키트 에치백을 실시하여 질화막(15)을 노출시킨 다음에, SF6와 C12가스를 사용하여 상기 질화막(15)을 제거하고 전체구조의 상부에 다시 Ti/TiN막(20)을 텅스텐-플러그(19)의 들뜸 방지막으로 형성한다.Subsequently, as shown in FIG. 2C, the tungsten film 18 and the Ti / TiN film 17 were subjected to a blank kit etch back using the SF 2 and O 2 gas to expose the nitride film 15, and then SF 6 And the nitride film 15 is removed using C1 2 gas, and the Ti / TiN film 20 is formed again as an anti-lift film of the tungsten-plug 19 on top of the entire structure.
끝으로, 제 2D 도와 같이 상기 텅스텐-플러그(19)의 들뜸방지막인 Ti/TiN막(20)막 상에 Al 합금막(21)을 증착하고, 금속배선 마스크를 사용하여 A1 합금막(21) 및 Ti/TiN막(20)을 패터닝하여 금속배선을 완료한다.Finally, an Al alloy film 21 is deposited on the Ti / TiN film 20 film, which is an anti-lifting film of the tungsten-plug 19, as in the 2D diagram, and the A1 alloy film 21 is formed using a metal wiring mask. And patterning the Ti / TiN film 20 to complete metallization.
이상, 상기 설명과 같이 이루어지는 본 발명은 질화막의 두께에 따라 절연용 산화막 표면 높이 상부로 돌출되는 텅스텐-플러그를 손쉽게 조절하면서, 돌출된 텅스텐-플러그에 Ti/TiN막의 2차 형성으로 6000Å 이상의 텅스텐막에 의한 들뜸현상을 완벽하게 방지할 수 있게 되어, 금속배선의 접속불량을 방지함으로써 소자의 전기적 특성, 신뢰성, 제조 수율을 향상시키는 효과를 가져온다.As described above, the present invention made as described above is a tungsten film of 6000 Å or more due to the secondary formation of the Ti / TiN film on the protruding tungsten plug while easily adjusting the tungsten plug which protrudes above the surface height of the insulating oxide film according to the thickness of the nitride film. It is possible to completely prevent the lifting phenomenon by, thereby preventing the poor connection of the metal wiring brings the effect of improving the electrical characteristics, reliability, manufacturing yield of the device.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037667A KR0139569B1 (en) | 1994-12-28 | 1994-12-28 | Method of forming metal wiring in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037667A KR0139569B1 (en) | 1994-12-28 | 1994-12-28 | Method of forming metal wiring in semiconductor device |
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| Publication Number | Publication Date |
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| KR960026185A KR960026185A (en) | 1996-07-22 |
| KR0139569B1 true KR0139569B1 (en) | 1998-07-15 |
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| KR1019940037667A KR0139569B1 (en) | 1994-12-28 | 1994-12-28 | Method of forming metal wiring in semiconductor device |
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| KR (1) | KR0139569B1 (en) |
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1994
- 1994-12-28 KR KR1019940037667A patent/KR0139569B1/en not_active IP Right Cessation
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| KR960026185A (en) | 1996-07-22 |
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