KR0139347B1 - Manufacturing method of liquid crystal display using anodizing - Google Patents
Manufacturing method of liquid crystal display using anodizingInfo
- Publication number
- KR0139347B1 KR0139347B1 KR1019940002118A KR19940002118A KR0139347B1 KR 0139347 B1 KR0139347 B1 KR 0139347B1 KR 1019940002118 A KR1019940002118 A KR 1019940002118A KR 19940002118 A KR19940002118 A KR 19940002118A KR 0139347 B1 KR0139347 B1 KR 0139347B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- wiring
- liquid crystal
- gate wiring
- anodization
- Prior art date
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000007743 anodising Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 33
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052804 chromium Inorganic materials 0.000 claims abstract description 10
- 239000011651 chromium Substances 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 8
- 229910004205 SiNX Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 238000002048 anodisation reaction Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 3
- 239000011159 matrix material Substances 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 19
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910003070 TaOx Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 액티브 매트릭스 액정디스플레이(Active matrix liquid crystal:이하 AM LCD라 한다)에 관한 것으로, 게이트 크롬 위에 양극산화 가능한 물질을 성막하고 포토레지스트 패턴을 마스크로 게이트 배선과 패드 부위를 제외한 부분을 전면양극산화하므로서 종래 상하 배선간의 쇼트 방지목적으로 실시되던 절연막의 이중화 공정없이도 양극산화 기법으로 단차 완화 및 테이퍼화를 달성할 수 있어 상하 배선간에 발생되던 쇼트를 방지할 수 있고, 스텝 커버리지(step coverage) 불량에 의한 드레인 배선 오픈을 방지할 수 있어 고신뢰성, 고수율, 고화질을 실현할 수 있을 뿐 아니라 별도의 게이트 크롬 테이퍼 기법없이도 게이트 배선부의 테이퍼가 가능하고 배선 측벽부에 형성된 산화막에 의해 TFT의 신뢰성을 향상시킬 수 있는 고신뢰성의 양극산화를 이용한 액정디스플레이를 구현할 수 있게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal (hereinafter referred to as AM LCD), wherein an anodizable material is deposited on the gate chromium, and a portion of the entire surface except the gate wiring and the pad portion is masked using a photoresist pattern as a mask. By oxidizing, step reduction and tapering can be achieved by anodization without the double layering process of insulating film, which is conventionally used to prevent shorting between upper and lower wirings, and it is possible to prevent shorts generated between upper and lower wirings, and poor step coverage. Drain wiring can be prevented from opening, which enables high reliability, high yield, and high image quality, and enables taper of the gate wiring without a separate gate chrome taper technique, and improves TFT reliability by an oxide film formed on the wiring sidewall. Solution using highly reliable anodization It is possible to implement a display.
Description
제1도는 종래 기술에 의한 액정표시패널의 화소구조를 도시한 평면도.1 is a plan view showing a pixel structure of a liquid crystal display panel according to the prior art.
제2도는 상기 패널의 A-A 절단면을 도시한 단면도,2 is a cross-sectional view showing an A-A cut surface of the panel,
제3도는 본 발명의 일실시예에 따른 액정표시패널의 화소구조를 도시한 평면도,3 is a plan view illustrating a pixel structure of a liquid crystal display panel according to an exemplary embodiment of the present invention;
제4도는 상기 패널의 B-B 절단면을도시한 단면도이다.4 is a cross-sectional view showing a cut line B-B of the panel.
본 발명은 액티브 매트릭스 액정디스플레이(Active matrix liquid crystal:이하 AM LCD라 한다)에 관한 것으로, 보다 상세하게는 TFT LCD의 화소부에 형성된 게이트 배선 및 그 측벽부의 절연막 패턴 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal (hereinafter referred to as AM LCD), and more particularly, to a gate wiring formed in a pixel portion of a TFT LCD and an insulating film pattern forming method thereof.
정보 매체(media)의 휴대화와 고급화의 추세에 힘입어 최근 액정 평판 표시소자는 그 수요가 반도체 곡선과 CRT(Cathod Ray Tube)수요곡선에 따라 점차 증가하고 있다. 이에 부합되는 액정 평판 표시소자로 특히 TFT LCD(Thin Film Transistor Liquid Crystal Display)는 CRT에 필적할 만한 화질과 저소비전력의 장점으로 휴대용 정보 매체의 표시소자가 널리 채용되고 있다.In recent years, the demand for liquid crystal flat panel display devices has gradually increased according to the semiconductor curve and the demand curve of CRT (Cathod Ray Tube). In particular, TFT LCD (Thin Film Transistor Liquid Crystal Display) is a liquid crystal flat panel display device, and display devices of portable information media are widely adopted due to advantages of image quality and low power consumption comparable to CRT.
이와 관련된 종래 액정표시패널의 기본적인 화소구조는 제1도 및 제2도에 도시해 놓은 바와 같다. 여기서 제 1도는 평면도를, 제 2도는 제1도의 A-A를 절단한 단면도를 나타낸다. 상기 도면을 참조로 그 제조공정을 개략적으로 설명하면 아래와 같다. 즉 먼저 유리기판(s)상에 게이트 배선 및 축적용량 패턴을 불투명 금속으로 형성하고 게이트 전극(1)과 게이트 절연막(2), 반도체층(비정질실리콘)(3), 에치스토퍼층을 연속 층착한 후 사진 및 건·습식공정으로 에치스토퍼(4)를 소정 크기로 패터닝시킨다. 그 후 n+비정질실리콘층을 증착하고 사진 및 건식공정으로 패터닝하여 액티브 패턴(5)을 형성한다. 계속해서 상기 패턴(5) 상에 투명전극막을 증착한 후 사진 및 습식공정으로 화소전극(9)을 패터닝하고 소오스/드레인 금속층을 스퍼터 방법으로 적층한 후 사진 및 습식공정으로 소오스/드레인(6)을 패터닝한다. 이 후 상기 소오스/드레인(6)을 마스크로 이용한 건식공정으로 n+층을 식각하고 보호막을 증착하여 TFT패널 제조를 완성한다.The basic pixel structure of the related art liquid crystal display panel is as shown in FIGS. 1 and 2. 1 is a plan view, and FIG. 2 is a sectional view taken along the line A-A of FIG. The manufacturing process is described schematically with reference to the drawings. That is, first, the gate wiring and the storage capacitance pattern are formed of an opaque metal on the glass substrate s, and the gate electrode 1, the gate insulating film 2, the semiconductor layer (amorphous silicon) 3, and the etch stopper layer are successively laminated. Thereafter, the etch stopper 4 is patterned to a predetermined size by a photograph and a dry / wet process. The n + amorphous silicon layer is then deposited and patterned by photo and dry processes to form the active pattern 5. Subsequently, after depositing a transparent electrode film on the pattern (5), patterning the pixel electrode (9) by a photo and wet process, and layering a source / drain metal layer by a sputtering method, the source / drain (6) by a photo and wet process Pattern. After that, the n + layer is etched and the protective film is deposited by a dry process using the source / drain 6 as a mask to complete the TFT panel manufacturing.
상기 공정을 걸쳐 완성된 TFT패널의 원가 절감의 한 방법으로 게이트 금속(1)으로 크롬으로 사용하여 게이트 배선과 패드를 동시에 형성하는 것을 들 수 있는데, 이 경우는 알루미늄 배선 사용시보다 공정을 단순화할 수 있다는 장점을 가지게 된다. 즉 알루미늄 힐럭(hillock) 방지 목적으로 실시하는 양극산화 공정이나 별도의 패드를 사용할 수도 있으나 탄탈륨은 일반적으로 박막 비저항이 약 200μΩ·cm의 고저항 금속이라는 점과, 크롬 정도로 저저항화하기 위해서는 별도의 공정 기법이 필요하다는 단점이 있다. 반면 크롬은 박막 비저항이 50μΩ·cm로 비교적 저항이 낮다. 이러한 크롬 금속을 게이트 배선으로 사용하였을 경우에는, 게이트 크롬과 데이타 배선과의 쇼트를 방지하기 위해서 스퍼터링 방법으로 TaOx를 성막하고 3층막(SiNx/a-Si/n+a-Si)을 PECVD(plasma enhanced chemical vapor deposition)기법으로 증착하거나, 열 CVD 기법으로 SiOx를 성막하고 3층막을 증착하는 방법을 사용하고 있다. 그러나 상기 크롬 금속은 테이퍼 처리하기가 용이하지 않을 뿐 아니라 테이퍼 처리를 하지 않고 배선으로 사용할 경우는 스텝 커버리지(step coverage) 불량으로 데이타 배선이 끊어지거나 스텝부위의 절연막 취약화로 축적용량(storage capacitor) 불량을 유발할 수 있다. 즉, 상기 크롬을 게이트 배선으로 사용시에 게이트 배선과 패드를 동시에 형성할 수 있다는 장점은 있으나 추가 절연막 형성공정이 필요하고, 또한 테이퍼 처리가 용이하지 않아 데이타 배선 단락과 축적용량 불량이 발생할 가능성이 높아지게 되는 문제점이 발생하게 된다.One method of reducing the cost of the TFT panel completed through the above process is to form the gate wiring and the pad at the same time by using chromium as the gate metal (1). In this case, the process can be simplified than when using aluminum wiring. It has the advantage that it is. In other words, anodization process for the purpose of preventing aluminum hillock or a separate pad may be used, but tantalum is generally a high-resistance metal having a thin film resistivity of about 200 µΩ · cm, and a low chromium resistance to reduce the resistance to chromium. The disadvantage is that a process technique is required. Chromium, on the other hand, has a relatively low resistivity of 50 µΩ · cm. When such chromium metal is used as the gate wiring, in order to prevent the short circuit between the gate chromium and the data wiring, TaOx is formed by sputtering and a three-layer film (SiNx / a-Si / n + a-Si) is PECVD (plasma). Evaporation is performed by an enhanced chemical vapor deposition (CVD) technique, or a thermal CVD technique is used to deposit SiOx and deposit a three-layer film. However, the chromium metal is not easy to taper, and when used as a wiring without tapering, data wiring is broken due to poor step coverage or poor storage capacitor due to weak insulation of the stepped portion. May cause. In other words, when the chromium is used as the gate wiring, the gate wiring and the pad can be simultaneously formed, but an additional insulating film forming process is required, and the taper processing is not easy. The problem arises.
이에 본 발명은 상기와 같은 문제점을 해결하기 위한 것으로 게이트 크롬 위에 양극산화 가능한 물질을 성막하고 게이트 배선과 패드 부위를 제외한 부분은 전면양극산화하여 게이트 절연막 보강과 테이퍼 효과를 동시에 제공함으써 고신뢰성 및 수율향상을 달성할 수 있는 양극산화를 이용한 액정디스플레이 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above problems by depositing an anodizable material on the gate chromium and anodizing the entire area except the gate wiring and the pad portion, thereby providing a high reliability and taper effect of the gate insulating film at the same time. It is an object of the present invention to provide a method for manufacturing a liquid crystal display using anodization which can achieve a yield improvement.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 양극산화를 이용한 액정 디스플레이 제조방법은 투명절연기판 상에 게이트 배선, 게이트 전극 및 패드 전극을 양극산화되지 않은 제1금속을 이용하여 형성하는 공정과, 상기 게이트 배선, 게이트 전극 및 패드 전극 상에 양극산화 가능한 제2금속을 성막한 후 상기 게이트 배선, 게이트 전극 및 패드전극보다 좁은 폭의 포토레지스트를 마스크로 하면 양극산화하는 공정과, 상기 제2금속막 상에 SiNx으로 게이트 절연막을 형성하는 공정을 구비하여 이루어진다.According to an embodiment of the present invention, a method of manufacturing a liquid crystal display using anodization includes forming a gate wiring, a gate electrode, and a pad electrode on a transparent insulating substrate using a first metal that is not anodized; Forming a second anodizable metal on the gate wiring, the gate electrode and the pad electrode, and then anodizing the photoresist having a narrower width than the gate wiring, the gate electrode and the pad electrode as a mask; And forming a gate insulating film on the film by SiNx.
본 발명은 상술한 공정에 의해 별도의 게이트 크롬 테이퍼 기법 없이도 게이트 배선부의 테이퍼가 가능할 뿐 아니라 배선 측벽부에 형성된 산화막으로 인해 TFT의 신뢰성을 향상시킬 수 있게 된다.The present invention enables not only the tapering of the gate wiring portion without a separate gate chrome taper technique, but also the reliability of the TFT due to the oxide film formed on the wiring sidewall portion.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 보다 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제3도는 본 발명의 일실시예에 따른 액정패널의 화소구조를 도시한 평면도를 나타낸 것이며, 제4도는 상기 도면의 B-B 절단면을 도시한 단면도를 나타낸 것이다.FIG. 3 is a plan view showing a pixel structure of a liquid crystal panel according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view showing a cut line B-B of the figure.
상기 도면을 참조로 하여 그 제조공정을 살펴보면, 먼저 잘 세정된 투명기판(s) 상에 스퍼터링(sputtering) 방법으로 게이트 금속(1)인 크롬을 성막하고 사진 및 식각공정으로 게이트 배선 및 전극을 형성한다.Referring to the manufacturing process with reference to the drawings, first, chromium, the gate metal 1, is formed by sputtering on a well cleaned transparent substrate s, and gate wirings and electrodes are formed by a photo and etching process. do.
이후 스퍼터링 방법으로 양극산화 가능한 물질인 탄탈륨(7)을 약 500Å 정도의 두께로 성막하고 사진기법으로 게이트 배선 및 패드 전극부를 포토레지스트로 패터닝한다. 이 때 상기 포토레지스트 패턴은 게이트배선 및 패드 전극보다 약 1.5μm 정도 좁게 형성한다. 이것은 마스크 미스 얼라인먼트(mask miss alognment)를 고려한 값이다.Then, a tantalum (7), which is an anodizable material, is formed to a thickness of about 500 GPa by the sputtering method, and the gate wiring and the pad electrode part are patterned by photoresist by a photo technique. In this case, the photoresist pattern is formed to be about 1.5 μm narrower than the gate wiring and the pad electrode. This value takes into account mask miss alognment.
그 후 양극산화 기법으로 전면 양극산화를 실시한다. 이와 같이 할 경우 게이트 배선 및 패드 전극부는 양극산화가 되지 않아 배선 이중화로 단락을 방지할 수 있게 된다. 뿐만 아니라 게이트 배선 및 패드 전극 주변부가 양극산화되어 약 1.5배 정도의 부피 팽창을 하게 되므로 크롬 배선(1)과 기판(s) 층간의 단차를 완화시킬 수 있다. 또한 종래에는 축적 불량 및 상하 배선간 단락으로 별도의 게이트 절연막 형성이 추가적으로 실시되었으나, 본 발명에 의하면 배선 측벽부에 양극산화막(8)으로 절연막이 형성되어 TFT 신뢰성 향상 및 상하 배선간 쇼트를 방지할 수 있으며, 단차 완화 및 테이퍼(taper)화로 드레인 배선 오픈(open)을 방지할 수 있고 단차로 인한 러빙(rubbing) 결함발생도 억제할 수 있다. 즉 이와 같은 방법에 의하면 게이트 배선 이중화로 게이트 오픈을 방지할 수 있고, 게이트 배선에 양극산화막인 절연막이 형성되어 TFT 신뢰성을 향상시킬 수 있으며 상하 배선간 쇼트를 방지할 수 있을 뿐 아니라, 단차 완화 및 테이퍼화로 드레인 배선 오픈을 방지할 수 있어 수율향상 및 고신뢰성, 화질향상을 실현할 수 있다.After that, the entire surface anodization is performed by anodization. In this case, the gate wiring and the pad electrode portion are not anodized, and thus, a short circuit can be prevented by double wiring. In addition, since the gate wiring and the peripheral portion of the pad electrode is anodized to have about 1.5 times volume expansion, the step difference between the chrome wiring 1 and the substrate s layer can be alleviated. In addition, in the related art, a separate gate insulating film was additionally formed due to poor accumulation and a short circuit between the upper and lower wirings. However, according to the present invention, an insulating film is formed by the anodizing film 8 in the wiring sidewall portion to improve TFT reliability and prevent short circuit between upper and lower wirings. It is possible to prevent the opening of the drain wiring by reducing the step and tapering, and also to prevent the occurrence of rubbing defects due to the step. That is, according to this method, gate open can be prevented by doubled gate wiring, and an insulating film, which is an anodized film, is formed on the gate wiring to improve TFT reliability, prevent short circuit between upper and lower wiring, and reduce step difference. The taper makes it possible to prevent the drain wiring to be opened, thereby improving yield, high reliability, and improving image quality.
계속해서 상기 패턴 상에 PECVD(plasma enhanced chemical vapor deposition)기법으로 반도체층(3)인 SiNx/a-Si/etch-stopper SiNx를 연속 성막한다.Subsequently, SiNx / a-Si / etch-stopper SiNx, which is the semiconductor layer 3, is continuously formed on the pattern by a plasma enhanced chemical vapor deposition (PECVD) technique.
이후 사진 및 식각기법으로 에치스토퍼 패턴(4)을 형성하고 PECVD 기법으로 n+비정질실리콘층을 성막하고 사진 및 식각기법으로 액티브 패턴(5)을 형성한다.Thereafter, the etch stopper pattern 4 is formed by photo and etching techniques, and the n + amorphous silicon layer is formed by PECVD, and the active pattern 5 is formed by photo and etching techniques.
그 다음 소오스/드레인 금속(6)을 스퍼터링 기법으로 성막하고 사진 및 식각공정으로소오스/드레인 배선 및 전극을 형성한다.The source / drain metal 6 is then formed by sputtering, and the source / drain interconnects and electrodes are formed by photo and etching processes.
이후 상기 소오스/드레인 전극을 마스크로 하여 드라이 에치(dry etch) 기법으로 n+층(5)을 식각하고 상기 패턴 상에 보호막을 PECVD기법으로 성막한다.After that, the n + layer 5 is etched using a dry etch method using the source / drain electrodes as a mask, and a protective film is formed on the pattern by PECVD.
그다음 사진 및 식각 기법으로 패드 전극부를 오픈하여 TFT 기판제조를 완성한다.The pad electrode is then opened by photo and etching techniques to complete the manufacture of the TFT substrate.
한편, 상기 공정은 제4도에 제시된 바와 같은 에치스토퍼 타입 외에 도시되지 않은 에치백 타입에도 적용 가능하다. 이를 간략하게 설명하면 아래와 같다.On the other hand, the process is applicable to an etchback type not shown in addition to the etch stopper type as shown in FIG. This is briefly described as follows.
즉, 투명기판 상에 게이트 전극 및 게이트 배선(스캔)을 먼저 형성하고 양극산화 가능한 금속을 상기 기판상에 도포한다. 그후 상기 게이트 전극 및 게이트 배선의 폭보다 좁은 폭의 포토레지스트 패턴으르 마스크로 하여 전면 양극산화를 실시하고, 절연막을 도포한다. 이어서 일반적인 수순에 의해 반도체층, n+비정질실리콘층을 도포하고 소정 형상(island 형상)으로 패터닝한다. 이후 상기 패턴 상에 ITO층을 도포하고 화소전극을 패터닝한 뒤 소오스/드레인 금속을 도포하고 패터닝하여 소오스/드레인 배선 및 전극을 형성하므로써 본 공정을 완료한다.That is, a gate electrode and a gate wiring (scan) are first formed on the transparent substrate and anodized metal is coated on the substrate. After that, the entire surface is anodized using a photoresist pattern having a width narrower than that of the gate electrode and the gate wiring, and an insulating film is applied. Subsequently, the semiconductor layer and the n + amorphous silicon layer are coated in a general procedure and patterned into a predetermined shape (island shape). After the ITO layer is applied on the pattern and the pixel electrode is patterned, the source / drain metal is applied and patterned to form the source / drain wiring and the electrode, thereby completing the process.
상술한 바와 같이 본 발명에 의하면, 별도의 게이트 크롬 기법 없이도 게이트 배선부의 테이퍼가 가능할 뿐 아니라 배선 측벽부에 형성된 산화막에 의해 TFT의 신뢰성을 향상시킬 수 있게 된다. 또한 종래 상하 배선간의 쇼트 방지목적으로 실시되던 게이트 절연막의 이중화 공정없이도 양극산화 기법으로 단차 완화 및 테이퍼화를 달성할 수 있어 상하 배선간에 발생되던 쇼트를 방지할 수 있고, 스텝 커버리지(step coverage) 불량에 의한 드레인 배선 오픈을 방지할 수 있어 고신뢰성, 고수율, 고화질을 실현할 수 있게 된다.As described above, according to the present invention, not only the taper of the gate wiring portion can be tapered without a separate gate chrome technique, but also the reliability of the TFT can be improved by the oxide film formed on the wiring sidewall portion. In addition, it is possible to reduce the step difference and taper by anodizing without the gate insulating layer redundancy process, which has been conventionally performed to prevent short circuit between the upper and lower wirings, thereby preventing shorts generated between the upper and lower wirings, and poor step coverage. The drain wiring can be prevented from opening, and high reliability, high yield, and high quality can be realized.
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