KR0139267B1 - Forming method of field oxide in a semicondcutor device - Google Patents
Forming method of field oxide in a semicondcutor deviceInfo
- Publication number
- KR0139267B1 KR0139267B1 KR1019940038573A KR19940038573A KR0139267B1 KR 0139267 B1 KR0139267 B1 KR 0139267B1 KR 1019940038573 A KR1019940038573 A KR 1019940038573A KR 19940038573 A KR19940038573 A KR 19940038573A KR 0139267 B1 KR0139267 B1 KR 0139267B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- forming
- nitride film
- film
- silicon substrate
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 5
- 241000293849 Cordylanthus Species 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 소자의 필드산화막 형성방법에 관한 것으로, 질화막 상부에 층덮힘(Step coverage)특성이 좋지 않은 저온산화막(LTO막)을 형성한 후 블랜켓식각(Blanket etch)하여 실리콘기판을 리세스(recess)구조가 되도록 하므로써 실리콘기판으로 가해지는 스트레스(Stress)를 감소시켜 실리콘기판에 생성되는 결함(Defect)을 감소시키며 버즈빅(Bird's beak)을 감소시키는 동시에 평탄화특성을 향상시킬 수 있도록 한 반도체 소자의 필드산화막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a field oxide film of a semiconductor device, wherein a silicon oxide substrate is recessed by forming a blanket etch after forming a low temperature oxide film (LTO film) having poor step coverage characteristics on the nitride film. The semiconductor is designed to reduce the stress applied to the silicon substrate by reducing the structure of the silicon substrate, thereby reducing the defects generated on the silicon substrate, reducing the bird's beak and improving the planarization characteristics. A field oxide film forming method of a device is provided.
Description
제 1a 내지 제 1c 도는 종래 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a field oxide film of a conventional semiconductor device.
제 2a 내지 제 2g 도는 본 발명에 따른 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도.2A to 2G are cross-sectional views of a device for explaining a method of forming a field oxide film of a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1: 실리콘기판2: 패드 산화막1: silicon substrate 2: pad oxide film
3: 폴리실리콘층4 및 14: 제 1 질화막3: polysilicon layers 4 and 14: first nitride film
5: 소자분리층6 및 16: 제 2 질화막5: device isolation layers 6 and 16: second nitride film
6a: 질화막스페이서7 및 17: 필드산화막6a: nitride film spacers 7 and 17: field oxide film
13: 버퍼폴리실리콘층15: 저온산화막13: buffer polysilicon layer 15: low temperature oxide film
본 발명은 반도체 소자의 필드산화막 형성방법에 관한 것으로, 특히 질화막 상부에 층덮힘(Step coverage)특성이 좋지 않은 저온산화막(LTO막)을 형성한 후 블랜켓식각(Blanket etch)하여 실리콘기판을 리세스(recess)구조가 되도록 하므로써 실리콘기판으로 가해지는 스트레스(Stress)를 감소시켜 실리콘기판에 생성되는 결함(Defect)을 감소시키며 버즈빅(Bird's beak)을 감소시키는 동시에 평탄화특성을 향상시킬 수 있도록 한 반도체 소자의 필드산화막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a field oxide film of a semiconductor device. In particular, a low temperature oxide film (LTO film) having a poor step coverage property is formed on a nitride film, and then a silicon substrate is removed by blanket etching. The recess structure reduces stress applied to the silicon substrate, reduces defects generated on the silicon substrate, reduces bird's beak and improves flattening characteristics. A field oxide film forming method of a semiconductor device.
일반적으로 반도체 소자의 제조공정에서 소자와 소자사이를 분리시키기 위하여 소자분리막인 필드산화막을 형성시키는데, 소자가 고집적화됨에 따라 최소한의 소자분리영역유지로 인한 충분한 활성영역의 확보, 버즈빅의 감소 및 평탄화특성의 향상 등이 요구되어진다. 그러면 종래 256M디램(DRAM) 이상의 고집적반도체 소자의 제조공정에 이용되는 필드산화막 형성방법을 제 1a 내지 제 1c 도를 통해 설명하면 다음과 같다.In general, a field oxide film, which is a device isolation film, is formed to separate devices between devices in the manufacturing process of a semiconductor device. As the device is highly integrated, it secures sufficient active area due to maintaining a minimum device isolation area, decreases buzzing, and flattens. The improvement of a characteristic is calculated | required. The field oxide film formation method used in the manufacturing process of the conventional 256M DRAM or higher integrated semiconductor device is described with reference to FIGS. 1A to 1C as follows.
제 1a 내지 제 1c 도는 종래 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도로서,1A to 1C are cross-sectional views of a device for explaining a method of forming a field oxide film of a conventional semiconductor device.
제 1a 도는 실리콘기판(1)상에 패드산화막(2), 폴리실리콘층(3) 및 제 1 질화막(4)을 순차적으로 형성하여 소자분리층(Isolation Layer;5)을 형성한 후 소자분리마스크를 이용하여 상기 소자분리층(5)을 패터닝하고 전체면에 제 2 질화막(6)을 형성시킨 상태의 단면도이다.After forming a pad oxide film 2, a polysilicon layer 3, and a first nitride film 4 on the silicon substrate 1 in order to form an isolation layer 5, a device isolation mask is formed. Is a cross-sectional view of the device isolation layer 5 patterned by using and the second nitride film 6 formed on the entire surface.
제 1b 도는 상기 제 2 질화막(6)을 스페이서 식각하여 패터닝된 상기 소자분리층(5)의 측벽에 질화막스페이서(6A)를 형성시키고 노출된 실리콘기판(1)을 리세스(Recess) 구조가 되도록 소정깊이 식각한 상태의 단면도이다.In FIG. 1B, the nitride layer spacer 6A is formed on the sidewall of the device isolation layer 5 by spacer etching the second nitride layer 6, and the exposed silicon substrate 1 is recessed. It is sectional drawing of the state which etched predetermined depth.
제 1c 도는 산화공정을 실시하여 필드산화막(7)을 형성시킨 상태의 단면도인데, 상기 질화막스페이서(6A) 형성을 위한 제 2 질화막(6) 식각시하부의 제 1 질화막(4) 두께를 조절하기가 어렵다. 또한 필드산화막 형성전 최종질화막의 두께보다 두꺼운 질화막이 증착되야 하기 때문에 실리콘기판으로 가해지는 스트레스가 심하여 결함이 생성되고, 이로 인해 게이트산화막의 특성이 열화되며 접합누설(Junction leakage) 전류 특성이 저하된다.FIG. 1C is a cross-sectional view of a field oxide film 7 formed by performing an oxidation process, and adjusting the thickness of the first nitride film 4 under the etching process of the second nitride film 6 for forming the nitride film spacer 6A. Is difficult. In addition, since a nitride film thicker than the thickness of the final nitride film must be deposited before the field oxide film is formed, defects are generated due to the stress applied to the silicon substrate. .
따라서 본 발명은 질화막 상부에 층덮힘특성이 좋지 않은 저온산화막(LTO막)을 형성한 후 블랜켓식각하여 실리콘기판을 리세스구조가 되도록 하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 필드산화막 형성방법을 제공하는데 그 목적이 있다.Therefore, the present invention forms a field oxide film of a semiconductor device that can solve the above-mentioned disadvantages by forming a low temperature oxide film (LTO film) having a poor layer covering property on the nitride film and then etching the blanket to form a recess structure of the silicon substrate. The purpose is to provide a method.
상기한 목적을 달성하기 위한 본 발명은 실리콘기판상에 패드산화막, 버퍼폴리실리콘층 및 제 1 질화막을 순차적으로 형성시킨 후 소자분리마스크를 이용하여 필드영역의 제 1 질화막 및 버퍼폴리실리콘층을 순차적으로 식각하는 단계와, 상기 단계로부터 전체면에 제 2 질화막을 얇게 형성하고 그 상부에 저온산화막을 형성시키는 단계와, 상기 단계로부터 블랜켓식각을 실시하여 실리콘기판을 리세스구조로 식각한 후 잔류된 저온산화막을 제거하는 단계와, 상기 단계로부터 산화공정을 실시하여 필드영역에 필드산화막을 형성시키는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention sequentially forms a pad oxide film, a buffer polysilicon layer, and a first nitride film on a silicon substrate, and then sequentially forms the first nitride film and the buffer polysilicon layer in a field region using an element isolation mask. Etching, forming a thin second nitride film on the entire surface from the step, and forming a low temperature oxide film on the upper surface, and performing a blanket etching from the step to etch the silicon substrate into a recess structure. Removing the low temperature oxide film, and forming a field oxide film in the field region by performing an oxidation process from the step.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 2a 내지 제 2g 도는 본 발명에 따른 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도로서,2A to 2G are cross-sectional views of devices for explaining a method of forming a field oxide film of a semiconductor device according to the present invention.
제 2a 도는 실리콘기판(1)상에 패드산화막(2), 버퍼폴리실리콘층(13) 및 제 1 질화막(14)을 순차적으로 형성한 상태의 단면도이며, 제 2b 도는 소자분리마스크를 이용하여 필드영역의 제 1 질화막(14) 및 버퍼폴리실리콘층(13)을 순차적으로 식각한 상태의 단면도이다.FIG. 2A is a cross-sectional view of a pad oxide film 2, a buffer polysilicon layer 13, and a first nitride film 14 sequentially formed on a silicon substrate 1, and FIG. 2B is a field using a device isolation mask. It is sectional drawing of the state which etched the 1st nitride film 14 and the buffer polysilicon layer 13 of the area sequentially.
제 2c 도는 전체면에 제 2 질화막(16)을 100 내지 500Å 정도로 얇게 형성한 상태의 단면도이고, 제 2d 도는 층덮힘(Step coverage) 특성이 좋지 않은 저온산화막(LTO;15)을 형성한 상태의 단면도이다.FIG. 2C is a cross-sectional view of the second nitride film 16 formed on the entire surface as thin as about 100 to 500 kPa, and FIG. 2D is a low temperature oxide film (LTO) having a poor step coverage property. It is a cross section.
제 2e 도는 블랜켓(Blanket)식각을 실시하여 실리콘기판(1)을 리세스구조로 식각한 상태의 단면도로서, 이때 상기 형성된 저온산화막(15)에 의해 상기 제 2 질화막(16)의 손실이 방지된다.FIG. 2E is a cross-sectional view of a silicon substrate 1 having a recess structure by performing a blanket etching to prevent the loss of the second nitride film 16 by the formed low temperature oxide film 15. do.
제 2f 도는 BOE 용액에 디핑(Diping)하여 잔류된 저온산화막(15)을 제거한 상태의 단면도이다.FIG. 2F is a cross-sectional view of the low temperature oxide film 15 removed by dipping in a BOE solution.
제 2g 도는 산화공정을 실시하여 필드영역에 필드산화막(17)을 형성시킨 상태의 단면도로서, 버즈빅이 감소되고 평탄화가 향상된 상태가 도시된다.FIG. 2G is a cross-sectional view of a state in which a field oxide film 17 is formed in a field region by performing an oxidation process, in which a state in which buzzing is reduced and planarization is improved.
상술한 바와 같이 본 발명에 의하여 층덮힘 특성이 좋지 않은 저온산화막을 이용하므로 필요 이상의 질화막증착으로 인한 스트레스를 감소시킬 수 있으며, 이에 따라 실리콘기판에 결함의 생성이 방지되어 게이트산화막의 특성 및 접합누설전류 특성이 향상될 수 있다. 또한 버즈빅이 거의 발생되지 않아 충분한 활성영역을 확보할 수 있으며 평탄화가 향상될 수 있는 탁월한 효과가 있다.As described above, since the low temperature oxide film having poor layer covering properties is used according to the present invention, stress due to more than necessary nitride film deposition can be reduced, thereby preventing the generation of defects in the silicon substrate, thereby preventing the formation of defects in the gate oxide film and the junction leakage. Current characteristics can be improved. In addition, since hardly any buzz is generated, sufficient active area can be secured and planarization can be improved.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940038573A KR0139267B1 (en) | 1994-12-29 | 1994-12-29 | Forming method of field oxide in a semicondcutor device |
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| KR1019940038573A KR0139267B1 (en) | 1994-12-29 | 1994-12-29 | Forming method of field oxide in a semicondcutor device |
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| Publication Number | Publication Date |
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| KR960026577A KR960026577A (en) | 1996-07-22 |
| KR0139267B1 true KR0139267B1 (en) | 1998-06-01 |
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| KR1019940038573A KR0139267B1 (en) | 1994-12-29 | 1994-12-29 | Forming method of field oxide in a semicondcutor device |
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| KR100439107B1 (en) * | 1997-12-29 | 2004-07-16 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device to prevent leakage current |
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1994
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| KR960026577A (en) | 1996-07-22 |
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