KR0121102B1 - Constant voltage device - Google Patents

Constant voltage device

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Publication number
KR0121102B1
KR0121102B1 KR1019950002656A KR19950002656A KR0121102B1 KR 0121102 B1 KR0121102 B1 KR 0121102B1 KR 1019950002656 A KR1019950002656 A KR 1019950002656A KR 19950002656 A KR19950002656 A KR 19950002656A KR 0121102 B1 KR0121102 B1 KR 0121102B1
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South Korea
Prior art keywords
nmos transistor
source
drain
gate
transistor
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KR1019950002656A
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Korean (ko)
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KR960032132A (en
Inventor
김주한
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문정환
엘지반도체주식회사
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Priority to KR1019950002656A priority Critical patent/KR0121102B1/en
Publication of KR960032132A publication Critical patent/KR960032132A/en
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Publication of KR0121102B1 publication Critical patent/KR0121102B1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

A supply voltage is applied to the drains of the first and second PMOS transistors. The gate and the source of the PMOS transistor are connected to the gate of the first PMOS transistor. The source of the PMOS transistor is connected to the drain of the second NMOS transistor. The gate and the drain of the first NMOS transistor are commonly connected to the gate of the second NMOS transistor and the source of the first PMOS transistor. The drain and the gate of the fourth NMOS transistor whose source are commonly connected to the source of the second NMOS transistor are connected to the second resistor. The drain and the gate of the third NMOS transistor whose source is connected to the source of the first NMOS transistor are commonly connected to the first resistor. The constant voltage is output from the drain of the first NMOS transistor. Thus, the constant voltage is not affected by the variation of the temperature and the supply voltage.

Description

정전압장치Constant voltage device

제1도는 종래 정전압장치의 회로도.1 is a circuit diagram of a conventional constant voltage device.

제2도는 종래 다른 정전압장치의 회로도.2 is a circuit diagram of another conventional constant voltage device.

제3도는 본 발명 일실시예에 따른 정전압장치의 회로도.3 is a circuit diagram of a constant voltage device according to an embodiment of the present invention.

제4도는 본 발명 다른 일실시예에 따른 정전압장치의 회로도.4 is a circuit diagram of a constant voltage device according to another embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

MN1 : 제1엔모스트랜지스터, MN2 : 제2엔모스트랜지스터,MN1: 1st NMOS transistor, MN2: 2nd NMOS transistor,

MN3 : 제3엔모스트랜지스터, MN4 : 제4엔모스트랜지스터,MN3: 3rd NMOS transistor, MN4: 4th NMOS transistor,

MP1 : 제1피모스트랜지스터, MP2 : 제2피모스트랜지스터,MP1: first PMOS transistor, MP2: second PMOS transistor,

MP3 : 제3피모스트랜지스터, MP4 : 제4피모스트랜지스터,MP3: 3rd PMOS transistor, MP4: 4th PMOS transistor,

본 발명은 정전압장치에 관한 것으로, 특히 캐스코드전류원(cascode current source)을 이용하여 전원전압의 변동이나 온도변화에 영항을 받지 않고 안정된 정전압을 발생할 수 있는 정전압장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage device, and more particularly, to a constant voltage device capable of generating a stable constant voltage without being affected by fluctuations in power supply voltage or temperature change by using a cascode current source.

제1도는 '캐스코드전류원'이라 불리우는 종래 정전압장치의 회로도로, 이에 나타낸 바와 같이, 종래 정전압장치는, 드레인에 전원전압(Vcc)이 인가된 제2피모스트랜지스터(MP2)의 게이트 및 소오스에, 드레인에 전원전압(Vcc)이 인가된 제1피모스트랜지스터(MP1)의 게이트가 접속되고; 상기 제2피모스트랜지스터(MP2)의 소오스에 제2엔모스트랜지스터(MN2)의 드레인이 접속되며; 이 제2엔모스트랜지스터(MN2)의게이트에, 소오스가 접지(ground)되고 드레인이 상기 제1피모스트랜지스터(MP1)의 소오스에 접속된 제1엔모스트랜지스터(MN1)의 게이트와 드레인이 공통접속되고; 상기 제2엔모스트랜지스터(MN2)의 소오스에, 일측이 접지된 저항(R)이 접속되어서; 상기 제1엔모스트랜지스터(MN1)의 상기 드레인에서, 즉 출력단자(OUT)에서, 정전압이 출력되도록 되어 있다.FIG. 1 is a circuit diagram of a conventional constant voltage device called a 'cascode current source'. As shown in the drawing, the conventional constant voltage device is applied to a gate and a source of a second PMOS transistor MP2 to which a power supply voltage Vcc is applied to a drain. A gate of the first PMOS transistor MP1 to which the power supply voltage Vcc is applied to the drain is connected; A drain of the second NMOS transistor MN2 is connected to the source of the second PMOS transistor MP2; The gate and the drain of the first NMOS transistor MN1 having a source grounded and a drain connected to the source of the first PMOS transistor MP1 are common to the gate of the second NMOS transistor MN2. Connected; A resistor R having one side grounded is connected to a source of the second NMOS transistor MN2; The constant voltage is output from the drain of the first NMOS transistor MN1, that is, from the output terminal OUT.

이러한 회로도의 종래 정전압장치에서, 두 트랜지스터, 즉 상기 제1피모스트랜지스터(MP1)과 제2피모스트랜지스터(MP2)의 채널폭(W)과 채널길이(L)의 비율은 동일하다.In the conventional constant voltage device of this circuit diagram, the ratio of the channel width W and the channel length L of the two transistors, that is, the first PMOS transistor MP1 and the second PMOS transistor MP2, is the same.

따라서, 포화영역에서 상기 제1피모스트랜지스터(MP1)와 제2피모스트랜지스터(MP2)에 흐르는 두 전류(I)도 동일해져서 다음의 관계식(1)이 성립한다.Therefore, the two currents I flowing through the first PMOS transistor MP1 and the second PMOS transistor MP2 in the saturation region are also the same, and the following relation (1) is established.

VGS2+ IR = VGS1……………………………………………… (1)V GS2 + IR = V GS1 ... … … … … … … … … … … … … … … … … … (One)

단, VGS1는 제1엔모스트랜지스터(MN1)의 게이트-소오스 전압,However, V GS1 is a gate-source voltage of the first NMOS transistor MN1,

VGS2는 제2엔모스트랜지스터(MN2)의 게이트-소오스 전압.V GS2 is the gate-source voltage of the second NMOS transistor MN2.

따라서, 위의 전류(I)는,Therefore, the above current I is

단,μN은 엔모스트랜지스터의 이동도,Where μ N is the mobility of the NMOS transistor,

Cox는 게이트의 용량, (W/L)1(W/L)2 C ox is the gate capacity, (W / L) 1 (W / L) 2

또는,or,

로 나타내진다.It is represented by

위의 식(2)(3)으로부터 알 수 있는 바와 같이, 전류(I)는 전원전압(Vcc)에 무관하므로 출력단자(OUT)에서 출력되는 정전압은 전원전압(Vcc)의 변동에 영향을 받지 않는 안정된 정전압이 된다.As can be seen from equation (2) and (3) above, since the current I is independent of the power supply voltage Vcc, the constant voltage output from the output terminal OUT is not affected by the fluctuation of the power supply voltage Vcc. Does not become a stable constant voltage.

제1도에서 제2엔모스트랜지스터(MN2)와 접지사이에 접속되어 있는 저항(R)은 전류조절용이다.In FIG. 1, the resistor R connected between the second NMOS transistor MN2 and the ground is for current regulation.

제2도는 종래의 다른 정전압장치의 회로도로, 제1엔모스트랜지스터(MN1)는 바이어스부(101)로부터 바이어스전압을 공급받아 동작하고, 이처럼 동작하는 그 제1엔모스트랜지스터(MN1)의 드레인에 게이트가 접속된 제2엔모스트랜지스터(MN2)에 흐르는 전류를, 정전압이 얻어질 수 있도록, 전류제한부(102)에서 적절히 제한하며, 그 제2엔모스트랜지스터(MN2)의 소오스에서, 즉 출력단자(OUT)에서, 정전압이 출력되도록 되어있다.2 is a circuit diagram of another conventional constant voltage device, in which the first NMOS transistor MN1 operates by receiving a bias voltage from the bias unit 101, and operates in the drain of the first NMOS transistor MN1 operating as described above. The current flowing through the second NMOS transistor MN2 to which the gate is connected is appropriately limited by the current limiting unit 102 so that a constant voltage can be obtained, and that is, at the source of the second NMOS transistor MN2, that is, the output. At the terminal OUT, a constant voltage is output.

특히, 상기 바이어스부(101)는, 드레인에 전원전압(Vcc) 이 인가된 제 1피모스트랜지스터(MP1)의 게이트와 소오스가 접속되고, 드레인에 전원전압(Vcc)이 인가된 제2피모스트랜지스터(MP2)의 게이트가 상기 제1피모스트랜지스터(MP1)의 게이트에 접속되며, 이 제1,제 2 피모스트랜지스터(MP1)(MP2)의 게이트에 드레인이 접속된 제3엔모스트랜지스터(MN3)의 게이트와 소오스 사이에 다이오드(Dl)가 접속되고, 이 제3엔모스트랜지스터(MN3)의 드레인에 제4엔모스트랜지스터(MN3)의 드래인이 접속되고 그 제3,제4엔모스트랜지스터(MN3)(MN4)의 소오스가 공통접지되어 있다.In particular, the bias unit 101 is connected to a gate and a source of the first PMOS transistor MP1 to which the power supply voltage Vcc is applied to the drain, and the second PMOS to which the power supply voltage Vcc is applied to the drain. A third NMOS transistor having a gate connected to the gate of the first PMOS transistor MP1 and having a drain connected to the gate of the first and second PMOS transistors MP1 and MP2. The diode Dl is connected between the gate of the MN3 and the source, and the drain of the fourth NMOS transistor MN3 is connected to the drain of the third NMOS transistor MN3, and the third and fourth NMOS The sources of the transistors MN3 and MN4 are common grounded.

그리고 전류제한부(102)는, 상기 바이어스부(101)의 제1,제2피모스트랜지스터(MP1)(MP2)의 게이트에, 드레인에 전원전압(Vcc)이 인가된 제3피모스트랜지스터(MP3)가 접속되고; 이 제3피모스트랜지스터(MP3)의 소오스에, 소오스가 접지된 제5엔모스트랜지스터(MN5)의 드레인과 게이트가 공통접속되며; 이 제5엔모스트랜지스터(MN5)의 게이트에, 드레인이 상기 제2엔모스트랜지스터(MN2)의 소오스에 접속되고 소오스는 접지된 제6엔모스트랜지스터(MN6)의 게이트가 접속되어 있다.In addition, the current limiting unit 102 may include a third PMOS transistor having a power supply voltage Vcc applied to a drain of the first and second PMOS transistors MP1 and MP2 of the bias unit 101. MP3) is connected; A drain and a gate of the fifth NMOS transistor MN5 having the source grounded are commonly connected to the source of the third PMOS transistor MP3; The gate of the sixth NMOS transistor MN6 is connected to the gate of the fifth NMOS transistor MN5, and the drain thereof is connected to the source of the second NMOS transistor MN2.

이에 따라, 다음의 관계식(4)이 성립한다.Accordingly, the following relational expression (4) holds.

VT1=VT2+VDS6······················ (4)V T1 = V T2 + V DS6 (4)

여기서, VT1은 제1엔모스트랜지스터(MN1) 의 문턱전압이고, VT2는 제2엔모스트랜지스터(MN2)의 문턱전압이며, VDS6은 제6엔모스트랜지스터(MN6)의 드레인-소오스전압, 즉 출력단자(OUT)에서 출력되는 정전압이다.Here, V T1 is the threshold voltage of the first NMOS transistor MN1, V T2 is the threshold voltage of the second NMOS transistor MN2, and V DS6 is the drain-source voltage of the sixth NMOS transistor MN6. That is, it is a constant voltage output from the output terminal OUT.

따라서, 상기 식(4)으로부터 알 수 있는 바와 같이, 출력단자(OUT)에서 출력되는 정전압은 두 문턱전압간의 차, 즉 'VT1-VT2'가 되며, 이처럼 정전압은 두 문턱전압만으로 결정되므로 전원전압(VCC)의 변동이나 온도변화에 영향을 받지 않는다.Therefore, as can be seen from Equation (4), the constant voltage output from the output terminal (OUT) is the difference between the two threshold voltages, that is, 'V T1 -V T2 ', and thus the constant voltage is determined by only two threshold voltages It is not affected by fluctuations in power supply voltage (V CC ) or temperature changes.

그러나 종래에 제1도와 같은 정전압장치에서는 전원전압의 변동에 무관한 정전압을 발생할 수 있으나 이 정전압이 온도변화에 영향을 받는다는 문제점이 있다.However, in the conventional constant voltage device as shown in FIG. 1, a constant voltage may be generated regardless of the fluctuation of the power supply voltage. However, the constant voltage may be affected by the temperature change.

그리고, 제2도와 같은 다른 정전압장치에서는 전원전압의 변동이나 온도변화에 무관한 정전압을 발생할 수 있으나, 많은 수의 피모스, 엔모스트랜지스터를 필요로 하므로 칩내에서 차지하는 면적이 넓다는 문제점이 있다.In addition, other constant voltage devices such as FIG. 2 may generate constant voltages regardless of fluctuations in power supply voltage or temperature change, but require a large number of PMOS and NMOS transistors.

본 발명은 이 종래 문제점들이 감안되어 창안된 것이다.The present invention has been made in view of these conventional problems.

이에 따라 본 발명의 목적은, 전원전압의 변동이나 온도변화에 영향을 받지 않음은 물론 칩내에서 차지하는 면적이 좁은 정전압장치를 제공함에 있다.Accordingly, an object of the present invention is to provide a constant voltage device having a small area occupied in a chip as well as being not affected by fluctuations in power supply voltage or temperature change.

상기 목적에 따른 본 발명 정전압장치는, 캐스코드전류원에 1개의 저항과 2개의 엔모스트랜지스터(하기의 제3,제4엔모스트랜지스터)를 추가접속함으로써 구성되는데, 즉, 제3도에 나타낸 바와 같이, 드레인에 전원전압(Vcc)이 인가된 제2피모스트랜지스터(MP2)의 게이트와 소오스에, 드레인에 전원전압(Vcc)이 인가된 제1피모스트랜지스터(MP1)의 게이트가 접속되고; 상기 제2피모스트랜지스터(MP2)의 소오스에 제2엔모스트랜지스터(MN2)의 드레인이 접속되며; 이 제2엔모스트랜지스터(MN2)의 게이트와 상기 제l피모스트랜지스터(MP1)의 소오스에 제1엔모스트랜지스터(MN1)의 게이트와 드레인이 공통접속되고; 상기 제2엔모스트랜지스터(MN2)의 소오스에, 소오스가 접지된 제4엔모스트랜지스터(MN4)의 드레인과 게이트가 제2저항(R2)을 통해 공통접속되며; 상기 제1엔모스트랜지스터(MNl)의 소오스에, 소오스가 접지된 제3엔모스트랜지스터(MN3)의 드레인과 게이트과 제1저항(Rl)을 통해 공통접속되고, 상기 제1엔모스트랜지스터(MNl)의 상기 드레인에서, 즉 출력단자(OUT)에서 정전압이 출력되도록 되어 있다.The constant voltage device of the present invention according to the above object is constituted by additionally connecting one resistor and two en-mo transistors (the third and fourth en-mo transistors below) to the cascode current source, that is, as shown in FIG. Likewise, the gate and source of the second PMOS transistor MP2 to which the power supply voltage Vcc is applied to the drain are connected to the gate of the first PMOS transistor MP1 to which the power supply voltage Vcc is applied to the drain; A drain of the second NMOS transistor MN2 is connected to the source of the second PMOS transistor MP2; A gate and a drain of the first NMOS transistor MN1 are commonly connected to the gate of the second NMOS transistor MN2 and the source of the first PMOS transistor MP1; A drain and a gate of the fourth NMOS transistor MN4 having a source grounded are commonly connected to a source of the second NMOS transistor MN2 through a second resistor R2; The source of the first NMOS transistor MNl is commonly connected to a drain of the third NMOS transistor MN3 having a source grounded through the gate and the first resistor Rl, and the first NMOS transistor MNl. The constant voltage is output from the drain of the signal, i.e., from the output terminal OUT.

이때, 제4엔모스트랜지스터(MN4)의 문턱전압은 도면에 나타낸 바와 같이 'VT2'이고, 나머지 엔모스트랜지스터들, 즉 제1 내지 제3엔모스트랜지스터(MN1-MN3)의 문턱전압은 'VT1'이다(VT1≠VT2).At this time, the threshold voltage of the fourth NMOS transistor MN4 is' V T2 ', as shown in the figure, and the threshold voltages of the remaining NMOS transistors, that is, the first to third NMOS transistors MN1-MN3 are' V T1 '(V T1 ≠ V T2 ).

그리고 제1 내지 제4피모스트랜지스터(MP1-MP4)의 문턱전압은 모두 동일하며, 특히 제1피모스트랜지스터(MP1)와 제2피모스트랜지스터(MP2)의 채널폭(W)과 채널길이(L)의 비율이 동일하다. 또 제1저항(Rl)은 제2저항(R2)보다 크다.The threshold voltages of the first to fourth PMOS transistors MP1 to MP4 are the same, and in particular, the channel width W and the channel length of the first PMOS transistor MP1 and the second PMOS transistor MP2 are equal to each other. The ratio of L) is the same. The first resistor Rl is larger than the second resistor R2.

따라서, 포화영역에서 상기 제l피모스트랜지스터(MPl)와 제2피모스트랜지스터(MP2)에 흐르는 두 전류(I)도 동일해져서 다음의 관계식(5)이 성립한다.Therefore, the two currents I flowing through the first PMO transistor MPl and the second PMO transistor MP2 in the saturation region are also equal, and the following relation (5) is established.

VGS1+ IR1+ VT1= VGS2+IR2 + VT2···············(5)V GS1 + IR1 + V T1 = V GS2 + IR2 + V T2 (...) (5)

그리고 앞서 언급한 바와 같이 제1 내지 제3엔모스트랜지스터(MN1-MN3)의 문턱전압은 'VT1'으로 모두 동일하므로 상기 식(5)에서 'VGS1=VGS2'이 성립하며, 따라서 전류(I)는,As mentioned above, since the threshold voltages of the first to third NMOS transistors MN1 to MN3 are the same as 'V T1 ', 'V GS1 = V GS2 ' is established in Equation (5), and thus the current (I) is

………………………………………………………………………(6) … … … … … … … … … … … … … … … … … … … … … … … … … … … (6)

이다.to be.

이 식(6)으로부터 알 수 있는 바와 같이, 제1피모스트랜지스터(MP1)와 제2피모스트랜지스터(MP2)에 각각 흐르는 전류(I)는 문턱전압의 차(VT2-VT1)에 따라 결정되므로 출력단자(OUT)에서 얻어지는 정전압은 전원전압(Vcc)의 변동이나 온도변화에 영향을 받지 않는다. 이때, 제1,제2저항(Rl)(R2)은 온도변화에 둔감한 물질로 만든 저항이다.As can be seen from this equation (6), the current I flowing through the first PMOS transistor MP1 and the second PMOS transistor MP2 respectively depends on the threshold voltage difference V T2 -V T1 . As a result, the constant voltage obtained at the output terminal OUT is not affected by a change in the power supply voltage Vcc or a temperature change. In this case, the first and second resistors Rl and R2 are resistors made of a material insensitive to temperature change.

특히, 제3도에서 제3, 제4엔모스트랜지스터(MN3)(MN4)에 바이어스전압을 인가하기 위한 바이어스회로를 필요로 하지 않으므로 요구되는 엔모스, 피모스트랜지스터의 개수가 적어 칩내에서 차지하는 면적이 좁다.In particular, in FIG. 3, since the bias circuit for applying the bias voltage to the third and fourth NMOS transistors MN3 and MN4 is not required, the number of NMOS and PMOS transistors required is small and occupies an area of the chip. Is narrow.

제4도는 본 발명에 따른 제2구체적 실시예로, 제3도에서 제1, 제2엔모스트랜지스터(MNl)(MN2)와 제1, 제2저항(Rl)(R2)을 없에고, 제4도에 나타낸 바와 같이, 전원전압(Vcc)과, 제1, 제2피모스트랜지스터(MP1)(MP2)와의 사이에 제3, 제4피모스트랜지스터(MP3)(MP4)와 제1, 제2저항(Rl)(R2)을 접속한 것이다.FIG. 4 is a second specific embodiment according to the present invention. In FIG. 3, the first and second NMOS transistors MNl (MN2) and the first and second resistors Rl (R2) are omitted. As shown in the figure, between the power supply voltage Vcc and the first and second PMOS transistors MP1 and MP2, the third and fourth PMOS transistors MP3 and MP4 and the first and second pulses. The resistors Rl and R2 are connected.

이상에서 상세히 설명한 바와 같이, 본 발명은 캐스코드전류원에 제1저항과, 문턱전압이 서로 다른 두 엔모스트랜지스터, 즉 제3, 제4엔모스트랜지스터를 추가 접속함으로써 출력단자에서 출력되는 정전압이 전원전압의 변동이나 온도변화에 영향을 받지 않고 안정된 정전압을 발생할 수 있으며, 그리고 요구되는 트랜지스터의 개수가 적어져 칩내에서 차지하는 면적이 크게 줄어든다는 효과를 갖는다.As described in detail above, in the present invention, the constant voltage outputted from the output terminal is obtained by additionally connecting two NMOS transistors, that is, third and fourth NMOS transistors having different threshold voltages, to the cascode current source. A stable constant voltage can be generated without being affected by voltage fluctuations or temperature changes, and the number of transistors required is reduced, thereby reducing the area occupied in a chip.

Claims (3)

드레인에 전원전압이 인가된 제2피모스트랜지스터의 게이트와 소오스에, 드레인에 전원전압이 인가된 제1피모스트랜지스터의 게이트가 접속되고; 상기 제2피모스트랜지스터의 소오스에 제2엔모스트랜지스터의 드레인이 접속되며; 상기 제2엔모스트랜지스터의 게이트와 상기 제1피모스트랜지스터의 소오스에 제1엔모스트랜지스터의 게이트와 드레인이 공통접속되고; 상기 제2엔모스트랜지스터의 소오스에, 소오스가 접지된 제4엔모스트랜지스터의 드레인과 게이트가 제2저항을 통해 공통접속되며; 상기 제1엔모스트랜지스터의 소오스에, 소오스가 접지된 제3엔모스트랜지스터의 드레인과 게이트가 제1저항을 통해 공통접속되고; 상기 제1엔모스트랜지스터의 상기 드레인에서 정전압이 출력되도록 된 것을 특징으로 하는 정전압장치.A gate of the first PMOS transistor to which the power voltage is applied to the drain is connected to the gate and the source of the second PMOS transistor to which the power voltage is applied to the drain; A drain of the second NMOS transistor is connected to a source of the second PMOS transistor; A gate and a drain of the first NMOS transistor are commonly connected to the gate of the second NMOS transistor and the source of the first PMOS transistor; A drain and a gate of a fourth NMOS transistor having a source grounded are commonly connected to a source of the second NMOS transistor through a second resistor; A drain and a gate of the third NMOS transistor of which the source is grounded are commonly connected to a source of the first NMOS transistor through a first resistor; And a constant voltage is output from the drain of the first NMOS transistor. 제1항에 있어서, 제1 내지 제3엔모스트랜지스터의 문턱전압은 동일하고, 상기 제l저항은 상기 제2저항보다 큰 것을 특징으로 하는 정전압장치.The constant voltage device of claim 1, wherein the threshold voltages of the first to third NMOS transistors are the same, and the first resistance is greater than the second resistance. 제l항에 있어서, 제1, 제2엔모스트랜지스터와 제1, 제2저항을 없애고, 상기 전원전압과 상기 제1, 제2피모스트랜지스터와의 사이에 제3, 제4피모스트랜지스터와 상기 제1, 제2저항을 접속한 것을 특징으로하는 정전압장치.The method of claim 1, wherein the first and second NMOS transistors and the first and second resistors are removed, and the third and fourth PMOS transistors are disposed between the power supply voltage and the first and second PMOS transistors. And said first and second resistors are connected.
KR1019950002656A 1995-02-14 1995-02-14 Constant voltage device KR0121102B1 (en)

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