KR0114433Y1 - Video signal converting circuit - Google Patents
Video signal converting circuit Download PDFInfo
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- KR0114433Y1 KR0114433Y1 KR2019910019831U KR910019831U KR0114433Y1 KR 0114433 Y1 KR0114433 Y1 KR 0114433Y1 KR 2019910019831 U KR2019910019831 U KR 2019910019831U KR 910019831 U KR910019831 U KR 910019831U KR 0114433 Y1 KR0114433 Y1 KR 0114433Y1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/77—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
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- Multimedia (AREA)
- Signal Processing (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
본 고안은 영상신호 변환회로에 관한 것으로, 특히 디지탈 휘도신호와 디지탈 색차신호를 디지탈 색신호로 변환할 수 있는 영상신호 변환회로에 관한 것이다. 본 고안에 의한 영상신호 변환기는 감산 및 곱셈 처리는 ROM에서 행하고 가산처리는 애더(Adder)에서 행함으로써, 디지탈 휘도신호와 색차신호를 실시간으로 색신호로 변환한다.The present invention relates to a video signal conversion circuit, and more particularly, to a video signal conversion circuit capable of converting a digital luminance signal and a digital color difference signal into a digital color signal. In the video signal converter according to the present invention, the subtraction and multiplication processing is performed in the ROM, and the addition processing is performed in the Adder, thereby converting the digital luminance signal and the color difference signal into color signals in real time.
Description
제1도는 본 고안에 의한 영상신호 변환회로의 블럭도.1 is a block diagram of a video signal conversion circuit according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 3, 5, 6 : 제1 내지 제4 ROM 2, 4, 7, 9 : 제1 내지 제4 애더1, 3, 5, 6: 1st to 4th ROM 2, 4, 7, 9: 1st to 4th Adder
8 : 2의 보수 변환기8: 2's complement converter
본 고안은 영상신호 변환회로에 관한 것으로, 특히 디지탈 휘도신호와 디지탈 색차신호를 디지탈 색신호로 변환할 수 있는 영상신호 변환회로에 관한 것이다. 국제 무선통신자문위원회(CCIR)에서 제정한 권고안 No.6에는 영상신호인 디지탈 휘도신호와 디지탈 색차신호를 디지탈 색신호로 변환하는 회로에 관해서 규정되어 있다. 일반적으로, R(적색), G(녹색) 및 B(청색)의 디지탈 색신호는 디지탈 휘도신호(Y)와 디지탈 색차신호(Cb,Cr)를 변환시켜서 발생할 수 있다. 종래에는 디지탈 휘도신호(Y)와 디지탈 색차신호(Cb,Cr)를 디지탈 색신호(R,G,B)로 변환할 경우, 곱셈처리를 멀티플렉서 등으로 행했기 때문에 디지탈 색신호(R,G,B)를 실시간으로 발생할 수 없는 문제점이 있었다. 본 고안은 상술한 바와 같은 문제점을 감안하여 안출한 것으로, 디지탈 휘도신호(Y)와 디지탈 색차신호(Cb,Cr)를 실시간으로 디지탈 색신호(R,G,B)로 변환할 수 있는 영상신호 변환회로를 제공하는데 목적이 있다. 상기와 같은 목적을 달성하기 위한 본 고안의 특징은, 디지탈 휘도신호(Y)와 디지탈 색차신호(Cb,Cr)로 변환하는 영상신호 변환회로에 있어서, 상기 디지탈 색차신호(Cr)를 인가받아 소정의 감산 및 곱셈 연산을 행하는 제1ROM과, 제1 ROM(1)으로부터 인가되는 연산데이타와 상기 휘도신호(Y)를 가산하여 디지탈 색신호(R)를 출력하는 제1 애더(2)와, 상기 디지탈 색차신호(Cb)를 인가받아 소정의 감산 및 곱셈 연산을 행하는 제2 ROM(3)과, 상기 제2 ROM(3)으로부터 인가되는 연산데이터와 상기 휘도신호(Y)를 가산하여 디지탈 색신호(B)를 출력하는 제2 애더(4)와, 상기 디지탈 색차신호(Cb)를 인가받아 소정의 감산 및 곱셈을 행하는 제3 ROM(5)과, 상기 디지탈 색차신호(Cr)를 인가받아 소정의 감산 및 곱셈을 행하는 제4 ROM(6)과, 상기 제3 및 제4 ROM(5),(6)으로부터 인가되는 연산데이터를 가산하는데 제3 애더(7)와 상기 제3 애더(7)로부터 인가되는 연산데이터에 대한 2의 보수를 구하는 2의 보수 변환키(8)와, 상기 2의 보수 변환키(8)로부터 인가받은 2의 보수와 상기 휘도신호(Y)를 가산하여 디지탈 색신호(G)를 출력하는 제4 애더(9)를 구비하는데 있다. 이하 첨부된 도면을 참조하여 본 고안을 상세히 설명한다. 디지탈 휘도신호(Y)와 디지탈 색차신호(Cb,Cr)를 디지탈 색신호(R,G,B)로 변환하는 식은 다음과 같다. R = Y+1.730(Cr-128) (A) G =Y-{0.698(Cr-128)+0.336(Cb-128)}(B) B=Y+1.370(Cb-128)(C)(여기서, Y,Cb,Cr은 각각 8비트 데이터로서 그 값의 범위는 Y는 16~235, Cb 및 Cr은 16~240이다.) 위의 (A),(B) 및 (C)식을 연산처리함으로써 디지탈 휘도신호(Y)와 디지탈 색차신호(Cb,Cr)를 디지탈 색신호(R,G,B)로 변환할 수 있다. 제1도는 본 고안에 의한 영상신호 변환회로의 블럭도이다. 도면에서 알 수 있는 바와 같이, 영상신호 변환회로는 복수의 ROM, 복수의 애더(Adder) 및 2의 보수 변환기로 연결구성된다. 제1, 2, 3 및 4 ROM(1,3,5,6)에서는 감산 및 곱셈을 행하고, 제1, 2, 3 및 4애더(2,4,7,9)에서는 가산을 행하고, 2의 보수변환기(8)에서는 감산을 위한 2의 보수를 구한다. 휘도신호(Y)와 색차신호(Cr)로부터 색신호(R)를 발생할 경우, 제1 ROM(1)은 입력된 색차신호(Cr)를 이용해 (A)식의 {1.370(Cr-128)}에 대한 연산을 행하여 그 결과를 제1 애더(2)측으로 출력하고, 제1 애더(2)는 입력된 휘도신호(Y)와 제1 ROM(1)으로 부터의 결과를 가산하여 색신호(R)를 출력한다. 휘도신호(Y)와 색차신호(Cb)로부터 색신호(B)를 발생할 경우, 제2 ROM(3) 입력된 색차신호(Cb)를 이용해 (C)식의 {1.730(Cb-128)}에 대한 연산을 행하여 그 결과를 제2애더(4)측으로 출력하고, 제2 애더(4)는 입력된 휘도신호(Y)와 제2 ROM(3)으로부터의 결과를 가산하여 색신호(B)를 출력한다.The present invention relates to a video signal conversion circuit, and more particularly, to a video signal conversion circuit capable of converting a digital luminance signal and a digital color difference signal into a digital color signal. Recommendation No. 6 established by the International Radiocommunication Advisory Committee (CCIR) stipulates a circuit for converting a digital luminance signal and a digital color difference signal, which are video signals, into a digital color signal. In general, digital color signals of R (red), G (green), and B (blue) can be generated by converting the digital luminance signal Y and the digital color difference signals Cb and Cr. Conventionally, when converting the digital luminance signal (Y) and the digital color difference signals (Cb, Cr) into digital color signals (R, G, B), the multiplication process is performed by a multiplexer or the like, and thus the digital color signals (R, G, B). There was a problem that cannot occur in real time. The present invention has been devised in view of the above-described problems, and is capable of converting a digital luminance signal (Y) and a digital color difference signal (Cb, Cr) into digital color signals (R, G, B) in real time. The purpose is to provide a circuit. A feature of the present invention for achieving the above object is, in the image signal conversion circuit for converting the digital luminance signal (Y) and the digital color difference signal (Cb, Cr), the digital color difference signal (Cr) is applied to a predetermined A first ROM for performing a subtraction and multiplication operation, a first adder 2 for adding a calculation data applied from the first ROM 1 and the luminance signal Y to output a digital color signal R, and the digital. The second ROM 3 which receives the color difference signal Cb and performs a predetermined subtraction and multiplication operation, the operation data applied from the second ROM 3 and the luminance signal Y are added to the digital color signal B. FIG. The second adder 4 for outputting the < RTI ID = 0.0 >), < / RTI > third ROM 5 for receiving a predetermined subtraction and multiplication by receiving the digital color difference signal Cb, and a predetermined subtraction after receiving the digital color difference signal Cr. And a fourth ROM 6 for multiplication, and a link applied from the third and fourth ROMs 5 and 6; A two's complement conversion key 8 for obtaining a two's complement for the operation data applied from the third adder 7 and the third adder 7, and the two's complement conversion key 8 for adding the acid data. And a fourth adder 9 for outputting the digital color signal G by adding the two's complement and the luminance signal Y. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. The equation for converting the digital luminance signal Y and the digital color difference signals Cb and Cr into the digital color signals R, G and B is as follows. R = Y + 1.730 (Cr-128) (A) G = Y- {0.698 (Cr-128) +0.336 (Cb-128)} (B) B = Y + 1.370 (Cb-128) (C), where , Y, Cb, and Cr are 8-bit data, respectively, and the range of values is 16 to 235 for Y, and 16 to 240 for Cb and Cr.) The above formulas (A), (B) and (C) Thus, the digital luminance signal Y and the digital color difference signals Cb and Cr can be converted into the digital color signals R, G and B. 1 is a block diagram of a video signal conversion circuit according to the present invention. As can be seen from the figure, the video signal conversion circuit is composed of a plurality of ROMs, a plurality of adders, and a two's complement converter. Subtraction and multiplication are performed in the first, second, third and fourth ROMs (1, 3, 5, 6), and addition is performed in the first, second, third and fourth adders (2, 4, 7, and 9). The complement converter 8 finds a two's complement for subtraction. When the color signal R is generated from the luminance signal Y and the color difference signal Cr, the first ROM 1 uses the input color difference signal Cr in accordance with {1.370 (Cr-128)} of the formula (A). And the result is output to the first adder 2 side, and the first adder 2 adds the input luminance signal Y and the result from the first ROM 1 to add the color signal R. FIG. Output When the color signal B is generated from the luminance signal Y and the color difference signal Cb, the {1.730 (Cb-128)} expression (C) is used by using the color difference signal Cb inputted in the second ROM 3. The calculation is performed to output the result to the second adder 4 side, and the second adder 4 adds the input luminance signal Y and the result from the second ROM 3 to output the color signal B. FIG. .
휘도신호(Y)와 색차신호(Cb,Cr)로부터 색신호(G)를 발생할 경우, 제3 ROM (5) 입력된 색차신호(Cb)를 이용해 (B)식의 {0.366×(Cb-128)}에 대한 연산을 행하여 그 결과를 제3 애더(7)측으로 출력하고, 제4 ROM(6)은 입력된 색차신호(Cr)를 이용해 (B)식의 {0.698×(Cr-128)}에 대한 연산을 행하여 그 결과를 제3 애더(7)측으로 출력한다. 제3 애더(7)는 제3 및 제4 ROM(5),(6)으로부터의 연산 결과를 가산하여 그 결과를 2의 보수 변환기(8)측으로 출력한다. 2의 보수 변환기(8)는 제3 애더(7)로부터의 연산결과에 대한 보수를 구하여 제4 애더(9)측으로 출력하고, 제4 애더(9)는 입력된 휘도신호(Y)와 2의 보수 변환기(8)로부터의 보수를 가산하여 색신호(G)를 출력한다. 이상 설명한 바와 같이, 본 고안은 감산 및 곱셈 처리는 ROM에서 행하고 가산처리는 애더(Adder)에서 행함으로써 디지탈 휘도신호와 색차신호를 디지탈 색신호로 변환하므로, 멀티플렉서에 의한 곱셈처리를 행하지 않아도 되어 색신호를 실시간으로 발생하게 된다.When the color signal G is generated from the luminance signal Y and the color difference signals Cb and Cr, {0.366 × (Cb-128) of the formula (B) using the color difference signal Cb input to the third ROM 5. } And the result is output to the third adder 7 side, and the fourth ROM 6 uses the input color difference signal Cr to the {0.698 × (Cr-128)} of the formula (B). Is performed and the result is output to the third adder 7 side. The third adder 7 adds the calculation results from the third and fourth ROMs 5 and 6 and outputs the result to the two's complement converter 8 side. The two's complement converter 8 obtains the complement of the calculation result from the third adder 7 and outputs it to the fourth adder 9, and the fourth adder 9 is inputted with the input luminance signal Y and the second. The color signal G is output by adding the complement from the complement converter 8. As described above, the present invention converts the digital luminance signal and the color difference signal into a digital color signal by performing the subtraction and multiplication process in the ROM and the add process in the Adder, so that the color signal is not required to be multiplied by the multiplexer. It occurs in real time.
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KR2019910019831U KR0114433Y1 (en) | 1991-11-19 | 1991-11-19 | Video signal converting circuit |
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KR2019910019831U KR0114433Y1 (en) | 1991-11-19 | 1991-11-19 | Video signal converting circuit |
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KR930012471U KR930012471U (en) | 1993-06-25 |
KR0114433Y1 true KR0114433Y1 (en) | 1998-04-16 |
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KR2019910019831U KR0114433Y1 (en) | 1991-11-19 | 1991-11-19 | Video signal converting circuit |
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