JPWO2022239226A1 - - Google Patents

Info

Publication number
JPWO2022239226A1
JPWO2022239226A1 JP2021559564A JP2021559564A JPWO2022239226A1 JP WO2022239226 A1 JPWO2022239226 A1 JP WO2022239226A1 JP 2021559564 A JP2021559564 A JP 2021559564A JP 2021559564 A JP2021559564 A JP 2021559564A JP WO2022239226 A1 JPWO2022239226 A1 JP WO2022239226A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021559564A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2022239226A1 publication Critical patent/JPWO2022239226A1/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2021559564A 2021-05-14 2021-05-14 Pending JPWO2022239226A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/018388 WO2022239226A1 (en) 2021-05-14 2021-05-14 Incorporated circuit, circuit quality confirmation device, and circuit quality confirmation method

Publications (1)

Publication Number Publication Date
JPWO2022239226A1 true JPWO2022239226A1 (en) 2022-11-17

Family

ID=84028933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021559564A Pending JPWO2022239226A1 (en) 2021-05-14 2021-05-14

Country Status (2)

Country Link
JP (1) JPWO2022239226A1 (en)
WO (1) WO2022239226A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0528210A (en) * 1991-07-19 1993-02-05 Nec Corp Timing verification system
JP2000194734A (en) * 1998-12-25 2000-07-14 Matsushita Electric Ind Co Ltd Back annotation method for semiconductor integrated circuit
JP2009110380A (en) * 2007-10-31 2009-05-21 Fujitsu Microelectronics Ltd Layout support program, storage medium recording the program, layout support device, and layout support method
JP2009187344A (en) * 2008-02-07 2009-08-20 Sony Corp Asynchronous logic circuit verification device, its method, and program
JP2011502316A (en) * 2007-10-30 2011-01-20 テラダイン、 インコーポレイテッド Method for testing with a reconfigurable tester
JP2013037596A (en) * 2011-08-10 2013-02-21 Renesas Electronics Corp Asynchronous interface verification device, asynchronous interface verification method and its program

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9672008B2 (en) * 2014-11-24 2017-06-06 Nvidia Corporation Pausible bisynchronous FIFO

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0528210A (en) * 1991-07-19 1993-02-05 Nec Corp Timing verification system
JP2000194734A (en) * 1998-12-25 2000-07-14 Matsushita Electric Ind Co Ltd Back annotation method for semiconductor integrated circuit
JP2011502316A (en) * 2007-10-30 2011-01-20 テラダイン、 インコーポレイテッド Method for testing with a reconfigurable tester
JP2009110380A (en) * 2007-10-31 2009-05-21 Fujitsu Microelectronics Ltd Layout support program, storage medium recording the program, layout support device, and layout support method
JP2009187344A (en) * 2008-02-07 2009-08-20 Sony Corp Asynchronous logic circuit verification device, its method, and program
JP2013037596A (en) * 2011-08-10 2013-02-21 Renesas Electronics Corp Asynchronous interface verification device, asynchronous interface verification method and its program

Also Published As

Publication number Publication date
WO2022239226A1 (en) 2022-11-17

Similar Documents

Publication Publication Date Title
BR112022024743A2 (en)
BR112022009896A2 (en)
BR102021007058A2 (en)
BR102020022030A2 (en)
BR202021022912U2 (en)
BR102021015247A2 (en)
BR102021015220A2 (en)
BR102021014056A2 (en)
BR102021014044A2 (en)
BR102021013929A2 (en)
BR112021017747A2 (en)
BR102021012571A2 (en)
BR102021012230A2 (en)
BR102021012107A2 (en)
BR102021012003A2 (en)
BR102021010467A2 (en)
BR102021009555A2 (en)
BR102021009475A2 (en)
JPWO2022239226A1 (en)
BR102021007978A2 (en)
BR202021005381U2 (en)
BR102021004425A2 (en)
BR102020022457A2 (en)
BR102020021699A2 (en)
BR102020019899A2 (en)

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20211006

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20211006

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20211006

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20211207

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220128

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20220315