JPWO2019032373A5 - - Google Patents
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- JPWO2019032373A5 JPWO2019032373A5 JP2020507575A JP2020507575A JPWO2019032373A5 JP WO2019032373 A5 JPWO2019032373 A5 JP WO2019032373A5 JP 2020507575 A JP2020507575 A JP 2020507575A JP 2020507575 A JP2020507575 A JP 2020507575A JP WO2019032373 A5 JPWO2019032373 A5 JP WO2019032373A5
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- 239000000463 material Substances 0.000 description 49
- 238000000034 method Methods 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 7
- 238000000926 separation method Methods 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N HF Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 201000011452 adrenoleukodystrophy Diseases 0.000 description 4
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- AIRCTMFFNKZQPN-UHFFFAOYSA-N AlO Inorganic materials [Al]=O AIRCTMFFNKZQPN-UHFFFAOYSA-N 0.000 description 3
- 229940091292 Alo Drugs 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N al2o3 Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- TWXTWZIUMCFMSG-UHFFFAOYSA-N nitride(3-) Chemical compound [N-3] TWXTWZIUMCFMSG-UHFFFAOYSA-N 0.000 description 2
- 229910004140 HfO Inorganic materials 0.000 description 1
- 102000014961 Protein Precursors Human genes 0.000 description 1
- 108010078762 Protein Precursors Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N Silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 150000002366 halogen compounds Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- OZAIFHULBGXAKX-UHFFFAOYSA-N precursor Substances N#CC(C)(C)N=NC(C)(C)C#N OZAIFHULBGXAKX-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Description
誘電体ブロック領域109とゲート115との間にある薄い領域として構造化される誘電体バリア110は、ゲート115から誘電体ブロック領域109を通って電荷トラップ領域105への電子のバックトンネルを防止するトンネルバリアの向上を可能にし、それによって、動作上の消去飽和を小さい正の閾値電圧(Vt)レベルまたは小さい負の閾値電圧(Vt)レベルに制限することができる。誘電体バリア110は、誘電体ブロック領域109とゲート115との間に約15オングストローム~約50オングストロームの範囲の厚さを有し得る。誘電体バリア110の材料の選択はCT構造101の製作に基づき得る。例えば、ボイド120を含むCT構造101がCT構造101の側面に対するエリアからの材料の除去によって形成されるプロセスでは、誘電体バリア110の材料は、誘電体バリア110の材料がCT構造101の側面からのこれらの材料の除去に使用される処理ケミストリ及び温度において除去を阻むように、選択されることができる。誘電体バリア110の材料は、マスクとして働き、係る除去プロセスでは誘電体ブロック領域109の除去を防止することができる。 The dielectric barrier 110, which is structured as a thin region between the dielectric block region 109 and the gate 115, prevents electron back tunneling from the gate 115 through the dielectric block region 109 to the charge trap region 105. It allows for improved tunnel barriers, thereby limiting operational erasure saturation to small positive threshold voltage ( Vt ) levels or small negative threshold voltage ( Vt ) levels. The dielectric barrier 110 may have a thickness in the range of about 15 angstroms to about 50 angstroms between the dielectric block region 109 and the gate 115. The choice of material for the dielectric barrier 110 may be based on the fabrication of the CT structure 101. For example, in a process in which the CT structure 101 containing the void 120 is formed by removing the material from the area relative to the side surface of the CT structure 101, the material of the dielectric barrier 110 is such that the material of the dielectric barrier 110 is from the side surface of the CT structure 101. Can be selected to prevent removal at the treatment chemistry and temperature used to remove these materials. The material of the dielectric barrier 110 acts as a mask and can prevent the removal of the dielectric block region 109 in such a removal process.
図4は、導電領域の上方に電荷トラップ構造を形成する例示的な方法400の実施形態の特徴のフロー図である。410において、誘電体バリアは、材料スタック内の開口部の壁上に形成される。誘電体バリアを形成することは、酸化アルミニウム、または酸化アルミニウムの誘電率よりも大きい誘電率を有する誘電体を形成することを含み得る。他の誘電体を使用し得る。誘電体バリアを形成することは、電荷トラップ構造の処理中にエッチングされる誘電体ブロック領域をマスクするための温度及びエッチングケミストリに耐えることができる材料で誘電体バリアを形成することを含み得る。 FIG. 4 is a flow diagram of the features of the embodiment of the exemplary method 400 of forming a charge trap structure above the conductive region. At 410, the dielectric barrier is formed on the wall of the opening in the material stack. Forming a dielectric barrier may include forming aluminum oxide, or a dielectric having a dielectric constant greater than that of aluminum oxide. Other dielectrics may be used. Forming a dielectric barrier may include forming the dielectric barrier with a material that can withstand the temperature and etching chemistry to mask the dielectric block regions etched during the processing of the charge trap structure.
方法400と同様または同一の方法は、開口部を材料スタック内に形成することを含み得、材料スタックは交互に並ぶ犠牲領域及び分離誘電体を有する。誘電体バリアの材料を実質的に除去することなく犠牲領域を除去するケミストリ及びプロセスを使用して、誘電体バリアに隣接する犠牲領域を除去することができる。ゲートは犠牲領域が除去されている領域内に形成されることができ、隣接ゲートは犠牲領域の別の1つが除去されている領域内に形成されることができる。誘電体バリアの材料を実質的に除去することなく、ゲートの材料を実質的に除去することなく、及び隣接ゲートの材料を実質的に除去することなく、隣接する犠牲領域の間に事前に形成した分離誘電体を除去するケミストリ及びプロセスによって、開放エリアを形成するために、ゲートと隣接ゲートとの間から材料を除去することができる。ボイドを形成するために、開放エリアの少なくとも一部に誘電体を形成することができる。 Similar or identical methods to method 400 may include forming openings in the material stack, the material stack having alternating sacrificial regions and separating dielectrics. Chemistries and processes that remove the sacrificial region without substantially removing the material of the dielectric barrier can be used to remove the sacrificial region adjacent to the dielectric barrier. A gate can be formed in the area where the sacrificial area has been removed, and an adjacent gate can be formed in the area where another one of the sacrificial areas has been removed. Preformed between adjacent sacrificial regions without substantially removing the material of the dielectric barrier, without substantially removing the material of the gate, and without substantially removing the material of the adjacent gate. The chemistry and process of removing the separated dielectric can remove material from between the gate and the adjacent gate to form an open area. Dielectrics can be formed in at least a portion of the open area to form voids.
520において、誘電体バリアの材料に接触する複数のゲートは形成され、各ゲートが開放エリアによって複数のゲートの垂直隣接ゲートから分離されるように、材料をスタックから除去し、誘電体バリアの材料の一部を露出する。誘電体バリアの材料に接触する複数のゲートを形成し、各ゲートが複数のゲートの垂直隣接ゲートから分離されるように材料を除去することは、材料のスタックが、トンネル領域、電荷トラップ領域、誘電体ブロック領域、及び誘電体バリアを形成するために、材料に隣接する交互に並ぶ犠牲領域及び分離誘電体を含む状態で、誘電体バリアの材料を実質的に除去することなく犠牲領域を除去するケミストリ及びプロセスを使用して、誘電体バリアの材料に隣接する犠牲領域を除去することと、ゲート材料を犠牲領域が除去される各領域内に形成することと、誘電体バリアの材料を実質的に除去することなく及び各領域内のゲート材料を実質的に除去することなく、隣接する犠牲領域の間に事前に形成した分離誘電体を除去するケミストリ及びプロセスによって、各ゲート間から材料を除去することと、を含み得る。ゲート材料を犠牲領域が除去される各領域内に形成することは、メモリデバイスのメモリアレイ内のアクセス線に結合されるゲート材料を形成することを含み得る。 At 520, the material is removed from the stack so that a plurality of gates in contact with the material of the dielectric barrier are formed and each gate is separated from the vertically adjacent gates of the plurality of gates by an open area, and the material of the dielectric barrier. Exposing a part of. Forming multiple gates in contact with the material of the dielectric barrier and removing the material so that each gate is separated from the vertically adjacent gates of the multiple gates is a stack of materials in the tunnel region, charge trap region, Dielectric block regions, and sacrificial regions that include alternating sacrificial regions and separate dielectrics adjacent to the material to form the dielectric barrier, without substantially removing the material of the dielectric barrier. The removal of sacrificial regions adjacent to the material of the dielectric barrier and the formation of gate material within each region where the sacrificial region is removed, and the material of the dielectric barrier. From between each gate by a chemistry and process that removes the preformed separation dielectric between adjacent sacrificial regions without substantially removing the gate material within each region. May include removing material. Forming a gate material within each region where the sacrificial region is removed may include forming a gate material that is coupled to an access line in the memory array of the memory device.
図6A~図6Nは、電子デバイス内の複数のCT構造を形成する実施形態の段階の特徴を示す断面図である。図6Aは、基板602上の導電性領域613の上方に材料スタック621を示す。材料スタック621は、導電性領域613の上方に、交互に並ぶ分離誘電体618及び犠牲領域619を含む。交互に並ぶ分離誘電体618及び犠牲領域619の数は、垂直スタック内に形成されるCT構造の数によって決定され得る。3次元メモリデバイスでは、この数は、メモリデバイスのメモリアレイの段数(例えば、段毎の分離誘電体618及び犠牲領域619の対の数)によって決定され得る。メモリデバイスのメモリアレイの3つの段に対応し得る3つの分離誘電体618及び3つの犠牲領域619は、説明しやすくするために図6Aに示される。分離誘電体618は、限定ではないが、酸化ケイ素等の酸化物を含み得、犠牲領域619は、限定ではないが、窒化ケイ素等の窒化物を含み得る。分離誘電体618及び犠牲領域619の材料の選択は、複数のCT構造を製作する際に使用される温度及びケミストリによって決定され得る。 6A-6N are cross-sectional views showing the characteristics of the stages of the embodiment forming a plurality of CT structures in an electronic device. FIG. 6A shows the material stack 621 above the conductive region 613 on the substrate 602. The material stack 621 includes alternating dielectrics 618 and sacrificial regions 619 above the conductive regions 613. The number of alternating dielectrics 618 and sacrificial regions 619 can be determined by the number of CT structures formed in the vertical stack. In a three-dimensional memory device, this number can be determined by the number of stages in the memory array of the memory device (eg, the number of pairs of separating dielectric 618 and sacrificial region 619 per stage). Three separate dielectrics 618 and three sacrificial regions 619 that can correspond to the three stages of the memory array of the memory device are shown in FIG. 6A for ease of explanation. The separation dielectric 618 may include, but is not limited to, an oxide such as silicon oxide, and the sacrificial region 619 may contain, but not limited to, a nitride such as silicon nitride. The choice of materials for the separating dielectric 618 and the sacrificial region 619 can be determined by the temperature and chemistry used in the fabrication of multiple CT structures.
図6Kは、ゲート615の材料の間の分離領域618の材料を除去した後の図6Jの構造を示す。分離領域618の段の除去は、ゲート615の材料及び誘電体バリア610の材料の選択と関連して選択されるケミストリを使用して行われる。選択のために使用される基準は、ゲート615の材料及び誘電体バリア610の材料に対して選択的であるケミストリを選択することを含み得、それにより、ケミストリは、ゲート615の材料及び誘電体バリア610の材料に実質的に影響を及ぼさない。誘電体バリア610の材料は、誘電体ブロック領域609の材料を除去することなく、分離領域618の段を除去することを可能にするマスクとして働く。分離領域618の段の除去は、フッ化水素(HF)、蒸気エッチング、または誘電体バリア610の材料が耐えることができる他のケミストリの使用を含み得、これにより、誘電体ブロック領域609の下層にある材料は、分離領域618の段の除去によって除去されない。 FIG. 6K shows the structure of FIG. 6J after removing the material in the separation region 618 between the materials in the gate 615. Removal of the stage of the separation region 618 is performed using chemistry selected in connection with the selection of the material of the gate 615 and the material of the dielectric barrier 610. The criteria used for selection may include selecting a chemistry that is selective for the material of the gate 615 and the material of the dielectric barrier 610, whereby the chemistry may include the material and dielectric of the gate 615. It has virtually no effect on the material of the barrier 610. The material of the dielectric barrier 610 acts as a mask that allows the steps of the separation region 618 to be removed without removing the material of the dielectric block region 609. Removal of the stage of separation region 618 may include hydrogen fluoride (HF), vapor etching, or the use of other chemistries that the material of the dielectric barrier 610 can withstand, thereby underlaying the dielectric block region 609. The material at is not removed by the removal of the steps of the separation region 618.
AlOxまたは他の高誘電率(高k(high-k))材料等の誘電体バリア610の材料は、窒化物除去等の犠牲領域619の高温リン酸除去と、酸化物段除去等の分離領域618の除去のために使用されるHFまたは他のケミストリとの両方に抵抗することが可能であるように堆積される。AlOxに関して、これらのケミストリに耐えるようにAlOxを堆積するために実施され得る、高温ALDプロセス及びハロゲン化合物ベースALDプロセスがある。ハロゲン化物法は、これらの堆積膜が高温リン酸ならびにHF及び他の酸化物エッチングケミストリに耐えるように実施され得るように、HfOx及び他の高誘電率材料を堆積するために存在する。除去プロセスを存続するようにHfOx及び/または誘電体バリア610の他の高誘電率材料を形成するための他のプロセスは、標準的な金属有機ALD前駆体の使用を含み得る。除去プロセスを存続するために誘電体バリア610を条件付ける他のプロセスは、ALD堆積後の様々な処置を使用することを含み得る。これらの他のプロセスは、アニール(不活性環境または反応環境のいずか一方で行われる)、プラズマ処理等を含み得る。 Dielectric barrier 610 materials, such as AlO x or other high dielectric constant ( high-k ) materials, are separated from high-temperature phosphoric acid removal in the sacrificial region 619, such as nitride removal, and oxide stage removal, etc. Accumulated to be capable of resisting both HF or other chemistries used for the removal of region 618. For AlO x , there are high temperature ALD processes and halogen compound based ALD processes that can be performed to deposit AlO x to withstand these chemistries . Halide methods exist to deposit HfOx and other high dielectric constant materials so that these deposits can be implemented to withstand high temperature phosphoric acid and HF and other oxide etching chemistries . Other processes for forming HfO x and / or other high dielectric constant materials of the dielectric barrier 610 to survive the removal process may include the use of standard metal organic ALD precursors. Other processes that condition the dielectric barrier 610 to survive the removal process may include the use of various treatments after ALD deposition. These other processes may include annealing (performed in either the inert environment or the reaction environment), plasma treatment and the like.
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US15/675,197 US10446572B2 (en) | 2017-08-11 | 2017-08-11 | Void formation for charge trap structures |
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PCT/US2018/044990 WO2019032373A1 (en) | 2017-08-11 | 2018-08-02 | Void formation for charge trap structures |
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