JPWO2016147970A1 - Photoelectric conversion element and method for producing photoelectric conversion element - Google Patents
Photoelectric conversion element and method for producing photoelectric conversion element Download PDFInfo
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- 239000010703 silicon Substances 0.000 claims abstract description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 53
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
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Abstract
光電変換素子は、第１導電型または第２導電型の半導体基板（１）と、半導体基板（１）の第１主面（１ｂ）の面内または面上の第１導電型領域（３，６５）と、半導体基板（１）の第１主面（１ｂ）の面内若しくは面上、または第１主面（１ｂ）とは異なる第２主面（１ａ）の面内若しくは面上の第２導電型領域（５，６３）と、第１導電型領域（３，６５）上の電極（７）と、第２導電型領域（５，６３）上の電極（８）とを備えている。電極（７，８）の少なくとも１つが銀とシリコンとを含んでいる。The photoelectric conversion element includes a first conductivity type or second conductivity type semiconductor substrate (1), and a first conductivity type region (3, 3) in or on the first main surface (1b) of the semiconductor substrate (1). 65) and the first main surface (1b) of the semiconductor substrate (1) or the second main surface (1a) different from the first main surface (1b). A second conductivity type region (5, 63); an electrode (7) on the first conductivity type region (3, 65); and an electrode (8) on the second conductivity type region (5, 63). . At least one of the electrodes (7, 8) includes silver and silicon.
Description
本発明は、光電変換素子および光電変換素子の製造方法に関する。 The present invention relates to a photoelectric conversion element and a method for manufacturing the photoelectric conversion element.
太陽光エネルギを電気エネルギに直接変換する太陽電池は、近年、特に、地球環境問題の観点から、次世代のエネルギ源としての期待が急激に高まっている。なかでも、現在、最も多く製造および販売されている太陽電池は、太陽光が入射する側の主面である受光面と受光面の反対側の主面である裏面とにそれぞれ電極が形成された両面電極型太陽電池であるが、裏面のみに電極を形成した裏面接合型太陽電池の開発も進められている（たとえば特許文献１参照）。 In recent years, a solar cell that directly converts solar energy into electric energy has been rapidly expected as a next-generation energy source particularly from the viewpoint of global environmental problems. In particular, the most manufactured and sold solar cells have electrodes formed on the light receiving surface that is the main surface on which sunlight is incident and the back surface that is the main surface opposite to the light receiving surface. Although it is a double-sided electrode type solar cell, the development of the back junction type solar cell which formed the electrode only in the back surface is also advanced (for example, refer patent document 1).
図２８に、特許文献１に記載の裏面接合型太陽電池の模式的な断面図を示す。図２８に示される裏面接合型太陽電池は、半導体基板１１１の受光面上に、ｉ型非晶質半導体層１１９、ｎ型非晶質半導体層１２０、および絶縁層１２４が順次積層された構成を有する。 FIG. 28 is a schematic cross-sectional view of the back junction solar cell described in Patent Document 1. The back junction solar cell shown in FIG. 28 has a configuration in which an i-type amorphous semiconductor layer 119, an n-type amorphous semiconductor layer 120, and an insulating layer 124 are sequentially stacked on the light-receiving surface of a semiconductor substrate 111. Have.
半導体基板１１１の裏面のｎ側電極１１６に対応する領域においては、半導体基板１１１上に、ｉ型非晶質半導体層１１２、ｎ型非晶質半導体層１１４、絶縁層１２１、およびｎ側電極１１６が順次積層されている。また、ｉ型非晶質半導体層１１２とｎ型非晶質半導体層１１４との積層体からＩＮ積層体１２２が構成されており、絶縁層１２１を貫通する穴を通してｎ型非晶質半導体層１１４とｎ側電極１１６とが接続されている。 In a region corresponding to the n-side electrode 116 on the back surface of the semiconductor substrate 111, the i-type amorphous semiconductor layer 112, the n-type amorphous semiconductor layer 114, the insulating layer 121, and the n-side electrode 116 are formed on the semiconductor substrate 111. Are sequentially stacked. Further, an IN stacked body 122 is formed by a stacked body of the i-type amorphous semiconductor layer 112 and the n-type amorphous semiconductor layer 114, and the n-type amorphous semiconductor layer 114 is passed through a hole penetrating the insulating layer 121. And the n-side electrode 116 are connected.
半導体基板１１１の裏面のｐ側電極１１７に対応する領域においては、半導体基板１１１上に、ｉ型非晶質半導体層１１３、ｐ型非晶質半導体層１１５、およびｐ側電極１１７が順次積層されている。また、ｉ型非晶質半導体層１１３とｐ型非晶質半導体層１１５との積層体からＩＰ積層体１２３が構成されている。 In a region corresponding to the p-side electrode 117 on the back surface of the semiconductor substrate 111, the i-type amorphous semiconductor layer 113, the p-type amorphous semiconductor layer 115, and the p-side electrode 117 are sequentially stacked on the semiconductor substrate 111. ing. In addition, the IP stacked body 123 is formed of a stacked body of the i-type amorphous semiconductor layer 113 and the p-type amorphous semiconductor layer 115.
ｎ側電極１１６およびｐ側電極１１７は、それぞれ、第１導電層１１６ａ，１１７ａ、第２導電層１１６ｂ，１１７ｂ、第３導電層１１６ｃ，１１７ｃおよび第４導電層１１６ｄ，１１７ｄがこの順に積層されることによって構成されている。 In the n-side electrode 116 and the p-side electrode 117, the first conductive layers 116a and 117a, the second conductive layers 116b and 117b, the third conductive layers 116c and 117c, and the fourth conductive layers 116d and 117d are stacked in this order. Is made up of.
図２９に、図２８に示される裏面接合型太陽電池の製造方法のフローチャートを示す。以下、図２９を参照して、図２８に示される裏面接合型太陽電池の製造方法について説明する。まず、ステップＳ１ａにおいて、半導体基板１１１の受光面および裏面をそれぞれ洗浄する。 FIG. 29 shows a flowchart of the manufacturing method of the back junction solar cell shown in FIG. Hereafter, with reference to FIG. 29, the manufacturing method of the back junction type solar cell shown by FIG. 28 is demonstrated. First, in step S1a, the light receiving surface and the back surface of the semiconductor substrate 111 are each cleaned.
次に、ステップＳ２ａにおいて、半導体基板１１１の受光面上にｉ型非晶質半導体層１１９とｎ型非晶質半導体層１２０とを形成するとともに、半導体基板１１１の裏面上にｉ型非晶質半導体層１１２とｎ型非晶質半導体層１１４とを形成する。 Next, in step S <b> 2 a, the i-type amorphous semiconductor layer 119 and the n-type amorphous semiconductor layer 120 are formed on the light receiving surface of the semiconductor substrate 111 and the i-type amorphous semiconductor is formed on the back surface of the semiconductor substrate 111. A semiconductor layer 112 and an n-type amorphous semiconductor layer 114 are formed.
次に、ステップＳ３ａにおいて、ｎ型非晶質半導体層１２０上に酸化シリコン、窒化シリコンまたは酸窒化シリコンからなる絶縁層１２４を形成するとともに、ｎ型非晶質半導体層１１４上に酸化シリコン、窒化シリコンまたは酸窒化シリコンからなる絶縁層１２１を形成する。 Next, in step S3a, an insulating layer 124 made of silicon oxide, silicon nitride, or silicon oxynitride is formed on the n-type amorphous semiconductor layer 120, and silicon oxide, nitride is formed on the n-type amorphous semiconductor layer 114. An insulating layer 121 made of silicon or silicon oxynitride is formed.
次に、ステップＳ４ａにおいて、絶縁層１２１を酸性のエッチング液を用いてエッチングすることにより、絶縁層１２１の一部分を除去する。 Next, in step S4a, the insulating layer 121 is etched using an acidic etchant to remove a portion of the insulating layer 121.
次に、ステップＳ５ａにおいて、ステップＳ４ａにおいてパターニングした絶縁層１２１をマスクとして用いて、ｉ型非晶質半導体層１１２とｎ型非晶質半導体層１１４とをアルカリ性のエッチング液を用いてエッチングすることにより、ｉ型非晶質半導体層１１２およびｎ型非晶質半導体層１１４の絶縁層１２１により覆われている部分以外の部分を除去する。 Next, in step S5a, using the insulating layer 121 patterned in step S4a as a mask, the i-type amorphous semiconductor layer 112 and the n-type amorphous semiconductor layer 114 are etched using an alkaline etchant. Thus, portions other than the portions covered by the insulating layer 121 of the i-type amorphous semiconductor layer 112 and the n-type amorphous semiconductor layer 114 are removed.
次に、ステップＳ６ａにおいて、半導体基板１１１の裏面を覆うように、ｉ型非晶質半導体層１１３とｐ型非晶質半導体層１１５とをこの順序で形成する。 Next, in step S6a, the i-type amorphous semiconductor layer 113 and the p-type amorphous semiconductor layer 115 are formed in this order so as to cover the back surface of the semiconductor substrate 111.
次に、ステップＳ７ａにおいて、ｉ型非晶質半導体層１１３およびｐ型非晶質半導体層１１５の絶縁層１２１上に位置している部分の一部分をアルカリ性のエッチング液を用いてエッチングする。 Next, in step S7a, portions of the i-type amorphous semiconductor layer 113 and the p-type amorphous semiconductor layer 115 located on the insulating layer 121 are etched using an alkaline etchant.
次に、ステップＳ８ａにおいて、バッファードフッ酸をエッチング液として用いたエッチングにより絶縁層１２１をエッチングする。 Next, in step S8a, the insulating layer 121 is etched by etching using buffered hydrofluoric acid as an etchant.
最後に、ステップＳ９ａにおいて、ＩＮ積層体１２２上にｎ側電極１１６を形成し、ＩＰ積層体１２３上にｐ側電極１１７を形成することによって、図２８に示される裏面接合型太陽電池が製造される。具体的には、ｎ側電極１１６およびｐ側電極１１７は、以下のように形成される。まず、ＴＣＯからなる第１導電層１１６ａ，１１７ａ、およびＣｕなどの金属や合金からなる第２導電層１１６ｂ，１１７ｂをスパッタリング法等の薄膜形成法によりこの順序で形成する。次に、第１導電層１１６ａ，１１７ａおよび第２導電層１１６ｂ，１１７ｂをフォトリソグラフィー法などにより分断する。その後、Ｃｕからなる第３導電層１１６ｃ，１１７ｃ、およびＳｎからなる第４導電層１１６ｄ，１１７ｄをめっきにより形成することによって、ｎ側電極１１６およびｐ側電極１１７が形成される（特許文献１の段落［００５６］〜［００５８］）。 Finally, in step S9a, the n-side electrode 116 is formed on the IN stacked body 122, and the p-side electrode 117 is formed on the IP stacked body 123, whereby the back junction solar cell shown in FIG. The Specifically, the n-side electrode 116 and the p-side electrode 117 are formed as follows. First, the first conductive layers 116a and 117a made of TCO and the second conductive layers 116b and 117b made of a metal or alloy such as Cu are formed in this order by a thin film forming method such as a sputtering method. Next, the first conductive layers 116a and 117a and the second conductive layers 116b and 117b are divided by a photolithography method or the like. Thereafter, the third conductive layers 116c and 117c made of Cu and the fourth conductive layers 116d and 117d made of Sn are formed by plating, whereby the n-side electrode 116 and the p-side electrode 117 are formed (see Patent Document 1). Paragraphs [0056] to [0058]).
しかしながら、特許文献１に記載の裏面接合型太陽電池のｎ側電極１１６およびｐ側電極１１７はそれぞれｎ型非晶質半導体層１１４およびｐ型非晶質半導体層１１５に対するコンタクト抵抗が高かったため、その改善が要望されていた。 However, the n-side electrode 116 and the p-side electrode 117 of the back junction solar cell described in Patent Document 1 have high contact resistances with respect to the n-type amorphous semiconductor layer 114 and the p-type amorphous semiconductor layer 115, respectively. Improvement was requested.
ここで開示された実施形態は、第１導電型または第２導電型の半導体基板と、半導体基板の第１主面の面内または面上の第１導電型領域と、半導体基板の第１主面の面内若しくは面上、または第１主面とは異なる第２主面の面内若しくは面上の第２導電型領域と、第１導電型領域上の電極と、第２導電型領域上の電極と、を備え、電極の少なくとも１つが、銀と、シリコンとを含む、光電変換素子である。 The embodiment disclosed herein includes a semiconductor substrate of a first conductivity type or a second conductivity type, a first conductivity type region in or on the first main surface of the semiconductor substrate, and a first main type of the semiconductor substrate. A second conductivity type region in or on the surface of the second main surface different from the first main surface, an electrode on the first conductivity type region, and on the second conductivity type region And at least one of the electrodes includes silver and silicon.
ここで開示された実施形態によれば、電極のコンタクト抵抗を低減することができる。 According to the embodiment disclosed herein, the contact resistance of the electrode can be reduced.
以下、ここで開示される実施形態の光電変換素子の一例としての実施形態のヘテロ接合型バックコンタクトセルについて説明する。なお、実施形態の説明に用いられる図面において、同一の参照符号は、同一部分または相当部分を表わすものとする。 Hereinafter, the heterojunction back contact cell of the embodiment as an example of the photoelectric conversion element of the embodiment disclosed herein will be described. In the drawings used to describe the embodiments, the same reference numerals represent the same or corresponding parts.
［実施形態１］
＜ヘテロ接合型バックコンタクトセルの構造＞
図１に、実施形態１のヘテロ接合型バックコンタクトセルの模式的な断面図を示す。実施形態１のヘテロ接合型バックコンタクトセルは、半導体基板１と、半導体基板１の受光面となる第２の主面１ａとは反対側の裏面となる第１の主面１ｂ上の第１のｉ型非晶質半導体膜２および第２のｉ型非晶質半導体膜４と、第１のｉ型非晶質半導体膜２上の第１導電型非晶質半導体膜３と、第２のｉ型非晶質半導体膜４上の第２導電型非晶質半導体膜５と、第１導電型非晶質半導体膜３に接する第１電極７と、第２導電型非晶質半導体膜５に接する第２電極８とを備えている。[Embodiment 1]
<Structure of heterojunction back contact cell>
FIG. 1 is a schematic cross-sectional view of the heterojunction back contact cell of the first embodiment. The heterojunction back contact cell according to Embodiment 1 includes a semiconductor substrate 1 and a first main surface 1b on the first main surface 1b that is the back surface opposite to the second main surface 1a that is the light receiving surface of the semiconductor substrate 1. i-type amorphous semiconductor film 2 and second i-type amorphous semiconductor film 4, first conductive type amorphous semiconductor film 3 on first i-type amorphous semiconductor film 2, second type A second conductive amorphous semiconductor film 5 on the i-type amorphous semiconductor film 4, a first electrode 7 in contact with the first conductive amorphous semiconductor film 3, and a second conductive amorphous semiconductor film 5 And a second electrode 8 in contact with.
本実施形態において、半導体基板１はｎ型単結晶シリコン基板であり、第１のｉ型非晶質半導体膜２および第２のｉ型非晶質半導体膜４はそれぞれｉ型非晶質シリコン膜であり、第１導電型非晶質半導体膜３はｐ型非晶質シリコン膜であり、第２導電型非晶質半導体膜５はｎ型非晶質シリコン膜である。 In the present embodiment, the semiconductor substrate 1 is an n-type single crystal silicon substrate, and the first i-type amorphous semiconductor film 2 and the second i-type amorphous semiconductor film 4 are i-type amorphous silicon films, respectively. The first conductive amorphous semiconductor film 3 is a p-type amorphous silicon film, and the second conductive amorphous semiconductor film 5 is an n-type amorphous silicon film.
実施形態１のヘテロ接合型バックコンタクトセルにおいては、第１電極７および第２電極８がそれぞれ銀（Ａｇ）とシリコン（Ｓｉ）とを含んでいる。 In the heterojunction back contact cell of the first embodiment, the first electrode 7 and the second electrode 8 contain silver (Ag) and silicon (Si), respectively.
なお、本実施形態において、「ｉ型」は、完全な真性の状態だけでなく、十分に低濃度（ｎ型不純物濃度が１×１０15個／ｃｍ3未満、かつｐ型不純物濃度が１×１０15個／ｃｍ3未満）であればｎ型またはｐ型の不純物が混入された状態のものも含む意味である。また、本実施形態において、「ｎ型」は、ｎ型不純物濃度が１×１０15個／ｃｍ3以上の状態を意味し、「ｐ型」は、ｐ型不純物濃度が１×１０15個／ｃｍ3以上の状態を意味する。ｎ型不純物濃度およびｐ型不純物濃度は、たとえば二次イオン質量分析（ＳＩＭＳ）によって測定することができる。In the present embodiment, “i-type” is not only a completely intrinsic state but also a sufficiently low concentration (n-type impurity concentration is less than 1 × 10 15 / cm 3 and p-type impurity concentration is 1 × (Less than 10 15 / cm 3 ) is meant to include n-type or p-type impurities. In the present embodiment, “n-type” means a state where the n-type impurity concentration is 1 × 10 15 / cm 3 or more, and “p-type” means that the p-type impurity concentration is 1 × 10 15 / cm 3. It means a state of cm 3 or more. The n-type impurity concentration and the p-type impurity concentration can be measured by, for example, secondary ion mass spectrometry (SIMS).
また、本実施形態において、「非晶質シリコン」には、シリコン原子の未結合手が水素で終端されていない非晶質シリコンだけでなく、水素化非晶質シリコンなどのシリコン原子の未結合手が水素等で終端されたものも含まれるものとする。 In this embodiment, “amorphous silicon” includes not only amorphous silicon in which the dangling bonds of silicon atoms are not terminated with hydrogen, but also dangling of silicon atoms such as hydrogenated amorphous silicon. It also includes those whose hands are terminated with hydrogen or the like.
＜ヘテロ接合型バックコンタクトセルの製造方法＞
以下、図２〜図１０の模式的断面図を参照して、実施形態１のヘテロ接合型バックコンタクトセルの製造方法の一例について説明する。<Method for manufacturing heterojunction back contact cell>
Hereinafter, an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1 will be described with reference to the schematic cross-sectional views of FIGS.
まず、図２に示すように、半導体基板１の受光面となる第２の主面１ａに凹凸形状を形成する。第２の主面１ａの凹凸形状は、たとえば、半導体基板１の第２の主面１ａをテクスチャエッチングすることにより形成することができる。なお、半導体基板１の第２の主面１ａ上には誘電体膜が形成されてもよい。 First, as shown in FIG. 2, a concavo-convex shape is formed on the second main surface 1 a serving as the light receiving surface of the semiconductor substrate 1. The uneven shape of the second main surface 1a can be formed by, for example, texture etching the second main surface 1a of the semiconductor substrate 1. A dielectric film may be formed on the second main surface 1a of the semiconductor substrate 1.
次に、図３に示すように、半導体基板１の第１の主面１ｂの全面に接するように第１のｉ型非晶質半導体膜２を形成し、その後、第１のｉ型非晶質半導体膜２の全面に接するように第１導電型非晶質半導体膜３を形成する。第１のｉ型非晶質半導体膜２および第１導電型非晶質半導体膜３の形成方法は特に限定されないが、たとえばプラズマＣＶＤ（Chemical Vapor Deposition）法を用いることができる。 Next, as shown in FIG. 3, a first i-type amorphous semiconductor film 2 is formed so as to be in contact with the entire surface of the first main surface 1b of the semiconductor substrate 1, and then the first i-type amorphous semiconductor is formed. A first conductive type amorphous semiconductor film 3 is formed so as to be in contact with the entire surface of the crystalline semiconductor film 2. A method for forming the first i-type amorphous semiconductor film 2 and the first conductive type amorphous semiconductor film 3 is not particularly limited. For example, a plasma CVD (Chemical Vapor Deposition) method can be used.
次に、図４に示すように、第１導電型非晶質半導体膜３上に、第１のｉ型非晶質半導体膜２と第１導電型非晶質半導体膜３との積層体である第１の積層体５１を厚さ方向にエッチングする箇所に開口部を有するエッチングマスク３１を形成する。 Next, as shown in FIG. 4, a stacked body of the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 is formed on the first conductive-type amorphous semiconductor film 3. An etching mask 31 having an opening at a location where a certain first stacked body 51 is etched in the thickness direction is formed.
次に、図５に示すように、エッチングマスク３１をマスクとして、第１の積層体５１を厚さ方向にエッチングすることによって、半導体基板１の第１の主面１ｂの一部を露出させる。その後、図６に示すように、エッチングマスク３１を除去する。 Next, as shown in FIG. 5, by using the etching mask 31 as a mask, the first stacked body 51 is etched in the thickness direction to expose a part of the first main surface 1 b of the semiconductor substrate 1. Thereafter, as shown in FIG. 6, the etching mask 31 is removed.
次に、図７に示すように、半導体基板１の露出面および第１の積層体５１を覆うように第２のｉ型非晶質半導体膜４を形成し、その後、第２のｉ型非晶質半導体膜４の全面に接するように第２導電型非晶質半導体膜５を形成する。第２のｉ型非晶質半導体膜４および第２導電型非晶質半導体膜５の形成方法は特に限定されないが、たとえばプラズマＣＶＤ法を用いることができる。 Next, as shown in FIG. 7, the second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the semiconductor substrate 1 and the first stacked body 51, and then the second i-type non-type is formed. A second conductivity type amorphous semiconductor film 5 is formed so as to be in contact with the entire surface of the crystalline semiconductor film 4. A method for forming the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is not particularly limited, and for example, a plasma CVD method can be used.
次に、図８に示すように、半導体基板１の第１の主面１ｂ上の第２のｉ型非晶質半導体膜４と第２導電型非晶質半導体膜５との積層体である第２の積層体５２を残す部分にのみエッチングマスク３２を形成する。 Next, as shown in FIG. 8, a stacked body of the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 on the first main surface 1 b of the semiconductor substrate 1. The etching mask 32 is formed only on the portion where the second stacked body 52 is left.
次に、図９に示すように、エッチングマスク３２をマスクとして、第２の積層体５２の一部を厚さ方向にエッチングすることによって、第１導電型非晶質半導体膜３の一部を露出させる。 Next, as shown in FIG. 9, a part of the first conductive type amorphous semiconductor film 3 is etched by etching a part of the second stacked body 52 in the thickness direction using the etching mask 32 as a mask. Expose.
次に、図１０に示すように、第１導電型非晶質半導体膜３に接するように第１の銀層７ａを形成するとともに、第２導電型非晶質半導体膜５に接するように第２の銀層８ａを形成する。ここで、第１の銀層７ａおよび第２の銀層８ａはそれぞれ主成分（最も原子数の多い成分）としてＡｇを含む層であれば副成分（主成分よりも原子数の少ない成分）としてＡｇ以外の原子を含んでいてもよい。副成分は特に限定されないが、たとえば窒素（Ｎ）、酸素（Ｏ）および炭素（Ｃ）からなる群から選択される少なくとも１種の成分を挙げることができる。なお、第１の銀層７ａおよび第２の銀層８ａの形成方法は特に限定されないが、たとえば蒸着法などを用いることができる。また、第１の銀層７ａおよび第２の銀層８ａは、たとえば、蒸着法またはめっき法によって形成してもよい。すなわち、第１の銀層７ａおよび第２の銀層８ａは、それぞれ独立して、スパッタリング法、蒸着法およびめっき法からなる群から選択された少なくとも１つの方法により形成することができる。 Next, as shown in FIG. 10, the first silver layer 7 a is formed so as to be in contact with the first conductive amorphous semiconductor film 3, and the first silver layer 7 a is in contact with the second conductive amorphous semiconductor film 5. Two silver layers 8a are formed. Here, if each of the first silver layer 7a and the second silver layer 8a is a layer containing Ag as a main component (a component having the largest number of atoms), a subcomponent (a component having a smaller number of atoms than the main component) is used. An atom other than Ag may be contained. The subcomponent is not particularly limited, and examples thereof include at least one component selected from the group consisting of nitrogen (N), oxygen (O), and carbon (C). In addition, the formation method of the 1st silver layer 7a and the 2nd silver layer 8a is not specifically limited, For example, a vapor deposition method etc. can be used. Moreover, you may form the 1st silver layer 7a and the 2nd silver layer 8a by the vapor deposition method or the plating method, for example. That is, the first silver layer 7a and the second silver layer 8a can be independently formed by at least one method selected from the group consisting of sputtering, vapor deposition, and plating.
次に、第１導電型非晶質半導体膜３および第１の銀層７ａ、ならびに第２導電型非晶質半導体膜５および第２の銀層８ａを半導体基板１とともにアニールする。これにより、第１導電型非晶質半導体膜３から第１の銀層７ａにＳｉが移動して第１の銀層７ａにＳｉが取り込まれて第１電極７が形成される。また、第２導電型非晶質半導体膜５から第２の銀層８ａにＳｉが移動して第２の銀層８ａにＳｉが取り込まれて第２電極８が形成される。以上により、実施形態１のヘテロ接合型バックコンタクトセルが完成する。ここで、第１電極７および第２電極８の少なくとも一方の電極の厚さが２０μｍ以下であることが好ましく、１０μｍ以下であることがより好ましい。第１電極７および第２電極８の少なくとも一方の電極の厚さが２０μｍ以下である場合には電極の厚さに起因する熱変形の応力を抑制することができ、第１電極７および第２電極８の少なくとも一方の電極の厚さが１０μｍ以下である場合には、電極が薄いことによって電流経路が短くなるため、電極を低抵抗とすることができる。また、第１電極７および第２電極８の少なくとも一方の電極の厚さは１μｍ以上であることが好ましい。第１電極７および第２電極８の少なくとも一方の電極の厚さが１μｍ以上である場合には、電極の厚さが薄すぎることによって銀の結晶成長が悪化して電極が高抵抗になるのを抑制することができる。 Next, the first conductive type amorphous semiconductor film 3 and the first silver layer 7a, and the second conductive type amorphous semiconductor film 5 and the second silver layer 8a are annealed together with the semiconductor substrate 1. As a result, Si moves from the first conductive type amorphous semiconductor film 3 to the first silver layer 7a, and Si is taken into the first silver layer 7a to form the first electrode 7. Further, Si moves from the second conductive type amorphous semiconductor film 5 to the second silver layer 8a, and Si is taken into the second silver layer 8a to form the second electrode 8. Thus, the heterojunction back contact cell of Embodiment 1 is completed. Here, the thickness of at least one of the first electrode 7 and the second electrode 8 is preferably 20 μm or less, and more preferably 10 μm or less. When the thickness of at least one of the first electrode 7 and the second electrode 8 is 20 μm or less, it is possible to suppress thermal deformation stress caused by the thickness of the electrode. When the thickness of at least one of the electrodes 8 is 10 μm or less, the current path is shortened due to the thinness of the electrode, so that the electrode can have a low resistance. The thickness of at least one of the first electrode 7 and the second electrode 8 is preferably 1 μm or more. When the thickness of at least one of the first electrode 7 and the second electrode 8 is 1 μm or more, the crystal growth of silver is deteriorated and the electrode becomes high resistance because the electrode is too thin. Can be suppressed.
なお、第１導電型非晶質半導体膜３および第２導電型非晶質半導体膜５からそれぞれ第１の銀層７ａおよび第２の銀層８ａにＳｉが移動する理由は不明であるが、たとえば加熱温度、時間および雰囲気などのアニール条件を適宜調整することによって、第１導電型非晶質半導体膜３および第２導電型非晶質半導体膜５の結晶化を抑制しつつ、ＡｇとＳｉとを含む第１電極７および第２電極８を形成できることが確認されている。第１導電型非晶質半導体膜３および第２導電型非晶質半導体膜５の結晶化を抑制しつつ、ＡｇとＳｉとを含む第１電極７および第２電極８を形成するための好適なアニール条件としては、たとえば、５０℃以上３００℃以下の温度で１０分以上６０分以下アニールする条件が挙げられる。銀ペーストを塗布した後に焼成することにより第１電極７および第２電極８を形成する場合には、銀ペーストから銀電極を形成するための焼成温度が高すぎて、第１導電型非晶質半導体膜３および第２導電型非晶質半導体膜５等の非晶質半導体膜が結晶化し得る。一方、本実施形態においては、スパッタリング法、蒸着法およびめっき法からなる群から選択された少なくとも１つの方法により第１の銀層７ａおよび第２の銀層８ａを形成した後に、第１の銀層７ａおよび第２の銀層８ａをアニールすることによって、銀ペーストの焼成温度よりも低いアニール温度で第１電極７および第２電極８を形成することができる。これにより、本実施形態においては、第１導電型非晶質半導体膜３および第２導電型非晶質半導体膜５等の非晶質半導体膜の結晶化を抑制して電極として機能する第１電極７および第２電極８を形成することができるとともに、第１導電型非晶質半導体膜３および第２導電型非晶質半導体膜５等の非晶質半導体膜および半導体基板１への熱ダメージも低減することができる。 The reason why Si moves from the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5 to the first silver layer 7a and the second silver layer 8a, respectively, is unknown. For example, by appropriately adjusting annealing conditions such as heating temperature, time, and atmosphere, the crystallization of the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5 is suppressed, and Ag and Si are suppressed. It has been confirmed that the first electrode 7 and the second electrode 8 including these can be formed. Suitable for forming first electrode 7 and second electrode 8 containing Ag and Si while suppressing crystallization of first conductive type amorphous semiconductor film 3 and second conductive type amorphous semiconductor film 5 Examples of suitable annealing conditions include conditions for annealing at a temperature of 50 to 300 ° C. for 10 to 60 minutes. When the first electrode 7 and the second electrode 8 are formed by baking after applying the silver paste, the baking temperature for forming the silver electrode from the silver paste is too high, and the first conductivity type amorphous Amorphous semiconductor films such as the semiconductor film 3 and the second conductivity type amorphous semiconductor film 5 can be crystallized. On the other hand, in the present embodiment, after the first silver layer 7a and the second silver layer 8a are formed by at least one method selected from the group consisting of sputtering, vapor deposition, and plating, the first silver is formed. By annealing the layer 7a and the second silver layer 8a, the first electrode 7 and the second electrode 8 can be formed at an annealing temperature lower than the firing temperature of the silver paste. As a result, in the present embodiment, the first conductivity functioning as an electrode while suppressing the crystallization of the amorphous semiconductor films such as the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5. The electrode 7 and the second electrode 8 can be formed, and heat to the amorphous semiconductor film such as the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5 and the semiconductor substrate 1 can be formed. Damage can also be reduced.
図１１に実施形態１のヘテロ接合型バックコンタクトセルの断面の透過型電子顕微鏡（ＴＥＭ）写真を示し、図１２にエネルギ分散型Ｘ線分光法（ＥＤＸ）による成分の濃度［原子％］とｃ−ＳｉからＡｇ側への距離［μｍ］との関係を示している。なお、図１１および図１２において、ｃ−Ｓｉがｎ型単結晶シリコン基板を示し、ａ−Ｓｉが非晶質シリコン膜を示し、Ａｇが電極を示している。 FIG. 11 shows a transmission electron microscope (TEM) photograph of a cross section of the heterojunction back contact cell of Embodiment 1, and FIG. 12 shows the component concentration [atomic%] and c by energy dispersive X-ray spectroscopy (EDX). It shows the relationship with the distance [μm] from -Si to Ag side. 11 and 12, c-Si represents an n-type single crystal silicon substrate, a-Si represents an amorphous silicon film, and Ag represents an electrode.
ここで、図１２に示す結果から明らかなように、電極中にＳｉが存在していることを確認することができる。また、電極には、主成分としてのＡｇ以外にも、副成分としてＮおよびＯも含まれていることが確認されている。 Here, as is apparent from the results shown in FIG. 12, it can be confirmed that Si is present in the electrode. Further, it has been confirmed that the electrode contains N and O as subcomponents in addition to Ag as the main component.
図１３に、実施形態１のヘテロ接合型バックコンタクトセルの構造とＳｉ濃度との関係の一例を模式的に示す。図１３（ａ）に実施形態１のヘテロ接合型バックコンタクトセルの断面構造を模式的に示す図であり、図１３（ｂ）にＳｉ濃度の分布の一例を示す。 FIG. 13 schematically shows an example of the relationship between the structure of the heterojunction back contact cell of Embodiment 1 and the Si concentration. FIG. 13A schematically shows a cross-sectional structure of the heterojunction back contact cell of Embodiment 1, and FIG. 13B shows an example of a Si concentration distribution.
図１３（ａ）および図１３（ｂ）に示す例においては、Ｓｉ濃度は、非晶質シリコン膜と電極との界面から電極側に進むにしたがって指数関数的に減少している。 In the examples shown in FIGS. 13A and 13B, the Si concentration decreases exponentially as it proceeds from the interface between the amorphous silicon film and the electrode toward the electrode.
＜課題解決のメカニズム＞
実施形態１のヘテロ接合型バックコンタクトセルにおいては、第１導電型非晶質半導体膜３に対する第１電極７のコンタクト抵抗および第２導電型非晶質半導体膜５に対する第１電極７のコンタクト抵抗を、それぞれ、特許文献１のｎ型非晶質半導体層１１４に対するｎ側電極１１６のコンタクト抵抗およびｐ型非晶質半導体層１１５に対するｐ側電極１１７のコンタクト抵抗と比べて低減することができ、特性を向上することができることが確認されている。<Mechanism of problem solving>
In the heterojunction back contact cell of the first embodiment, the contact resistance of the first electrode 7 with respect to the first conductive type amorphous semiconductor film 3 and the contact resistance of the first electrode 7 with respect to the second conductive type amorphous semiconductor film 5. Can be reduced as compared with the contact resistance of the n-side electrode 116 with respect to the n-type amorphous semiconductor layer 114 and the contact resistance of the p-side electrode 117 with respect to the p-type amorphous semiconductor layer 115 of Patent Document 1, respectively. It has been confirmed that the characteristics can be improved.
これは、実施形態１のヘテロ接合型バックコンタクトセルにおいては、第１導電型非晶質半導体膜３（ｐ型非晶質シリコン膜）に接する第１電極７と、第２導電型非晶質半導体膜５（ｎ型非晶質シリコン膜）に接する第２電極８とにはそれぞれＡｇとＳｉとを含む電極が用いられているが、特許文献１のｎ側電極１１６およびｐ側電極１１７にはそれぞれＡｇとＳｉとを含む電極が用いられていないことによるものと考えられる。 In the heterojunction back contact cell of the first embodiment, the first electrode 7 in contact with the first conductive type amorphous semiconductor film 3 (p type amorphous silicon film) and the second conductive type amorphous semiconductor are used. Although electrodes containing Ag and Si are used for the second electrode 8 in contact with the semiconductor film 5 (n-type amorphous silicon film), respectively, the n-side electrode 116 and the p-side electrode 117 of Patent Document 1 are used. Is considered to be due to the fact that electrodes containing Ag and Si are not used.
＜変形例＞
なお、上記においては、半導体基板１の導電型がｎ型である場合について説明したが、半導体基板１の導電型はｐ型であってもよい。<Modification>
In the above description, the case where the conductivity type of the semiconductor substrate 1 is n-type has been described. However, the conductivity type of the semiconductor substrate 1 may be p-type.
また、上記においては、第１導電型がｐ型であり、第２導電型がｎ型である場合について説明したが、第１導電型がｎ型であり、第２導電型がｐ型であってもよい。 In the above description, the first conductivity type is p-type and the second conductivity type is n-type. However, the first conductivity type is n-type and the second conductivity type is p-type. May be.
また、上記においては、第１電極７および第２電極８の両方がＡｇとＳｉとを含む場合について説明したが、第１電極７または第２電極８のいずれか一方のみがＡｇとＳｉとを含んでいてもよい。また、上記においては、第１電極７および第２電極８のすべてがＡｇとＳｉとを含む場合について説明したが、第１電極７および第２電極８の少なくとも１つがＡｇとＳｉとを含んでいればよい。 In the above description, the case where both the first electrode 7 and the second electrode 8 include Ag and Si has been described. However, only one of the first electrode 7 and the second electrode 8 includes Ag and Si. May be included. In the above description, the case where all of the first electrode 7 and the second electrode 8 include Ag and Si has been described. However, at least one of the first electrode 7 and the second electrode 8 includes Ag and Si. Just have to be.
［実施形態２］
図１４に、実施形態２のヘテロ接合型バックコンタクトセルの模式的な断面図を示す。図１４に示すように、実施形態２のヘテロ接合型バックコンタクトセルは、第１電極７と第１導電型非晶質半導体膜３との間のすべての領域に第１の介在層９ａを備えているとともに、第２電極８と第２導電型非晶質半導体膜５との間のすべての領域に第２の介在層９ｂを備えていることを特徴としている。このように、第１導電型非晶質半導体膜３に対する第１電極７のコンタクト抵抗および第２導電型非晶質半導体膜５に対する第２電極８のコンタクト抵抗の上昇に大きく影響を与えない程度の第１の介在層９ａおよび第２の介在層９ｂを形成することもできる。[Embodiment 2]
FIG. 14 is a schematic cross-sectional view of the heterojunction back contact cell of the second embodiment. As shown in FIG. 14, the heterojunction back contact cell of Embodiment 2 includes the first intervening layer 9 a in all regions between the first electrode 7 and the first conductive amorphous semiconductor film 3. In addition, the second intervening layer 9b is provided in all regions between the second electrode 8 and the second conductive type amorphous semiconductor film 5. As described above, the contact resistance of the first electrode 7 with respect to the first conductive type amorphous semiconductor film 3 and the contact resistance of the second electrode 8 with respect to the second conductive type amorphous semiconductor film 5 are not greatly affected. The first intervening layer 9a and the second intervening layer 9b can also be formed.
第１の介在層９ａとしては、たとえば第１導電型非晶質半導体膜３から第１電極７にキャリアを取り出すことができる層を用いることができるが、なかでもチタン（Ｔｉ）層を用いることが好ましい。第１の介在層９ａとしてＴｉ層を用いた場合には、第１導電型非晶質半導体膜３と第１電極７との間の密着性を向上することができる。 As the first intervening layer 9a, for example, a layer capable of extracting carriers from the first conductive type amorphous semiconductor film 3 to the first electrode 7 can be used, and in particular, a titanium (Ti) layer is used. Is preferred. When a Ti layer is used as the first intervening layer 9a, the adhesion between the first conductive type amorphous semiconductor film 3 and the first electrode 7 can be improved.
また、第２の介在層９ｂとしては、たとえば第２導電型非晶質半導体膜５から第２電極８にキャリアを取り出すことができる層を用いることができ、なかでもＴｉ層を用いることが好ましい。第２の介在層９ｂとしてＴｉ層を用いた場合には、第２導電型非晶質半導体膜５と第２電極８との間の密着性を向上することができる。 As the second intervening layer 9b, for example, a layer that can extract carriers from the second conductivity type amorphous semiconductor film 5 to the second electrode 8 can be used, and among these, a Ti layer is preferably used. . When a Ti layer is used as the second intervening layer 9b, the adhesion between the second conductive type amorphous semiconductor film 5 and the second electrode 8 can be improved.
なお、上記においては、第１の介在層９ａおよび第２の介在層９ｂの両方が存在する場合について説明したが、第１の介在層９ａまたは第２の介在層９ｂのいずれか一方のみが存在していてもよい。 In the above description, the case where both the first intervening layer 9a and the second intervening layer 9b exist has been described. However, only one of the first intervening layer 9a and the second intervening layer 9b exists. You may do it.
実施形態２における上記以外の説明は実施形態１と同様であるため、その説明については繰り返さない。 Since the description other than the above in the second embodiment is the same as that in the first embodiment, the description thereof will not be repeated.
［実施形態３］
図１５に、実施形態３のヘテロ接合型バックコンタクトセルの模式的な断面図を示す。図１５に示すように、実施形態３のヘテロ接合型バックコンタクトセルは、第１の介在層９ａおよび第２の介在層９ｂがそれぞれアイランド状であることを特徴としている。[Embodiment 3]
FIG. 15 is a schematic cross-sectional view of the heterojunction back contact cell of the third embodiment. As shown in FIG. 15, the heterojunction back contact cell of Embodiment 3 is characterized in that the first intervening layer 9a and the second intervening layer 9b are island-shaped.
実施形態３における上記以外の説明は実施形態１および実施形態２と同様であるため、その説明については繰り返さない。 Since the description other than the above in the third embodiment is the same as that in the first and second embodiments, the description thereof will not be repeated.
［実施形態４］
図１６に、実施形態の光電変換素子の他の一例である実施形態４の裏面電極型太陽電池セルの模式的な断面図を示す。図１６に示すように、実施形態４の裏面電極型太陽電池セルは、ｎ型単結晶シリコン基板からなる半導体基板１と、半導体基板１の裏面となる第１主面１ｂ内に間隔を空けて設けられた、第１導電型不純物含有領域としてのｐ型不純物拡散領域６５と、第２導電型不純物含有領域としてのｎ型不純物拡散領域６３とを備えている。また、ｐ型不純物拡散領域６５に接してＡｇとＳｉとを含む第１電極７が設けられており、ｎ型不純物拡散領域６３に接してＡｇとＳｉとを含む第２電極８が設けられている。[Embodiment 4]
In FIG. 16, the typical sectional drawing of the back surface electrode type photovoltaic cell of Embodiment 4 which is another example of the photoelectric conversion element of Embodiment is shown. As shown in FIG. 16, the back electrode type solar battery cell of Embodiment 4 is spaced apart from a semiconductor substrate 1 made of an n-type single crystal silicon substrate and a first main surface 1 b that is the back surface of the semiconductor substrate 1. A p-type impurity diffusion region 65 as a first conductivity type impurity-containing region and an n-type impurity diffusion region 63 as a second conductivity type impurity-containing region are provided. A first electrode 7 containing Ag and Si is provided in contact with the p-type impurity diffusion region 65, and a second electrode 8 containing Ag and Si is provided in contact with the n-type impurity diffusion region 63. Yes.
また、半導体基板１の裏面となる第１主面１ｂには、たとえば酸化シリコン膜または窒化シリコン膜等の誘電体膜６７が設けられており、半導体基板１の受光面となる第２主面１ａのテクスチャ構造６８上にもたとえば酸化シリコン膜または窒化シリコン膜等の誘電体膜６９が設けられている。 In addition, a dielectric film 67 such as a silicon oxide film or a silicon nitride film is provided on the first main surface 1 b that is the back surface of the semiconductor substrate 1, and the second main surface 1 a that is the light receiving surface of the semiconductor substrate 1. Also on the texture structure 68, a dielectric film 69 such as a silicon oxide film or a silicon nitride film is provided.
以下、図１７〜図２６の模式的断面図を参照して、実施形態４の裏面電極型太陽電池セルの製造方法の一例について説明する。 Hereinafter, an example of a method for manufacturing the back electrode type solar battery cell of Embodiment 4 will be described with reference to the schematic cross-sectional views of FIGS.
まず、図１７に示すように、半導体基板１の第１主面１ｂおよび第２主面１ａのそれぞれの全面に拡散マスク６２を設置し、半導体基板１の第１主面１ｂの拡散抑制マスク６２の一部に開口部６１ａを設ける。なお、開口部６１ａの形成方法は、特に限定されず、たとえばフォトリソグラフィ等の方法を用いることができる。 First, as shown in FIG. 17, a diffusion mask 62 is provided on each of the first main surface 1 b and the second main surface 1 a of the semiconductor substrate 1, and the diffusion suppression mask 62 on the first main surface 1 b of the semiconductor substrate 1 is set. An opening 61a is provided in a part of this. In addition, the formation method of the opening part 61a is not specifically limited, For example, methods, such as photolithography, can be used.
次に、図１８に示すように、ｎ型不純物含有ガス６４を流すことによって、半導体基板１の第１主面１ｂの拡散抑制マスク６２の開口部６１ａから露出している半導体基板１の第１主面１ｂにｎ型不純物を拡散させてｎ型不純物拡散領域６３を形成する。なお、ｎ型不純物含有ガス６４としては、たとえばｎ型不純物であるリンを含むＰＯＣｌ3などを用いることができる。また、ｎ型不純物拡散領域６３は、半導体基板１よりもｎ型不純物濃度が高い領域であればよい。Next, as shown in FIG. 18, by flowing an n-type impurity-containing gas 64, the first of the semiconductor substrate 1 exposed from the opening 61 a of the diffusion suppression mask 62 on the first main surface 1 b of the semiconductor substrate 1. An n-type impurity diffusion region 63 is formed by diffusing n-type impurities in the main surface 1b. As the n-type impurity-containing gas 64, for example, POCl 3 containing phosphorus which is an n-type impurity can be used. The n-type impurity diffusion region 63 may be a region having an n-type impurity concentration higher than that of the semiconductor substrate 1.
次に、半導体基板１の第１主面１ｂおよび第２主面１ａの拡散抑制マスク６２を一旦すべて除去した後に、半導体基板１の第１主面１ｂおよび第２主面１ａのそれぞれの全面に拡散抑制マスク６２を再度設置し、図１９に示すように、半導体基板１の第１主面１ｂの拡散抑制マスク６２の一部に開口部６１ｂを設ける。 Next, after all the diffusion suppression masks 62 on the first main surface 1b and the second main surface 1a of the semiconductor substrate 1 are once removed, the entire surfaces of the first main surface 1b and the second main surface 1a of the semiconductor substrate 1 are formed. The diffusion suppression mask 62 is installed again, and an opening 61b is provided in a part of the diffusion suppression mask 62 on the first main surface 1b of the semiconductor substrate 1 as shown in FIG.
次に、図２０に示すように、ｐ型不純物含有ガス６６を流すことによって、半導体基板１の第１主面１ｂの拡散抑制マスク６２の開口部６１ｂから露出している半導体基板１の第１主面１ｂにｐ型不純物を拡散させてｐ型不純物拡散領域６５を形成する。 Next, as shown in FIG. 20, by flowing a p-type impurity-containing gas 66, the first of the semiconductor substrate 1 exposed from the opening 61 b of the diffusion suppression mask 62 on the first main surface 1 b of the semiconductor substrate 1. A p-type impurity diffusion region 65 is formed by diffusing p-type impurities in main surface 1b.
次に、図２１に示すように、半導体基板１の第２主面１ａおよび第１主面１ｂの拡散抑制マスク６２をすべて除去する。次に、図２２に示すように、半導体基板１の第１主面１ｂの全面に誘電体膜６７を形成する。 Next, as shown in FIG. 21, all the diffusion suppression masks 62 on the second main surface 1a and the first main surface 1b of the semiconductor substrate 1 are removed. Next, as shown in FIG. 22, a dielectric film 67 is formed on the entire first main surface 1 b of the semiconductor substrate 1.
次に、図２３に示すように、半導体基板１の第２主面１ａをテクスチャエッチングすることによってテクスチャ構造６８を形成する。 Next, as shown in FIG. 23, the texture structure 68 is formed by texture-etching the second main surface 1a of the semiconductor substrate 1.
次に、図２４に示すように、半導体基板１の第２主面１ａのテクスチャ構造６８上に誘電体膜６９を形成する。次に、図２５に示すように、半導体基板１の第１主面１ｂの誘電体膜６７の一部を除去することによってコンタクトホール７０，７１を形成する。なお、コンタクトホール７０，７１の形成方法は、特に限定されず、たとえばフォトリソグラフィ等の方法を用いることができる。 Next, as shown in FIG. 24, a dielectric film 69 is formed on the texture structure 68 of the second main surface 1 a of the semiconductor substrate 1. Next, as shown in FIG. 25, contact holes 70 and 71 are formed by removing a part of the dielectric film 67 on the first main surface 1 b of the semiconductor substrate 1. In addition, the formation method of the contact holes 70 and 71 is not specifically limited, For example, methods, such as photolithography, can be used.
次に、図２６に示すように、コンタクトホール７１を通してｐ型不純物拡散領域６５に接する第１の銀層７ａを形成するとともに、コンタクトホール７０を通してｎ型不純物拡散領域６３に接する第２の銀層８ａを形成する。 Next, as shown in FIG. 26, a first silver layer 7a in contact with p-type impurity diffusion region 65 is formed through contact hole 71, and a second silver layer in contact with n-type impurity diffusion region 63 through contact hole 70 is formed. 8a is formed.
その後、第１の銀層７ａおよび第２の銀層８ａを半導体基板１とともにアニールする。これにより、ｐ型不純物拡散領域６５から第１の銀層７ａにＳｉが移動して第１の銀層７ａにＳｉが取り込まれて第１電極７が形成され、ｎ型不純物拡散領域６３から第２の銀層８ａにＳｉが移動して第２の銀層８ａにＳｉが取り込まれて第２電極８が形成される。以上により、実施形態４の裏面電極型太陽電池セルが完成する。 Thereafter, the first silver layer 7 a and the second silver layer 8 a are annealed together with the semiconductor substrate 1. As a result, Si moves from the p-type impurity diffusion region 65 to the first silver layer 7a, and Si is taken into the first silver layer 7a to form the first electrode 7. The first electrode 7 is formed from the n-type impurity diffusion region 63. Si moves to the second silver layer 8a, and Si is taken into the second silver layer 8a to form the second electrode 8. Thus, the back electrode type solar battery cell of Embodiment 4 is completed.
実施形態４における上記以外の説明は、実施形態１〜実施形態３と同様であるため、その説明については繰り返さない。 Since the description other than the above in Embodiment 4 is the same as that in Embodiments 1 to 3, the description thereof will not be repeated.
［実施形態５］
図２７に、実施形態の光電変換素子の他の一例である実施形態５の両面電極型太陽電池セルの模式的な断面図を示す。図２７に示すように、実施形態５の両面電極型太陽電池セルは、ｐ型単結晶または多結晶シリコン基板からなる半導体基板１と、半導体基板１の裏面となる第１主面１ｂ内に設けられた第１導電型不純物含有領域としてのｐ型不純物拡散領域６５と、半導体基板１の受光面となる第２主面１ａ内に設けられた第２導電型不純物含有領域としてのｎ型不純物拡散領域６３とを備えている。また、ｐ型不純物拡散領域６５に接してＡｇとＳｉとを含む第１電極７が設けられており、ｎ型不純物拡散領域６３に接してＡｇとＳｉとを含む第２電極８が設けられている。なお、ｐ型不純物拡散領域６５は、たとえば、半導体基板１の第１主面１ｂ内にｐ型不純物を拡散することにより形成することができる。また、ｎ型不純物拡散領域６３は、たとえば、半導体基板１の第２主面１ａ内にｎ型不純物を拡散することにより形成することができる。[Embodiment 5]
FIG. 27 shows a schematic cross-sectional view of a double-sided electrode type solar battery cell of Embodiment 5, which is another example of the photoelectric conversion element of the embodiment. As shown in FIG. 27, the double-sided electrode solar cell of Embodiment 5 is provided in a semiconductor substrate 1 made of a p-type single crystal or polycrystalline silicon substrate, and in a first main surface 1b which is the back surface of the semiconductor substrate 1. P-type impurity diffusion region 65 as the first conductivity type impurity containing region and n type impurity diffusion as the second conductivity type impurity containing region provided in the second main surface 1a serving as the light receiving surface of the semiconductor substrate 1 Region 63. A first electrode 7 containing Ag and Si is provided in contact with the p-type impurity diffusion region 65, and a second electrode 8 containing Ag and Si is provided in contact with the n-type impurity diffusion region 63. Yes. The p-type impurity diffusion region 65 can be formed, for example, by diffusing a p-type impurity in the first main surface 1b of the semiconductor substrate 1. The n-type impurity diffusion region 63 can be formed, for example, by diffusing an n-type impurity in the second main surface 1a of the semiconductor substrate 1.
実施形態５における上記以外の説明は、実施形態１〜実施形態４と同様であるため、その説明については繰り返さない。 Since the description other than the above in Embodiment 5 is the same as that in Embodiments 1 to 4, the description thereof will not be repeated.
［付記］
（１）ここで開示された実施形態は、第１導電型または第２導電型の半導体基板と、半導体基板の第１主面の面内または面上の第１導電型領域と、半導体基板の第１主面の面内若しくは面上、または第１主面とは異なる第２主面の面内若しくは面上の第２導電型領域と、第１導電型領域上の電極と、第２導電型領域上の電極とを備え、電極の少なくとも１つが、銀と、シリコンとを含む光電変換素子である。このような構成とすることにより、電極のコンタクト抵抗を低減することができる。[Appendix]
(1) An embodiment disclosed herein includes a semiconductor substrate of a first conductivity type or a second conductivity type, a first conductivity type region in or on a surface of a first main surface of the semiconductor substrate, and a semiconductor substrate A second conductivity type region in or on the surface of the first main surface, or in or on the second main surface different from the first main surface, an electrode on the first conductivity type region, and a second conductivity And an electrode on the mold region, and at least one of the electrodes is a photoelectric conversion element containing silver and silicon. With such a configuration, the contact resistance of the electrode can be reduced.
（２）ここで開示された実施形態の光電変換素子において、電極の少なくとも１つは、半導体基板から離れるにしたがってシリコンの濃度が減少する部分を含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (2) In the photoelectric conversion element of the embodiment disclosed herein, at least one of the electrodes may include a portion where the concentration of silicon decreases as the distance from the semiconductor substrate increases. Also in this case, the contact resistance of the electrode can be reduced.
（３）ここで開示された実施形態の光電変換素子において、第１導電型領域は第１導電型非晶質シリコン膜を含み、第２導電型領域は第２導電型非晶質シリコン膜を含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (3) In the photoelectric conversion element of the embodiment disclosed herein, the first conductivity type region includes the first conductivity type amorphous silicon film, and the second conductivity type region includes the second conductivity type amorphous silicon film. May be included. Also in this case, the contact resistance of the electrode can be reduced.
（４）ここで開示された実施形態の光電変換素子において、電極は、第１導電型非晶質シリコン膜上の第１電極と、第２導電型非晶質シリコン膜上の第２電極とを含み、第１電極および第２電極の少なくとも一方が、銀と、シリコンとを含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (4) In the photoelectric conversion element of the embodiment disclosed herein, the electrodes include a first electrode on the first conductivity type amorphous silicon film, and a second electrode on the second conductivity type amorphous silicon film. And at least one of the first electrode and the second electrode may contain silver and silicon. Also in this case, the contact resistance of the electrode can be reduced.
（５）ここで開示された実施形態の光電変換素子において、第１電極が第１導電型非晶質シリコン膜に接していてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (5) In the photoelectric conversion element of the embodiment disclosed herein, the first electrode may be in contact with the first conductivity type amorphous silicon film. Also in this case, the contact resistance of the electrode can be reduced.
（６）ここで開示された実施形態の光電変換素子は、第１電極と第１導電型非晶質シリコン膜との間の少なくとも一部の領域に第１の介在層をさらに備え、第１の介在層がチタンを含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (6) The photoelectric conversion element of the embodiment disclosed herein further includes a first intervening layer in at least a part of the region between the first electrode and the first conductivity type amorphous silicon film. The intervening layer may contain titanium. Also in this case, the contact resistance of the electrode can be reduced.
（７）ここで開示された実施形態の光電変換素子は、第１電極と第１導電型非晶質シリコン膜との間のすべての領域に第１の介在層をさらに備えていてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (7) The photoelectric conversion element of the embodiment disclosed herein may further include a first intervening layer in all regions between the first electrode and the first conductivity type amorphous silicon film. Also in this case, the contact resistance of the electrode can be reduced.
（８）ここで開示された実施形態の光電変換素子は、第１電極と第１導電型非晶質シリコン膜との間の一部の領域に第１の介在層をさらに備えていてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (8) The photoelectric conversion element of the embodiment disclosed herein may further include a first intervening layer in a partial region between the first electrode and the first conductivity type amorphous silicon film. . Also in this case, the contact resistance of the electrode can be reduced.
（９）ここで開示された実施形態の光電変換素子においては、第２電極が第２導電型非晶質シリコン膜に接していてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (9) In the photoelectric conversion element of the embodiment disclosed herein, the second electrode may be in contact with the second conductivity type amorphous silicon film. Also in this case, the contact resistance of the electrode can be reduced.
（１０）ここで開示された実施形態の光電変換素子は、第２電極と第２導電型非晶質シリコン膜との間の少なくとも一部の領域に第２の介在層をさらに備えていてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (10) The photoelectric conversion element of the embodiment disclosed herein may further include a second intervening layer in at least a partial region between the second electrode and the second conductivity type amorphous silicon film. Good. Also in this case, the contact resistance of the electrode can be reduced.
（１１）ここで開示された実施形態の光電変換素子は、第２電極と第２導電型非晶質シリコン膜との間のすべての領域に第２の介在層をさらに備えていてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (11) The photoelectric conversion element of the embodiment disclosed herein may further include a second intervening layer in all regions between the second electrode and the second conductivity type amorphous silicon film. Also in this case, the contact resistance of the electrode can be reduced.
（１２）ここで開示された実施形態の光電変換素子は、第２電極と第２導電型非晶質シリコン膜との間の一部の領域に第２の介在層をさらに備えていてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (12) The photoelectric conversion element of the embodiment disclosed herein may further include a second intervening layer in a partial region between the second electrode and the second conductivity type amorphous silicon film. . Also in this case, the contact resistance of the electrode can be reduced.
（１３）ここで開示された実施形態の光電変換素子においては、第２の介在層がチタンを含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (13) In the photoelectric conversion element of the embodiment disclosed herein, the second intervening layer may contain titanium. Also in this case, the contact resistance of the electrode can be reduced.
（１４）ここで開示された実施形態の光電変換素子は、半導体基板と第１導電型非晶質シリコン膜との間に第１のｉ型非晶質シリコン膜をさらに備えていてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (14) The photoelectric conversion element of the embodiment disclosed herein may further include a first i-type amorphous silicon film between the semiconductor substrate and the first conductive amorphous silicon film. Also in this case, the contact resistance of the electrode can be reduced.
（１５）ここで開示された実施形態の光電変換素子において、第１のｉ型非晶質シリコン膜は、半導体基板と第１導電型非晶質シリコン膜とのそれぞれに接していてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (15) In the photoelectric conversion element of the embodiment disclosed herein, the first i-type amorphous silicon film may be in contact with each of the semiconductor substrate and the first conductivity-type amorphous silicon film. Also in this case, the contact resistance of the electrode can be reduced.
（１６）ここで開示された実施形態の光電変換素子は、半導体基板と第２導電型非晶質シリコン膜との間に第２のｉ型非晶質シリコン膜をさらに備えていてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (16) The photoelectric conversion element of the embodiment disclosed herein may further include a second i-type amorphous silicon film between the semiconductor substrate and the second conductivity type amorphous silicon film. Also in this case, the contact resistance of the electrode can be reduced.
（１７）ここで開示された実施形態の光電変換素子において、第２のｉ型非晶質シリコン膜は、半導体基板と第２導電型非晶質シリコン膜とのそれぞれに接していてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (17) In the photoelectric conversion element of the embodiment disclosed herein, the second i-type amorphous silicon film may be in contact with each of the semiconductor substrate and the second conductivity-type amorphous silicon film. Also in this case, the contact resistance of the electrode can be reduced.
（１８）ここで開示された実施形態の光電変換素子において、半導体基板は、シリコンを含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (18) In the photoelectric conversion element of the embodiment disclosed here, the semiconductor substrate may contain silicon. Also in this case, the contact resistance of the electrode can be reduced.
（１９）ここで開示された実施形態は、第１導電型または第２導電型の半導体基板の半導体基板の第１主面の面内または面上に第１導電型領域を形成する工程と、半導体基板の第１主面の面内若しくは面上、または第１主面とは異なる第２主面の面内若しくは面上に第２導電型領域を形成する工程と、第１導電型領域上および第２導電型領域上にそれぞれ電極を形成する工程とを備え、電極の少なくとも１つが、銀と、シリコンとを含む光電変換素子である。このような構成とすることにより、電極のコンタクト抵抗を低減することができる。 (19) An embodiment disclosed herein includes a step of forming a first conductivity type region in or on a surface of a first main surface of a semiconductor substrate of a semiconductor substrate of a first conductivity type or a second conductivity type; Forming a second conductivity type region in or on the surface of the first main surface of the semiconductor substrate, or in a surface of the second main surface different from the first main surface, and on the first conductivity type region; And a step of forming electrodes on the second conductivity type regions, respectively, and at least one of the electrodes is a photoelectric conversion element containing silver and silicon. With such a configuration, the contact resistance of the electrode can be reduced.
（２０）ここで開示された実施形態においては、第２導電型領域が第１主面の面内に設けられていてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (20) In the embodiment disclosed herein, the second conductivity type region may be provided in the plane of the first main surface. Also in this case, the contact resistance of the electrode can be reduced.
（２１）ここで開示された実施形態においては、電極の少なくとも１つの厚さが２０μｍ以下であってもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (21) In the embodiment disclosed herein, the thickness of at least one of the electrodes may be 20 μm or less. Also in this case, the contact resistance of the electrode can be reduced.
（２２）ここで開示された実施形態の光電変換素子の製造方法において、第１導電型領域および第２導電型領域を形成する工程は、半導体基板の一方の面側に第１導電型非晶質シリコン膜を形成する工程と、半導体基板の一方の面側に第２導電型非晶質シリコン膜を形成する工程とを含み、電極を形成する工程は、第１導電型非晶質シリコン膜上に第１銀含有層を形成する工程と、第２導電型非晶質シリコン膜上に第２銀含有層を形成する工程とを含むとともに、第１導電型非晶質シリコン膜および第１銀含有層をアニールすることによって第１導電型非晶質シリコン膜上に銀とシリコンとを含む第１電極を形成する工程、および第２導電型非晶質シリコン膜および第２銀含有層をアニールすることによって第２導電型非晶質シリコン膜上に銀とシリコンとを含む第２電極を形成する工程の少なくとも一方の工程を含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (22) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of forming the first conductivity type region and the second conductivity type region includes the first conductivity type amorphous on one surface side of the semiconductor substrate. The step of forming an electrode includes the step of forming a porous silicon film and the step of forming a second conductivity type amorphous silicon film on one surface side of the semiconductor substrate. A step of forming a first silver-containing layer on the second conductive-type amorphous silicon film; and a step of forming a second silver-containing layer on the second conductive-type amorphous silicon film. Forming a first electrode containing silver and silicon on the first conductive amorphous silicon film by annealing the silver-containing layer; and a second conductive amorphous silicon film and a second silver-containing layer. On the second conductive type amorphous silicon film by annealing At least one of the steps of forming a second electrode containing silicon and may contain. Also in this case, the contact resistance of the electrode can be reduced.
（２３）ここで開示された実施形態の光電変換素子の製造方法において、第１銀含有層を形成する工程は、第１導電型非晶質シリコン膜に接するように第１銀含有層を形成する工程を含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (23) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of forming the first silver-containing layer forms the first silver-containing layer so as to be in contact with the first conductivity type amorphous silicon film. The process of carrying out may be included. Also in this case, the contact resistance of the electrode can be reduced.
（２４）ここで開示された実施形態の光電変換素子の製造方法において、第１銀含有層を形成する工程は、第１導電型非晶質シリコン膜上の少なくとも一部の領域に第１の介在層を形成する工程と、第１の介在層が形成された第１導電型非晶質シリコン膜上に第１銀含有層を形成する工程とを含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (24) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of forming the first silver-containing layer includes the step of forming the first silver in at least a part of the region on the first conductivity type amorphous silicon film. A step of forming an intervening layer and a step of forming a first silver-containing layer on the first conductive type amorphous silicon film on which the first intervening layer is formed may be included. Also in this case, the contact resistance of the electrode can be reduced.
（２５）ここで開示された実施形態の光電変換素子の製造方法において、第２銀含有層を形成する工程は、第２導電型非晶質シリコン膜に接するように第２銀含有層を形成する工程を含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (25) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of forming the second silver-containing layer forms the second silver-containing layer so as to be in contact with the second conductivity type amorphous silicon film. The process of carrying out may be included. Also in this case, the contact resistance of the electrode can be reduced.
（２６）ここで開示された実施形態の光電変換素子の製造方法において、第２銀含有層を形成する工程は、第２導電型非晶質シリコン膜上の少なくとも一部の領域に第２の介在層を形成する工程と、第２の介在層が形成された第２導電型非晶質シリコン膜上に第２銀含有層を形成する工程とを含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (26) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of forming the second silver-containing layer includes the step of forming the second silver in at least a part of the region on the second conductivity type amorphous silicon film. There may be included a step of forming an intervening layer and a step of forming a second silver-containing layer on the second conductive type amorphous silicon film in which the second intervening layer is formed. Also in this case, the contact resistance of the electrode can be reduced.
（２７）ここで開示された実施形態の光電変換素子の製造方法において、半導体基板と第１導電型非晶質シリコン膜との間に第１のｉ型非晶質シリコン膜を形成する工程をさらに含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (27) In the method for manufacturing a photoelectric conversion element according to the embodiment disclosed herein, a step of forming a first i-type amorphous silicon film between the semiconductor substrate and the first conductive amorphous silicon film. Further, it may be included. Also in this case, the contact resistance of the electrode can be reduced.
（２８）ここで開示された実施形態の光電変換素子の製造方法において、半導体基板と第２導電型非晶質シリコン膜との間に第２のｉ型非晶質シリコン膜を形成する工程をさらに含んでいてもよい。この場合にも、電極のコンタクト抵抗を低減することができる。 (28) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, a step of forming a second i-type amorphous silicon film between the semiconductor substrate and the second conductive amorphous silicon film. Further, it may be included. Also in this case, the contact resistance of the electrode can be reduced.
以上のように実施形態について説明を行なったが、上述の各実施形態の構成を適宜組み合わせることも当初から予定している。 Although the embodiment has been described as described above, it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments.
今回開示された実施形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 It should be thought that embodiment disclosed this time is an illustration and restrictive at no points. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
ここで開示された実施形態は、光電変換素子および光電変換素子の製造方法に利用することができ、好適には裏面電極型または両面電極型の太陽電池および裏面電極型または両面電極型の太陽電池の製造方法に利用できる可能性があり、特に好適にはヘテロ接合型バックコンタクトセルおよびヘテロ接合型バックコンタクトセルに利用できる可能性がある。 Embodiment disclosed here can be utilized for the manufacturing method of a photoelectric conversion element and a photoelectric conversion element, and preferably a back electrode type or a double-sided electrode type solar cell and a back electrode type or a double-sided electrode type solar cell In particular, it may be used for heterojunction back contact cells and heterojunction back contact cells.
１ 半導体基板、１ａ 第２主面、１ｂ 第１主面、２ 第１のｉ型非晶質半導体膜、３ 第１導電型非晶質半導体膜、４ 第２のｉ型非晶質半導体膜、５ 第２導電型非晶質半導体膜、７ 第１電極、７ａ 第１の銀層、８ 第２電極、８ａ 第２の銀層、９ａ 第１の介在層、９ｂ 第２の介在層、３１，３２ エッチングマスク、５１ 第１の積層体、５２ 第２の積層体、６１ａ，６１ｂ 開口部、６２ 拡散マスク、６３ ｎ型不純物拡散領域、６４ ｎ型不純物含有ガス、６５ ｐ型不純物拡散領域、６６ ｐ型不純物含有ガス、６７ 誘電体膜、６８ テクスチャ構造、６９ 誘電体膜、７０，７１ コンタクトホール、１１１ 半導体基板、１１２ ｉ型非晶質半導体層、１１３ ｉ型非晶質半導体層、１１４ ｎ型非晶質半導体層、１１５ ｐ型非晶質半導体層、１１６ ｎ側電極、１１６ａ 第１導電層、１１６ｂ 第２導電層、１１６ｃ 第３導電層、１１６ｄ 第４導電層、１１７ ｐ側電極、１１７ａ 第１導電層、１１７ｂ 第２導電層、１１７ｃ 第３導電層、１１７ｄ 第４導電層、１１９ ｉ型非晶質半導体層、１２０ ｎ型非晶質半導体層、１２１ 絶縁層、１２２ ＩＮ積層体、１２３ ＩＰ積層体、１２４ 絶縁層。 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 1a 2nd main surface, 1b 1st main surface, 1st i type amorphous semiconductor film, 3 1st conductivity type amorphous semiconductor film, 4 2nd i type amorphous semiconductor film 5 second conductive type amorphous semiconductor film, 7 first electrode, 7a first silver layer, 8 second electrode, 8a second silver layer, 9a first intervening layer, 9b second intervening layer, 31, 32 Etching mask, 51 1st laminated body, 52 2nd laminated body, 61a, 61b opening, 62 diffusion mask, 63 n-type impurity diffusion region, 64 n-type impurity containing gas, 65 p-type impurity diffusion region , 66 p-type impurity-containing gas, 67 dielectric film, 68 texture structure, 69 dielectric film, 70, 71 contact hole, 111 semiconductor substrate, 112 i-type amorphous semiconductor layer, 113 i-type amorphous semiconductor layer, 114 n-type amorphous semiconductor layer, 115 p Amorphous semiconductor layer, 116 n-side electrode, 116a first conductive layer, 116b second conductive layer, 116c third conductive layer, 116d fourth conductive layer, 117 p-side electrode, 117a first conductive layer, 117b second conductive Layer, 117c third conductive layer, 117d fourth conductive layer, 119 i-type amorphous semiconductor layer, 120 n-type amorphous semiconductor layer, 121 insulating layer, 122 IN stacked body, 123 IP stacked body, 124 insulating layer.
Claims (8)
前記半導体基板の第１主面の面内または面上の第１導電型領域と、
前記半導体基板の前記第１主面の面内若しくは面上、または前記第１主面とは異なる第２主面の面内若しくは面上の第２導電型領域と、
前記第１導電型領域上の電極と、
前記第２導電型領域上の電極と、を備え、
前記電極の少なくとも１つが、銀と、シリコンとを含み、
前記電極の少なくとも１つは、前記半導体基板から離れるにしたがって前記シリコンの濃度が減少する部分を含む、光電変換素子。A semiconductor substrate of a first conductivity type or a second conductivity type;
A first conductivity type region in or on the first main surface of the semiconductor substrate;
A second conductivity type region in or on the first main surface of the semiconductor substrate, or in or on the second main surface different from the first main surface;
An electrode on the first conductivity type region;
An electrode on the second conductivity type region,
At least one of the electrodes comprises silver and silicon;
The photoelectric conversion element, wherein at least one of the electrodes includes a portion where the concentration of the silicon decreases as the distance from the semiconductor substrate increases.
前記第２導電型領域は、第２導電型非晶質シリコン膜を含む、請求項１に記載の光電変換素子。The first conductivity type region includes a first conductivity type amorphous silicon film,
The photoelectric conversion element according to claim 1, wherein the second conductivity type region includes a second conductivity type amorphous silicon film.
前記第１電極および前記第２電極の少なくとも一方が、銀と、シリコンとを含む、請求項２に記載の光電変換素子。The electrode includes a first electrode on the first conductivity type amorphous silicon film and a second electrode on the second conductivity type amorphous silicon film,
The photoelectric conversion element according to claim 2, wherein at least one of the first electrode and the second electrode includes silver and silicon.
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