JPS649560A - Input and output control circuit - Google Patents

Input and output control circuit

Info

Publication number
JPS649560A
JPS649560A JP16593487A JP16593487A JPS649560A JP S649560 A JPS649560 A JP S649560A JP 16593487 A JP16593487 A JP 16593487A JP 16593487 A JP16593487 A JP 16593487A JP S649560 A JPS649560 A JP S649560A
Authority
JP
Japan
Prior art keywords
data
data signal
control circuit
input
output control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16593487A
Other languages
Japanese (ja)
Inventor
Tooru Motosu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16593487A priority Critical patent/JPS649560A/en
Publication of JPS649560A publication Critical patent/JPS649560A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To attain high speed data transfer without being affected by the length of a cable by sampling an effective data from each data signal and adjusting mismatching of a propagation time of a parallel data signals by a buffer. CONSTITUTION:Reception means 4-1-4-n of an input/output control circuit 1 sample an effective data from a data signal on each data signal line and stores in a data buffer 7. The data signal is a signal having information in the pulse width and samples the data by detecting a leading on data signal line. The serial data number sampled on each data signal line is counted synchronously with the synchronizing clock of an input/output control circuit and the result of count is inputted to a parallel data count means 6 counting the parallel data of the data signal of plural bits synchronously with the synchronizing clock of the input/output control circuit 1 and in detecting the arrival of the lowest data signal, the means 6 synchronizes it as the parallel data and sends the result to a host device from a data buffer 7. Thus, high speed data transmission is attained.
JP16593487A 1987-07-01 1987-07-01 Input and output control circuit Pending JPS649560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16593487A JPS649560A (en) 1987-07-01 1987-07-01 Input and output control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16593487A JPS649560A (en) 1987-07-01 1987-07-01 Input and output control circuit

Publications (1)

Publication Number Publication Date
JPS649560A true JPS649560A (en) 1989-01-12

Family

ID=15821792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16593487A Pending JPS649560A (en) 1987-07-01 1987-07-01 Input and output control circuit

Country Status (1)

Country Link
JP (1) JPS649560A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100240248B1 (en) * 1997-02-14 2000-01-15 윤종용 Data transmit/receive apparatus and data transmit/receive method
WO2011136298A1 (en) 2010-04-28 2011-11-03 芦森工業株式会社 Method of manufacturing cushion for front passenger seat air bag device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100240248B1 (en) * 1997-02-14 2000-01-15 윤종용 Data transmit/receive apparatus and data transmit/receive method
WO2011136298A1 (en) 2010-04-28 2011-11-03 芦森工業株式会社 Method of manufacturing cushion for front passenger seat air bag device

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