JPS6489868A - Video signal processing circuit - Google Patents

Video signal processing circuit

Info

Publication number
JPS6489868A
JPS6489868A JP62246914A JP24691487A JPS6489868A JP S6489868 A JPS6489868 A JP S6489868A JP 62246914 A JP62246914 A JP 62246914A JP 24691487 A JP24691487 A JP 24691487A JP S6489868 A JPS6489868 A JP S6489868A
Authority
JP
Japan
Prior art keywords
signal
level
signal level
video signal
advance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62246914A
Other languages
Japanese (ja)
Inventor
Shinji Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62246914A priority Critical patent/JPS6489868A/en
Publication of JPS6489868A publication Critical patent/JPS6489868A/en
Pending legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE:To prevent deterioration of picture quality of a reproduced video image in advance by setting a signal level of a blanking period to a prescribed value aud applying digital signal processing and adding a reference synchronizing signal. CONSTITUTION:A clamp circuit 21 clamping a pedestal level of an analog video signal SY to a prescribed signal level and a blanking circuit 22 replacing the signal level of horizontal and vertical blanking periods of an analog video signal outputted from the clamp circuit 21 into a prescribed signal level are provided. The signal level of the horizontal and vertical blanking periods to a prescribed value in the stage of the analog video signal SY and analog/digital conversion is processed and reference synchronizing signals DSYNC, DB1 are added. Thus, the shift in the pedestal level due to quantization error is prevented in advance to replace the synchronizing signal DSYNC, DB1 surely and the deterioration in the picture quality of the reproduced video image is prevented in advance.
JP62246914A 1987-09-30 1987-09-30 Video signal processing circuit Pending JPS6489868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62246914A JPS6489868A (en) 1987-09-30 1987-09-30 Video signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62246914A JPS6489868A (en) 1987-09-30 1987-09-30 Video signal processing circuit

Publications (1)

Publication Number Publication Date
JPS6489868A true JPS6489868A (en) 1989-04-05

Family

ID=17155629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62246914A Pending JPS6489868A (en) 1987-09-30 1987-09-30 Video signal processing circuit

Country Status (1)

Country Link
JP (1) JPS6489868A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104739A (en) * 2009-12-22 2011-06-22 索尼公司 Transmission system, imaging apparatus, and transmission method
US11803377B2 (en) 2017-09-08 2023-10-31 Oracle International Corporation Efficient direct convolution using SIMD instructions

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104739A (en) * 2009-12-22 2011-06-22 索尼公司 Transmission system, imaging apparatus, and transmission method
US11803377B2 (en) 2017-09-08 2023-10-31 Oracle International Corporation Efficient direct convolution using SIMD instructions

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