JPS6482546A - Method of positioning terminal of semiconductor integrated circuit - Google Patents

Method of positioning terminal of semiconductor integrated circuit

Info

Publication number
JPS6482546A
JPS6482546A JP62238836A JP23883687A JPS6482546A JP S6482546 A JPS6482546 A JP S6482546A JP 62238836 A JP62238836 A JP 62238836A JP 23883687 A JP23883687 A JP 23883687A JP S6482546 A JPS6482546 A JP S6482546A
Authority
JP
Japan
Prior art keywords
terminals
regions
wiring
positions
spaces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62238836A
Other languages
Japanese (ja)
Other versions
JP2703233B2 (en
Inventor
Masako Murofushi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62238836A priority Critical patent/JP2703233B2/en
Publication of JPS6482546A publication Critical patent/JPS6482546A/en
Application granted granted Critical
Publication of JP2703233B2 publication Critical patent/JP2703233B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce wiring length and wiring regions among blocks without increasing wiring regions in blocks by estimating a passable region on a cell line, computing the constraint of the spaces of the positions of terminals and keeping the spaces of the positions of the terminals at a constraint value or more when the positions of the terminals are determined. CONSTITUTION:1. the mean value of regions in which a wiring 8 can pass on a cell line 9 is obtained. 2. the constrain value of the spaces of the positions of terminals is acquired on the basis of the mean value. 3. an integrated region in which terminals are not separated at the constraint value or more is obtained. 4. the centers of gravity (m)=(positions of terminals)divided by (number of terminals in regions) of terminals in each region acquired by 3 are obtained. 5. respective region acquired by 3 is extended so as to satisfy the constraint value of the spaces of the terminals centering around (m). 6. when the extended regions are extruded from existence sides or the regions are made mutually to collide, the regions are adjusted. Accordingly, the wiring 8 connecting a cell 1a in a block and a block terminal 5b is not bent more than required, thus reducing wiring regions in the block.
JP62238836A 1987-09-25 1987-09-25 Method for determining terminal position of semiconductor integrated circuit Expired - Fee Related JP2703233B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62238836A JP2703233B2 (en) 1987-09-25 1987-09-25 Method for determining terminal position of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62238836A JP2703233B2 (en) 1987-09-25 1987-09-25 Method for determining terminal position of semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS6482546A true JPS6482546A (en) 1989-03-28
JP2703233B2 JP2703233B2 (en) 1998-01-26

Family

ID=17035997

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62238836A Expired - Fee Related JP2703233B2 (en) 1987-09-25 1987-09-25 Method for determining terminal position of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2703233B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61283143A (en) * 1985-06-10 1986-12-13 Nec Corp Semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61283143A (en) * 1985-06-10 1986-12-13 Nec Corp Semiconductor integrated circuit

Also Published As

Publication number Publication date
JP2703233B2 (en) 1998-01-26

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees