JPS6481423A - Multiplexing system - Google Patents
Multiplexing systemInfo
- Publication number
- JPS6481423A JPS6481423A JP23950387A JP23950387A JPS6481423A JP S6481423 A JPS6481423 A JP S6481423A JP 23950387 A JP23950387 A JP 23950387A JP 23950387 A JP23950387 A JP 23950387A JP S6481423 A JPS6481423 A JP S6481423A
- Authority
- JP
- Japan
- Prior art keywords
- call processing
- layer
- processing signal
- circuit
- flag
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Time-Division Multiplex Systems (AREA)
Abstract
PURPOSE:To reduce a band for call processing signal transmission by providing serial data interface circuits which detect the flag and bit error of a layer of a call signal and a LAP-D circuit which is connected to a multiplex circuit and terminates the layer of the call processing signal on a PCM transmission line. CONSTITUTION:This system has the serial data interface circuits 3-m and 3-n which detect the flag and bit error of the layer 2 of the call processing signal on the digital subscriber line, the multiplex circuit 4 which are connected to the serial data interface circuits 3-m and 3-n and adds, decides, and demultiplexes the number of a digital subscriber line corresponding to the call processing signal, and the LAP-D circuit 5 which is connected to the multiplex circuit 4 and terminates the flag of the layer 2 of the call processing signal on the PCM transmission line 7. Consequently, the band which contains call processing signals on a 1st-order or high-order group PCM transmission line is made smaller than the sum of bands containing call processing signals on digital subscriber lines to be multiplexed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23950387A JPH0785554B2 (en) | 1987-09-22 | 1987-09-22 | Multiplex system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23950387A JPH0785554B2 (en) | 1987-09-22 | 1987-09-22 | Multiplex system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6481423A true JPS6481423A (en) | 1989-03-27 |
JPH0785554B2 JPH0785554B2 (en) | 1995-09-13 |
Family
ID=17045756
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23950387A Expired - Lifetime JPH0785554B2 (en) | 1987-09-22 | 1987-09-22 | Multiplex system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0785554B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03104334A (en) * | 1989-09-19 | 1991-05-01 | Fujitsu Ltd | Control channel termination system |
-
1987
- 1987-09-22 JP JP23950387A patent/JPH0785554B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03104334A (en) * | 1989-09-19 | 1991-05-01 | Fujitsu Ltd | Control channel termination system |
Also Published As
Publication number | Publication date |
---|---|
JPH0785554B2 (en) | 1995-09-13 |
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