JPS6477241A - Phase matching circuit - Google Patents
Phase matching circuitInfo
- Publication number
- JPS6477241A JPS6477241A JP62232483A JP23248387A JPS6477241A JP S6477241 A JPS6477241 A JP S6477241A JP 62232483 A JP62232483 A JP 62232483A JP 23248387 A JP23248387 A JP 23248387A JP S6477241 A JPS6477241 A JP S6477241A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- phase
- data
- output buffer
- phase matching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To automatically perform phase matching by outputting data as it is in case of a second clock having the same phase as a first clock but outputting data after phase shift in case of the second clock having a phase opposite to that of the first clock. CONSTITUTION:An input buffer 31 into which a first data D1 synchronized with a first clock CK1 is taken is provided on the input side, and an output buffer 32 from which second data D2 synchronized with a second clock CK2 is sent is provided on the output side. The first clock CK1 and the second clock CK2 are compared and discriminated by a phase discriminating part 33, and first data is transferred to the output buffer 32 as it is if the clock CK2 has the same phase as the clock CK1, but first data D1 has the phase shifted and is transferred to the output buffer 32 if the clock CK2 has a phase opposite to that of the clock CK1. This control is performed by a phase control part 34. Thus, phase matching is performed in an inexpensive and small-scale constitution by complete automatic processing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62232483A JPH084259B2 (en) | 1987-09-18 | 1987-09-18 | Phase matching circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62232483A JPH084259B2 (en) | 1987-09-18 | 1987-09-18 | Phase matching circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6477241A true JPS6477241A (en) | 1989-03-23 |
JPH084259B2 JPH084259B2 (en) | 1996-01-17 |
Family
ID=16940016
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62232483A Expired - Lifetime JPH084259B2 (en) | 1987-09-18 | 1987-09-18 | Phase matching circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH084259B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5056120A (en) * | 1988-07-18 | 1991-10-08 | Fujitsu Limited | Phase adjusting circuit |
-
1987
- 1987-09-18 JP JP62232483A patent/JPH084259B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5056120A (en) * | 1988-07-18 | 1991-10-08 | Fujitsu Limited | Phase adjusting circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH084259B2 (en) | 1996-01-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0307166A3 (en) | Data processor | |
EP0351779A3 (en) | Phase adjusting circuit | |
DE3888703D1 (en) | ECL-compatible input / output circuits in CMOS technology. | |
EP0895356A3 (en) | Signal change detection circuit | |
ES8602332A1 (en) | Signal processing circuit | |
JPS56147260A (en) | Lsi for digital signal processing | |
JPS5674668A (en) | Logical device | |
EP0379279A3 (en) | Data transmission synchroniser | |
JPS6477241A (en) | Phase matching circuit | |
JPS5718169A (en) | Synchronizing circuit of video control data | |
KR940001556B1 (en) | Digital signal processing apparatus | |
JPS6453273A (en) | Image data memory circuit in image processor | |
JPS5787617A (en) | Phase shift circuit | |
JPS5621440A (en) | Stuff synchronizing system | |
JPS5685127A (en) | Digital signal processor | |
JPS572148A (en) | Ternary-to-binary code converting device | |
JPS51129160A (en) | Phase sychronize circuit | |
JPS537165A (en) | Synchronism detecting circuit of phase control circuit | |
JPS57116431A (en) | Programmable logic array | |
SU818017A1 (en) | Logic ''m from n''device | |
DE59008629D1 (en) | Synchronization device for high data rates. | |
SU855963A2 (en) | Clock pulse generator | |
JPS60123931A (en) | Arithmetic circuit | |
JPS5624630A (en) | Plural input and output device control system | |
JPS5638645A (en) | Digital output change-over system in duplex system |